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Commit d8d8ccf2 authored by Bert Kenward's avatar Bert Kenward Committed by David S. Miller
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sfc: update EF10 register definitions 

The RX_L4_CLASS field has shrunk from 3 bits to 2 bits. The upper
bit was never used in previous hardware, so we can use the new
definition throughout.

The TSO OUTER_IPID field was previously spelt differently from the
external definitions.
Signed-off-by: default avatarEdward Cree <ecree@solarflare.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent acaef3c1
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Showing with 37 additions and 25 deletions
drivers/net/ethernet/sfc/ef10.c
View file @ d8d8ccf2
...@@ -3292,8 +3292,8 @@ static u16 efx_ef10_handle_rx_event_errors(struct efx_channel *channel, ...@@ -3292,8 +3292,8 @@ static u16 efx_ef10_handle_rx_event_errors(struct efx_channel *channel,
if (unlikely(rx_encap_hdr != ESE_EZ_ENCAP_HDR_VXLAN && if (unlikely(rx_encap_hdr != ESE_EZ_ENCAP_HDR_VXLAN &&
((rx_l3_class != ESE_DZ_L3_CLASS_IP4 && ((rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
rx_l3_class != ESE_DZ_L3_CLASS_IP6) || rx_l3_class != ESE_DZ_L3_CLASS_IP6) ||
(rx_l4_class != ESE_DZ_L4_CLASS_TCP && (rx_l4_class != ESE_FZ_L4_CLASS_TCP &&
rx_l4_class != ESE_DZ_L4_CLASS_UDP)))) rx_l4_class != ESE_FZ_L4_CLASS_UDP))))
netdev_WARN(efx->net_dev, netdev_WARN(efx->net_dev,
"invalid class for RX_TCPUDP_CKSUM_ERR: event=" "invalid class for RX_TCPUDP_CKSUM_ERR: event="
EFX_QWORD_FMT "\n", EFX_QWORD_FMT "\n",
...@@ -3330,8 +3330,8 @@ static u16 efx_ef10_handle_rx_event_errors(struct efx_channel *channel, ...@@ -3330,8 +3330,8 @@ static u16 efx_ef10_handle_rx_event_errors(struct efx_channel *channel,
EFX_QWORD_VAL(*event)); EFX_QWORD_VAL(*event));
else if (unlikely((rx_l3_class != ESE_DZ_L3_CLASS_IP4 && else if (unlikely((rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
rx_l3_class != ESE_DZ_L3_CLASS_IP6) || rx_l3_class != ESE_DZ_L3_CLASS_IP6) ||
(rx_l4_class != ESE_DZ_L4_CLASS_TCP && (rx_l4_class != ESE_FZ_L4_CLASS_TCP &&
rx_l4_class != ESE_DZ_L4_CLASS_UDP))) rx_l4_class != ESE_FZ_L4_CLASS_UDP)))
netdev_WARN(efx->net_dev, netdev_WARN(efx->net_dev,
"invalid class for RX_TCP_UDP_INNER_CHKSUM_ERR: event=" "invalid class for RX_TCP_UDP_INNER_CHKSUM_ERR: event="
EFX_QWORD_FMT "\n", EFX_QWORD_FMT "\n",
...@@ -3366,7 +3366,7 @@ static int efx_ef10_handle_rx_event(struct efx_channel *channel, ...@@ -3366,7 +3366,7 @@ static int efx_ef10_handle_rx_event(struct efx_channel *channel,
next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS); next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS);
rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL); rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL);
rx_l3_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L3_CLASS); rx_l3_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L3_CLASS);
rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS); rx_l4_class = EFX_QWORD_FIELD(*event, ESF_FZ_RX_L4_CLASS);
rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT); rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT);
rx_encap_hdr = rx_encap_hdr =
nic_data->datapath_caps & nic_data->datapath_caps &
...@@ -3444,8 +3444,8 @@ static int efx_ef10_handle_rx_event(struct efx_channel *channel, ...@@ -3444,8 +3444,8 @@ static int efx_ef10_handle_rx_event(struct efx_channel *channel,
rx_l3_class, rx_l4_class, rx_l3_class, rx_l4_class,
event); event);
} else { } else {
bool tcpudp = rx_l4_class == ESE_DZ_L4_CLASS_TCP || bool tcpudp = rx_l4_class == ESE_FZ_L4_CLASS_TCP ||
rx_l4_class == ESE_DZ_L4_CLASS_UDP; rx_l4_class == ESE_FZ_L4_CLASS_UDP;
switch (rx_encap_hdr) { switch (rx_encap_hdr) {
case ESE_EZ_ENCAP_HDR_VXLAN: /* VxLAN or GENEVE */ case ESE_EZ_ENCAP_HDR_VXLAN: /* VxLAN or GENEVE */
...@@ -3466,7 +3466,7 @@ static int efx_ef10_handle_rx_event(struct efx_channel *channel, ...@@ -3466,7 +3466,7 @@ static int efx_ef10_handle_rx_event(struct efx_channel *channel,
} }
} }
if (rx_l4_class == ESE_DZ_L4_CLASS_TCP) if (rx_l4_class == ESE_FZ_L4_CLASS_TCP)
flags |= EFX_RX_PKT_TCP; flags |= EFX_RX_PKT_TCP;
channel->irq_mod_score += 2 * n_packets; channel->irq_mod_score += 2 * n_packets;
......
drivers/net/ethernet/sfc/ef10_regs.h
View file @ d8d8ccf2
/**************************************************************************** /****************************************************************************
* Driver for Solarflare network controllers and boards * Driver for Solarflare network controllers and boards
* Copyright 2012-2015 Solarflare Communications Inc. * Copyright 2012-2017 Solarflare Communications Inc.
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published * under the terms of the GNU General Public License version 2 as published
...@@ -79,6 +79,8 @@ ...@@ -79,6 +79,8 @@
#define ER_DZ_EVQ_TMR 0x00000420 #define ER_DZ_EVQ_TMR 0x00000420
#define ER_DZ_EVQ_TMR_STEP 8192 #define ER_DZ_EVQ_TMR_STEP 8192
#define ER_DZ_EVQ_TMR_ROWS 2048 #define ER_DZ_EVQ_TMR_ROWS 2048
#define ERF_FZ_TC_TMR_REL_VAL_LBN 16
#define ERF_FZ_TC_TMR_REL_VAL_WIDTH 14
#define ERF_DZ_TC_TIMER_MODE_LBN 14 #define ERF_DZ_TC_TIMER_MODE_LBN 14
#define ERF_DZ_TC_TIMER_MODE_WIDTH 2 #define ERF_DZ_TC_TIMER_MODE_WIDTH 2
#define ERF_DZ_TC_TIMER_VAL_LBN 0 #define ERF_DZ_TC_TIMER_VAL_LBN 0
...@@ -159,16 +161,24 @@ ...@@ -159,16 +161,24 @@
#define ESF_DZ_RX_EV_SOFT2_WIDTH 2 #define ESF_DZ_RX_EV_SOFT2_WIDTH 2
#define ESF_DZ_RX_DSC_PTR_LBITS_LBN 48 #define ESF_DZ_RX_DSC_PTR_LBITS_LBN 48
#define ESF_DZ_RX_DSC_PTR_LBITS_WIDTH 4 #define ESF_DZ_RX_DSC_PTR_LBITS_WIDTH 4
#define ESF_DZ_RX_L4_CLASS_LBN 45 #define ESF_DE_RX_L4_CLASS_LBN 45
#define ESF_DZ_RX_L4_CLASS_WIDTH 3 #define ESF_DE_RX_L4_CLASS_WIDTH 3
#define ESE_DZ_L4_CLASS_RSVD7 7 #define ESE_DE_L4_CLASS_RSVD7 7
#define ESE_DZ_L4_CLASS_RSVD6 6 #define ESE_DE_L4_CLASS_RSVD6 6
#define ESE_DZ_L4_CLASS_RSVD5 5 #define ESE_DE_L4_CLASS_RSVD5 5
#define ESE_DZ_L4_CLASS_RSVD4 4 #define ESE_DE_L4_CLASS_RSVD4 4
#define ESE_DZ_L4_CLASS_RSVD3 3 #define ESE_DE_L4_CLASS_RSVD3 3
#define ESE_DZ_L4_CLASS_UDP 2 #define ESE_DE_L4_CLASS_UDP 2
#define ESE_DZ_L4_CLASS_TCP 1 #define ESE_DE_L4_CLASS_TCP 1
#define ESE_DZ_L4_CLASS_UNKNOWN 0 #define ESE_DE_L4_CLASS_UNKNOWN 0
#define ESF_FZ_RX_FASTPD_INDCTR_LBN 47
#define ESF_FZ_RX_FASTPD_INDCTR_WIDTH 1
#define ESF_FZ_RX_L4_CLASS_LBN 45
#define ESF_FZ_RX_L4_CLASS_WIDTH 2
#define ESE_FZ_L4_CLASS_RSVD3 3
#define ESE_FZ_L4_CLASS_UDP 2
#define ESE_FZ_L4_CLASS_TCP 1
#define ESE_FZ_L4_CLASS_UNKNOWN 0
#define ESF_DZ_RX_L3_CLASS_LBN 42 #define ESF_DZ_RX_L3_CLASS_LBN 42
#define ESF_DZ_RX_L3_CLASS_WIDTH 3 #define ESF_DZ_RX_L3_CLASS_WIDTH 3
#define ESE_DZ_L3_CLASS_RSVD7 7 #define ESE_DZ_L3_CLASS_RSVD7 7
...@@ -215,6 +225,8 @@ ...@@ -215,6 +225,8 @@
#define ESF_EZ_RX_ABORT_WIDTH 1 #define ESF_EZ_RX_ABORT_WIDTH 1
#define ESF_DZ_RX_ECC_ERR_LBN 29 #define ESF_DZ_RX_ECC_ERR_LBN 29
#define ESF_DZ_RX_ECC_ERR_WIDTH 1 #define ESF_DZ_RX_ECC_ERR_WIDTH 1
#define ESF_DZ_RX_TRUNC_ERR_LBN 29
#define ESF_DZ_RX_TRUNC_ERR_WIDTH 1
#define ESF_DZ_RX_CRC1_ERR_LBN 28 #define ESF_DZ_RX_CRC1_ERR_LBN 28
#define ESF_DZ_RX_CRC1_ERR_WIDTH 1 #define ESF_DZ_RX_CRC1_ERR_WIDTH 1
#define ESF_DZ_RX_CRC0_ERR_LBN 27 #define ESF_DZ_RX_CRC0_ERR_LBN 27
...@@ -332,6 +344,8 @@ ...@@ -332,6 +344,8 @@
#define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0
#define ESF_DZ_TX_TSO_OPTION_TYPE_LBN 56 #define ESF_DZ_TX_TSO_OPTION_TYPE_LBN 56
#define ESF_DZ_TX_TSO_OPTION_TYPE_WIDTH 4 #define ESF_DZ_TX_TSO_OPTION_TYPE_WIDTH 4
#define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B 3
#define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A 2
#define ESE_DZ_TX_TSO_OPTION_DESC_ENCAP 1 #define ESE_DZ_TX_TSO_OPTION_DESC_ENCAP 1
#define ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0 #define ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0
#define ESF_DZ_TX_TSO_TCP_FLAGS_LBN 48 #define ESF_DZ_TX_TSO_TCP_FLAGS_LBN 48
...@@ -341,7 +355,7 @@ ...@@ -341,7 +355,7 @@
#define ESF_DZ_TX_TSO_TCP_SEQNO_LBN 0 #define ESF_DZ_TX_TSO_TCP_SEQNO_LBN 0
#define ESF_DZ_TX_TSO_TCP_SEQNO_WIDTH 32 #define ESF_DZ_TX_TSO_TCP_SEQNO_WIDTH 32
/* TX_TSO_FATSO2A_DESC */ /* TX_TSO_V2_DESC_A */
#define ESF_DZ_TX_DESC_IS_OPT_LBN 63 #define ESF_DZ_TX_DESC_IS_OPT_LBN 63
#define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1
#define ESF_DZ_TX_OPTION_TYPE_LBN 60 #define ESF_DZ_TX_OPTION_TYPE_LBN 60
...@@ -360,8 +374,7 @@ ...@@ -360,8 +374,7 @@
#define ESF_DZ_TX_TSO_TCP_SEQNO_LBN 0 #define ESF_DZ_TX_TSO_TCP_SEQNO_LBN 0
#define ESF_DZ_TX_TSO_TCP_SEQNO_WIDTH 32 #define ESF_DZ_TX_TSO_TCP_SEQNO_WIDTH 32
/* TX_TSO_V2_DESC_B */
/* TX_TSO_FATSO2B_DESC */
#define ESF_DZ_TX_DESC_IS_OPT_LBN 63 #define ESF_DZ_TX_DESC_IS_OPT_LBN 63
#define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1
#define ESF_DZ_TX_OPTION_TYPE_LBN 60 #define ESF_DZ_TX_OPTION_TYPE_LBN 60
...@@ -375,11 +388,10 @@ ...@@ -375,11 +388,10 @@
#define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A 2 #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A 2
#define ESE_DZ_TX_TSO_OPTION_DESC_ENCAP 1 #define ESE_DZ_TX_TSO_OPTION_DESC_ENCAP 1
#define ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0 #define ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0
#define ESF_DZ_TX_TSO_OUTER_IP_ID_LBN 0
#define ESF_DZ_TX_TSO_OUTER_IP_ID_WIDTH 16
#define ESF_DZ_TX_TSO_TCP_MSS_LBN 32 #define ESF_DZ_TX_TSO_TCP_MSS_LBN 32
#define ESF_DZ_TX_TSO_TCP_MSS_WIDTH 16 #define ESF_DZ_TX_TSO_TCP_MSS_WIDTH 16
#define ESF_DZ_TX_TSO_OUTER_IPID_LBN 0
#define ESF_DZ_TX_TSO_OUTER_IPID_WIDTH 16
/*************************************************************************/ /*************************************************************************/
......
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