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Commit d9f25b59 authored by Matthew Wilcox (Oracle)'s avatar Matthew Wilcox (Oracle) Committed by Helge Deller
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fbdev: Remove support for Carillo Ranch driver 

As far as anybody can tell, this product never shipped.  If it did,
it shipped in 2007 and nobody has access to one any more.  Remove the
fbdev driver and the backlight driver.
Signed-off-by: default avatarMatthew Wilcox (Oracle) <willy@infradead.org>
Signed-off-by: default avatarHelge Deller <deller@gmx.de>
parent 5379c646
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drivers/video/backlight/Kconfig
View file @ d9f25b59
...@@ -235,13 +235,6 @@ config BACKLIGHT_HP700 ...@@ -235,13 +235,6 @@ config BACKLIGHT_HP700
If you have an HP Jornada 700 series, If you have an HP Jornada 700 series,
say Y to include backlight control driver. say Y to include backlight control driver.
config BACKLIGHT_CARILLO_RANCH
tristate "Intel Carillo Ranch Backlight Driver"
depends on LCD_CLASS_DEVICE && PCI && X86 && FB_LE80578
help
If you have a Intel LE80578 (Carillo Ranch) say Y to enable the
backlight driver.
config BACKLIGHT_PWM config BACKLIGHT_PWM
tristate "Generic PWM based Backlight Driver" tristate "Generic PWM based Backlight Driver"
depends on PWM depends on PWM
......
drivers/video/backlight/Makefile
View file @ d9f25b59
...@@ -25,7 +25,6 @@ obj-$(CONFIG_BACKLIGHT_ADP8870) += adp8870_bl.o ...@@ -25,7 +25,6 @@ obj-$(CONFIG_BACKLIGHT_ADP8870) += adp8870_bl.o
obj-$(CONFIG_BACKLIGHT_APPLE) += apple_bl.o obj-$(CONFIG_BACKLIGHT_APPLE) += apple_bl.o
obj-$(CONFIG_BACKLIGHT_AS3711) += as3711_bl.o obj-$(CONFIG_BACKLIGHT_AS3711) += as3711_bl.o
obj-$(CONFIG_BACKLIGHT_BD6107) += bd6107.o obj-$(CONFIG_BACKLIGHT_BD6107) += bd6107.o
obj-$(CONFIG_BACKLIGHT_CARILLO_RANCH) += cr_bllcd.o
obj-$(CONFIG_BACKLIGHT_CLASS_DEVICE) += backlight.o obj-$(CONFIG_BACKLIGHT_CLASS_DEVICE) += backlight.o
obj-$(CONFIG_BACKLIGHT_DA903X) += da903x_bl.o obj-$(CONFIG_BACKLIGHT_DA903X) += da903x_bl.o
obj-$(CONFIG_BACKLIGHT_DA9052) += da9052_bl.o obj-$(CONFIG_BACKLIGHT_DA9052) += da9052_bl.o
......
drivers/video/backlight/cr_bllcd.c deleted 100644 → 0
View file @ 5379c646
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) Intel Corp. 2007.
* All Rights Reserved.
*
* Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
* develop this driver.
*
* This file is part of the Carillo Ranch video subsystem driver.
*
* Authors:
* Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
* Alan Hourihane <alanh-at-tungstengraphics-dot-com>
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/mutex.h>
#include <linux/fb.h>
#include <linux/backlight.h>
#include <linux/lcd.h>
#include <linux/pci.h>
#include <linux/slab.h>
/* The LVDS- and panel power controls sits on the
* GPIO port of the ISA bridge.
*/
#define CRVML_DEVICE_LPC 0x27B8
#define CRVML_REG_GPIOBAR 0x48
#define CRVML_REG_GPIOEN 0x4C
#define CRVML_GPIOEN_BIT (1 << 4)
#define CRVML_PANEL_PORT 0x38
#define CRVML_LVDS_ON 0x00000001
#define CRVML_PANEL_ON 0x00000002
#define CRVML_BACKLIGHT_OFF 0x00000004
/* The PLL Clock register sits on Host bridge */
#define CRVML_DEVICE_MCH 0x5001
#define CRVML_REG_MCHBAR 0x44
#define CRVML_REG_MCHEN 0x54
#define CRVML_MCHEN_BIT (1 << 28)
#define CRVML_MCHMAP_SIZE 4096
#define CRVML_REG_CLOCK 0xc3c
#define CRVML_CLOCK_SHIFT 8
#define CRVML_CLOCK_MASK 0x00000f00
static struct pci_dev *lpc_dev;
static u32 gpio_bar;
struct cr_panel {
struct backlight_device *cr_backlight_device;
struct lcd_device *cr_lcd_device;
};
static int cr_backlight_set_intensity(struct backlight_device *bd)
{
u32 addr = gpio_bar + CRVML_PANEL_PORT;
u32 cur = inl(addr);
if (backlight_get_brightness(bd) == 0) {
/* OFF */
cur |= CRVML_BACKLIGHT_OFF;
outl(cur, addr);
} else {
/* FULL ON */
cur &= ~CRVML_BACKLIGHT_OFF;
outl(cur, addr);
}
return 0;
}
static int cr_backlight_get_intensity(struct backlight_device *bd)
{
u32 addr = gpio_bar + CRVML_PANEL_PORT;
u32 cur = inl(addr);
u8 intensity;
if (cur & CRVML_BACKLIGHT_OFF)
intensity = 0;
else
intensity = 1;
return intensity;
}
static const struct backlight_ops cr_backlight_ops = {
.get_brightness = cr_backlight_get_intensity,
.update_status = cr_backlight_set_intensity,
};
static void cr_panel_on(void)
{
u32 addr = gpio_bar + CRVML_PANEL_PORT;
u32 cur = inl(addr);
if (!(cur & CRVML_PANEL_ON)) {
/* Make sure LVDS controller is down. */
if (cur & 0x00000001) {
cur &= ~CRVML_LVDS_ON;
outl(cur, addr);
}
/* Power up Panel */
schedule_timeout(HZ / 10);
cur |= CRVML_PANEL_ON;
outl(cur, addr);
}
/* Power up LVDS controller */
if (!(cur & CRVML_LVDS_ON)) {
schedule_timeout(HZ / 10);
outl(cur | CRVML_LVDS_ON, addr);
}
}
static void cr_panel_off(void)
{
u32 addr = gpio_bar + CRVML_PANEL_PORT;
u32 cur = inl(addr);
/* Power down LVDS controller first to avoid high currents */
if (cur & CRVML_LVDS_ON) {
cur &= ~CRVML_LVDS_ON;
outl(cur, addr);
}
if (cur & CRVML_PANEL_ON) {
schedule_timeout(HZ / 10);
outl(cur & ~CRVML_PANEL_ON, addr);
}
}
static int cr_lcd_set_power(struct lcd_device *ld, int power)
{
if (power == FB_BLANK_UNBLANK)
cr_panel_on();
if (power == FB_BLANK_POWERDOWN)
cr_panel_off();
return 0;
}
static struct lcd_ops cr_lcd_ops = {
.set_power = cr_lcd_set_power,
};
static int cr_backlight_probe(struct platform_device *pdev)
{
struct backlight_properties props;
struct backlight_device *bdp;
struct lcd_device *ldp;
struct cr_panel *crp;
u8 dev_en;
lpc_dev = pci_get_device(PCI_VENDOR_ID_INTEL,
CRVML_DEVICE_LPC, NULL);
if (!lpc_dev) {
pr_err("INTEL CARILLO RANCH LPC not found.\n");
return -ENODEV;
}
pci_read_config_byte(lpc_dev, CRVML_REG_GPIOEN, &dev_en);
if (!(dev_en & CRVML_GPIOEN_BIT)) {
pr_err("Carillo Ranch GPIO device was not enabled.\n");
pci_dev_put(lpc_dev);
return -ENODEV;
}
memset(&props, 0, sizeof(struct backlight_properties));
props.type = BACKLIGHT_RAW;
bdp = devm_backlight_device_register(&pdev->dev, "cr-backlight",
&pdev->dev, NULL, &cr_backlight_ops,
&props);
if (IS_ERR(bdp)) {
pci_dev_put(lpc_dev);
return PTR_ERR(bdp);
}
ldp = devm_lcd_device_register(&pdev->dev, "cr-lcd", &pdev->dev, NULL,
&cr_lcd_ops);
if (IS_ERR(ldp)) {
pci_dev_put(lpc_dev);
return PTR_ERR(ldp);
}
pci_read_config_dword(lpc_dev, CRVML_REG_GPIOBAR,
&gpio_bar);
gpio_bar &= ~0x3F;
crp = devm_kzalloc(&pdev->dev, sizeof(*crp), GFP_KERNEL);
if (!crp) {
pci_dev_put(lpc_dev);
return -ENOMEM;
}
crp->cr_backlight_device = bdp;
crp->cr_lcd_device = ldp;
crp->cr_backlight_device->props.power = FB_BLANK_UNBLANK;
crp->cr_backlight_device->props.brightness = 0;
cr_backlight_set_intensity(crp->cr_backlight_device);
cr_lcd_set_power(crp->cr_lcd_device, FB_BLANK_UNBLANK);
platform_set_drvdata(pdev, crp);
return 0;
}
static void cr_backlight_remove(struct platform_device *pdev)
{
struct cr_panel *crp = platform_get_drvdata(pdev);
crp->cr_backlight_device->props.power = FB_BLANK_POWERDOWN;
crp->cr_backlight_device->props.brightness = 0;
crp->cr_backlight_device->props.max_brightness = 0;
cr_backlight_set_intensity(crp->cr_backlight_device);
cr_lcd_set_power(crp->cr_lcd_device, FB_BLANK_POWERDOWN);
pci_dev_put(lpc_dev);
}
static struct platform_driver cr_backlight_driver = {
.probe = cr_backlight_probe,
.remove_new = cr_backlight_remove,
.driver = {
.name = "cr_backlight",
},
};
static struct platform_device *crp;
static int __init cr_backlight_init(void)
{
int ret = platform_driver_register(&cr_backlight_driver);
if (ret)
return ret;
crp = platform_device_register_simple("cr_backlight", -1, NULL, 0);
if (IS_ERR(crp)) {
platform_driver_unregister(&cr_backlight_driver);
return PTR_ERR(crp);
}
pr_info("Carillo Ranch Backlight Driver Initialized.\n");
return 0;
}
static void __exit cr_backlight_exit(void)
{
platform_device_unregister(crp);
platform_driver_unregister(&cr_backlight_driver);
}
module_init(cr_backlight_init);
module_exit(cr_backlight_exit);
MODULE_AUTHOR("Tungsten Graphics Inc.");
MODULE_DESCRIPTION("Carillo Ranch Backlight Driver");
MODULE_LICENSE("GPL");
drivers/video/fbdev/Kconfig
View file @ d9f25b59
...@@ -847,21 +847,6 @@ config FB_I810_I2C ...@@ -847,21 +847,6 @@ config FB_I810_I2C
If unsure, say Y. If unsure, say Y.
config FB_LE80578
tristate "Intel LE80578 (Vermilion) support"
depends on FB && PCI && X86
select FB_IOMEM_HELPERS
select FB_MODE_HELPERS
select VIDEO_NOMODESET
help
This driver supports the LE80578 (Vermilion Range) chipset
config FB_CARILLO_RANCH
tristate "Intel Carillo Ranch support"
depends on FB_LE80578 && FB && PCI && X86
help
This driver supports the LE80578 (Carillo Ranch) board
config FB_INTEL config FB_INTEL
tristate "Intel 830M/845G/852GM/855GM/865G/915G/945G/945GM/965G/965GM support" tristate "Intel 830M/845G/852GM/855GM/865G/915G/945G/945GM/965G/965GM support"
depends on FB && PCI && X86 && AGP_INTEL && EXPERT depends on FB && PCI && X86 && AGP_INTEL && EXPERT
......
drivers/video/fbdev/Makefile
View file @ d9f25b59
...@@ -42,7 +42,6 @@ obj-$(CONFIG_FB_IMSTT) += imsttfb.o ...@@ -42,7 +42,6 @@ obj-$(CONFIG_FB_IMSTT) += imsttfb.o
obj-$(CONFIG_FB_FM2) += fm2fb.o obj-$(CONFIG_FB_FM2) += fm2fb.o
obj-$(CONFIG_FB_VT8623) += vt8623fb.o obj-$(CONFIG_FB_VT8623) += vt8623fb.o
obj-$(CONFIG_FB_TRIDENT) += tridentfb.o obj-$(CONFIG_FB_TRIDENT) += tridentfb.o
obj-$(CONFIG_FB_LE80578) += vermilion/
obj-$(CONFIG_FB_S3) += s3fb.o obj-$(CONFIG_FB_S3) += s3fb.o
obj-$(CONFIG_FB_ARK) += arkfb.o obj-$(CONFIG_FB_ARK) += arkfb.o
obj-$(CONFIG_FB_STI) += stifb.o obj-$(CONFIG_FB_STI) += stifb.o
......
drivers/video/fbdev/vermilion/Makefile deleted 100644 → 0
View file @ 5379c646
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_FB_LE80578) += vmlfb.o
obj-$(CONFIG_FB_CARILLO_RANCH) += crvml.o
vmlfb-objs := vermilion.o
crvml-objs := cr_pll.o
drivers/video/fbdev/vermilion/cr_pll.c deleted 100644 → 0
View file @ 5379c646
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) Intel Corp. 2007.
* All Rights Reserved.
*
* Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
* develop this driver.
*
* This file is part of the Carillo Ranch video subsystem driver.
*
* Authors:
* Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
* Alan Hourihane <alanh-at-tungstengraphics-dot-com>
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/errno.h>
#include <linux/fb.h>
#include "vermilion.h"
/* The PLL Clock register sits on Host bridge */
#define CRVML_DEVICE_MCH 0x5001
#define CRVML_REG_MCHBAR 0x44
#define CRVML_REG_MCHEN 0x54
#define CRVML_MCHEN_BIT (1 << 28)
#define CRVML_MCHMAP_SIZE 4096
#define CRVML_REG_CLOCK 0xc3c
#define CRVML_CLOCK_SHIFT 8
#define CRVML_CLOCK_MASK 0x00000f00
static struct pci_dev *mch_dev;
static u32 mch_bar;
static void __iomem *mch_regs_base;
static u32 saved_clock;
static const unsigned crvml_clocks[] = {
6750,
13500,
27000,
29700,
37125,
54000,
59400,
74250,
120000
/*
* There are more clocks, but they are disabled on the CR board.
*/
};
static const u32 crvml_clock_bits[] = {
0x0a,
0x09,
0x08,
0x07,
0x06,
0x05,
0x04,
0x03,
0x0b
};
static const unsigned crvml_num_clocks = ARRAY_SIZE(crvml_clocks);
static int crvml_sys_restore(struct vml_sys *sys)
{
void __iomem *clock_reg = mch_regs_base + CRVML_REG_CLOCK;
iowrite32(saved_clock, clock_reg);
ioread32(clock_reg);
return 0;
}
static int crvml_sys_save(struct vml_sys *sys)
{
void __iomem *clock_reg = mch_regs_base + CRVML_REG_CLOCK;
saved_clock = ioread32(clock_reg);
return 0;
}
static int crvml_nearest_index(const struct vml_sys *sys, int clock)
{
int i;
int cur_index = 0;
int cur_diff;
int diff;
cur_diff = clock - crvml_clocks[0];
cur_diff = (cur_diff < 0) ? -cur_diff : cur_diff;
for (i = 1; i < crvml_num_clocks; ++i) {
diff = clock - crvml_clocks[i];
diff = (diff < 0) ? -diff : diff;
if (diff < cur_diff) {
cur_index = i;
cur_diff = diff;
}
}
return cur_index;
}
static int crvml_nearest_clock(const struct vml_sys *sys, int clock)
{
return crvml_clocks[crvml_nearest_index(sys, clock)];
}
static int crvml_set_clock(struct vml_sys *sys, int clock)
{
void __iomem *clock_reg = mch_regs_base + CRVML_REG_CLOCK;
int index;
u32 clock_val;
index = crvml_nearest_index(sys, clock);
if (crvml_clocks[index] != clock)
return -EINVAL;
clock_val = ioread32(clock_reg) & ~CRVML_CLOCK_MASK;
clock_val = crvml_clock_bits[index] << CRVML_CLOCK_SHIFT;
iowrite32(clock_val, clock_reg);
ioread32(clock_reg);
return 0;
}
static struct vml_sys cr_pll_ops = {
.name = "Carillo Ranch",
.save = crvml_sys_save,
.restore = crvml_sys_restore,
.set_clock = crvml_set_clock,
.nearest_clock = crvml_nearest_clock,
};
static int __init cr_pll_init(void)
{
int err;
u32 dev_en;
mch_dev = pci_get_device(PCI_VENDOR_ID_INTEL,
CRVML_DEVICE_MCH, NULL);
if (!mch_dev) {
printk(KERN_ERR
"Could not find Carillo Ranch MCH device.\n");
return -ENODEV;
}
pci_read_config_dword(mch_dev, CRVML_REG_MCHEN, &dev_en);
if (!(dev_en & CRVML_MCHEN_BIT)) {
printk(KERN_ERR
"Carillo Ranch MCH device was not enabled.\n");
pci_dev_put(mch_dev);
return -ENODEV;
}
pci_read_config_dword(mch_dev, CRVML_REG_MCHBAR,
&mch_bar);
mch_regs_base =
ioremap(mch_bar, CRVML_MCHMAP_SIZE);
if (!mch_regs_base) {
printk(KERN_ERR
"Carillo Ranch MCH device was not enabled.\n");
pci_dev_put(mch_dev);
return -ENODEV;
}
err = vmlfb_register_subsys(&cr_pll_ops);
if (err) {
printk(KERN_ERR
"Carillo Ranch failed to initialize vml_sys.\n");
iounmap(mch_regs_base);
pci_dev_put(mch_dev);
return err;
}
return 0;
}
static void __exit cr_pll_exit(void)
{
vmlfb_unregister_subsys(&cr_pll_ops);
iounmap(mch_regs_base);
pci_dev_put(mch_dev);
}
module_init(cr_pll_init);
module_exit(cr_pll_exit);
MODULE_AUTHOR("Tungsten Graphics Inc.");
MODULE_DESCRIPTION("Carillo Ranch PLL Driver");
MODULE_LICENSE("GPL");
drivers/video/fbdev/vermilion/vermilion.c deleted 100644 → 0
View file @ 5379c646
This diff is collapsed.
drivers/video/fbdev/vermilion/vermilion.h deleted 100644 → 0
View file @ 5379c646
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (c) Intel Corp. 2007.
* All Rights Reserved.
*
* Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
* develop this driver.
*
* This file is part of the Vermilion Range fb driver.
*
* Authors:
* Thomas Hellström <thomas-at-tungstengraphics-dot-com>
*/
#ifndef _VERMILION_H_
#define _VERMILION_H_
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/atomic.h>
#include <linux/mutex.h>
#define VML_DEVICE_GPU 0x5002
#define VML_DEVICE_VDC 0x5009
#define VML_VRAM_AREAS 3
#define VML_MAX_XRES 1024
#define VML_MAX_YRES 768
#define VML_MAX_XRES_VIRTUAL 1040
/*
* Display controller registers:
*/
/* Display controller 10-bit color representation */
#define VML_R_MASK 0x3FF00000
#define VML_R_SHIFT 20
#define VML_G_MASK 0x000FFC00
#define VML_G_SHIFT 10
#define VML_B_MASK 0x000003FF
#define VML_B_SHIFT 0
/* Graphics plane control */
#define VML_DSPCCNTR 0x00072180
#define VML_GFX_ENABLE 0x80000000
#define VML_GFX_GAMMABYPASS 0x40000000
#define VML_GFX_ARGB1555 0x0C000000
#define VML_GFX_RGB0888 0x18000000
#define VML_GFX_ARGB8888 0x1C000000
#define VML_GFX_ALPHACONST 0x02000000
#define VML_GFX_ALPHAMULT 0x01000000
#define VML_GFX_CONST_ALPHA 0x000000FF
/* Graphics plane start address. Pixel aligned. */
#define VML_DSPCADDR 0x00072184
/* Graphics plane stride register. */
#define VML_DSPCSTRIDE 0x00072188
/* Graphics plane position register. */
#define VML_DSPCPOS 0x0007218C
#define VML_POS_YMASK 0x0FFF0000
#define VML_POS_YSHIFT 16
#define VML_POS_XMASK 0x00000FFF
#define VML_POS_XSHIFT 0
/* Graphics plane height and width */
#define VML_DSPCSIZE 0x00072190
#define VML_SIZE_HMASK 0x0FFF0000
#define VML_SIZE_HSHIFT 16
#define VML_SISE_WMASK 0x00000FFF
#define VML_SIZE_WSHIFT 0
/* Graphics plane gamma correction lookup table registers (129 * 32 bits) */
#define VML_DSPCGAMLUT 0x00072200
/* Pixel video output configuration register */
#define VML_PVOCONFIG 0x00061140
#define VML_CONFIG_BASE 0x80000000
#define VML_CONFIG_PIXEL_SWAP 0x04000000
#define VML_CONFIG_DE_INV 0x01000000
#define VML_CONFIG_HREF_INV 0x00400000
#define VML_CONFIG_VREF_INV 0x00100000
#define VML_CONFIG_CLK_INV 0x00040000
#define VML_CONFIG_CLK_DIV2 0x00010000
#define VML_CONFIG_ESTRB_INV 0x00008000
/* Pipe A Horizontal total register */
#define VML_HTOTAL_A 0x00060000
#define VML_HTOTAL_MASK 0x1FFF0000
#define VML_HTOTAL_SHIFT 16
#define VML_HTOTAL_VAL 8192
#define VML_HACTIVE_MASK 0x000007FF
#define VML_HACTIVE_SHIFT 0
#define VML_HACTIVE_VAL 4096
/* Pipe A Horizontal Blank register */
#define VML_HBLANK_A 0x00060004
#define VML_HBLANK_END_MASK 0x1FFF0000
#define VML_HBLANK_END_SHIFT 16
#define VML_HBLANK_END_VAL 8192
#define VML_HBLANK_START_MASK 0x00001FFF
#define VML_HBLANK_START_SHIFT 0
#define VML_HBLANK_START_VAL 8192
/* Pipe A Horizontal Sync register */
#define VML_HSYNC_A 0x00060008
#define VML_HSYNC_END_MASK 0x1FFF0000
#define VML_HSYNC_END_SHIFT 16
#define VML_HSYNC_END_VAL 8192
#define VML_HSYNC_START_MASK 0x00001FFF
#define VML_HSYNC_START_SHIFT 0
#define VML_HSYNC_START_VAL 8192
/* Pipe A Vertical total register */
#define VML_VTOTAL_A 0x0006000C
#define VML_VTOTAL_MASK 0x1FFF0000
#define VML_VTOTAL_SHIFT 16
#define VML_VTOTAL_VAL 8192
#define VML_VACTIVE_MASK 0x000007FF
#define VML_VACTIVE_SHIFT 0
#define VML_VACTIVE_VAL 4096
/* Pipe A Vertical Blank register */
#define VML_VBLANK_A 0x00060010
#define VML_VBLANK_END_MASK 0x1FFF0000
#define VML_VBLANK_END_SHIFT 16
#define VML_VBLANK_END_VAL 8192
#define VML_VBLANK_START_MASK 0x00001FFF
#define VML_VBLANK_START_SHIFT 0
#define VML_VBLANK_START_VAL 8192
/* Pipe A Vertical Sync register */
#define VML_VSYNC_A 0x00060014
#define VML_VSYNC_END_MASK 0x1FFF0000
#define VML_VSYNC_END_SHIFT 16
#define VML_VSYNC_END_VAL 8192
#define VML_VSYNC_START_MASK 0x00001FFF
#define VML_VSYNC_START_SHIFT 0
#define VML_VSYNC_START_VAL 8192
/* Pipe A Source Image size (minus one - equal to active size)
* Programmable while pipe is enabled.
*/
#define VML_PIPEASRC 0x0006001C
#define VML_PIPEASRC_HMASK 0x0FFF0000
#define VML_PIPEASRC_HSHIFT 16
#define VML_PIPEASRC_VMASK 0x00000FFF
#define VML_PIPEASRC_VSHIFT 0
/* Pipe A Border Color Pattern register (10 bit color) */
#define VML_BCLRPAT_A 0x00060020
/* Pipe A Canvas Color register (10 bit color) */
#define VML_CANVSCLR_A 0x00060024
/* Pipe A Configuration register */
#define VML_PIPEACONF 0x00070008
#define VML_PIPE_BASE 0x00000000
#define VML_PIPE_ENABLE 0x80000000
#define VML_PIPE_FORCE_BORDER 0x02000000
#define VML_PIPE_PLANES_OFF 0x00080000
#define VML_PIPE_ARGB_OUTPUT_MODE 0x00040000
/* Pipe A FIFO setting */
#define VML_DSPARB 0x00070030
#define VML_FIFO_DEFAULT 0x00001D9C
/* MDVO rcomp status & pads control register */
#define VML_RCOMPSTAT 0x00070048
#define VML_MDVO_VDC_I_RCOMP 0x80000000
#define VML_MDVO_POWERSAVE_OFF 0x00000008
#define VML_MDVO_PAD_ENABLE 0x00000004
#define VML_MDVO_PULLDOWN_ENABLE 0x00000001
struct vml_par {
struct pci_dev *vdc;
u64 vdc_mem_base;
u64 vdc_mem_size;
char __iomem *vdc_mem;
struct pci_dev *gpu;
u64 gpu_mem_base;
u64 gpu_mem_size;
char __iomem *gpu_mem;
atomic_t refcount;
};
struct vram_area {
unsigned long logical;
unsigned long phys;
unsigned long size;
unsigned order;
};
struct vml_info {
struct fb_info info;
struct vml_par *par;
struct list_head head;
struct vram_area vram[VML_VRAM_AREAS];
u64 vram_start;
u64 vram_contig_size;
u32 num_areas;
void __iomem *vram_logical;
u32 pseudo_palette[16];
u32 stride;
u32 bytes_per_pixel;
atomic_t vmas;
int cur_blank_mode;
int pipe_disabled;
};
/*
* Subsystem
*/
struct vml_sys {
char *name;
/*
* Save / Restore;
*/
int (*save) (struct vml_sys * sys);
int (*restore) (struct vml_sys * sys);
/*
* PLL programming;
*/
int (*set_clock) (struct vml_sys * sys, int clock);
int (*nearest_clock) (const struct vml_sys * sys, int clock);
};
extern int vmlfb_register_subsys(struct vml_sys *sys);
extern void vmlfb_unregister_subsys(struct vml_sys *sys);
#define VML_READ32(_par, _offset) \
(ioread32((_par)->vdc_mem + (_offset)))
#define VML_WRITE32(_par, _offset, _value) \
iowrite32(_value, (_par)->vdc_mem + (_offset))
#endif
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