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Commit df35bf66 authored by Florian Schilhabel's avatar Florian Schilhabel Committed by Greg Kroah-Hartman
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Staging: rtl8192su: some work on SetBWModeCallback8192SUsbWorkItem 

mostly cosmetics.
Signed-off-by: default avatarFlorian Schilhabel <florian.c.schilhabel@googlemail.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
parent 8e399b03
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Showing with 80 additions and 105 deletions
drivers/staging/rtl8192su/r8192S_phy.c
View file @ df35bf66
...@@ -3607,128 +3607,103 @@ void SetBWModeCallback8192SUsb(struct net_device *dev) ...@@ -3607,128 +3607,103 @@ void SetBWModeCallback8192SUsb(struct net_device *dev)
RT_TRACE(COMP_SCAN, "<==SetBWMode8190Pci()" ); RT_TRACE(COMP_SCAN, "<==SetBWMode8190Pci()" );
} }
// /*
// Callback routine of the work item for set bandwidth mode. * Callback routine of the work item for set bandwidth mode.
// *
// use in phy only (in win it's work) * use in phy only (in win it's work)
*/
void SetBWModeCallback8192SUsbWorkItem(struct net_device *dev) void SetBWModeCallback8192SUsbWorkItem(struct net_device *dev)
{ {
struct r8192_priv *priv = ieee80211_priv(dev); struct r8192_priv *priv = ieee80211_priv(dev);
u8 regBwOpMode; u8 regBwOpMode;
u8 regRRSR_RSC;
// Added it for 20/40 mhz switch time evaluation by guangan 070531
//u32 NowL, NowH;
//u8Byte BeginTime, EndTime;
u8 regRRSR_RSC;
RT_TRACE(COMP_SCAN, "==>SetBWModeCallback8192SUsbWorkItem() Switch to %s bandwidth\n", \ RT_TRACE(COMP_SCAN, "%s(): Switch to %s bandwidth", __func__,
priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz"); priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20 ? "20MHz" : "40MHz");
if(priv->rf_chip == RF_PSEUDO_11N) if (priv->rf_chip == RF_PSEUDO_11N) {
{
priv->SetBWModeInProgress= FALSE; priv->SetBWModeInProgress= FALSE;
return; return;
} }
if(!priv->up) if(!priv->up)
return; return;
/* Set MAC register */
// Added it for 20/40 mhz switch time evaluation by guangan 070531
//NowL = read_nic_dword(dev, TSFR);
//NowH = read_nic_dword(dev, TSFR+4);
//BeginTime = ((u8Byte)NowH << 32) + NowL;
//3<1>Set MAC register
regBwOpMode = read_nic_byte(dev, BW_OPMODE); regBwOpMode = read_nic_byte(dev, BW_OPMODE);
regRRSR_RSC = read_nic_byte(dev, RRSR+2); regRRSR_RSC = read_nic_byte(dev, RRSR+2);
switch (priv->CurrentChannelBW) {
switch(priv->CurrentChannelBW) case HT_CHANNEL_WIDTH_20:
{ regBwOpMode |= BW_OPMODE_20MHZ;
case HT_CHANNEL_WIDTH_20: /* we have not verified whether this register works */
regBwOpMode |= BW_OPMODE_20MHZ; write_nic_byte(dev, BW_OPMODE, regBwOpMode);
// 2007/02/07 Mark by Emily becasue we have not verify whether this register works break;
write_nic_byte(dev, BW_OPMODE, regBwOpMode); case HT_CHANNEL_WIDTH_20_40:
break; regBwOpMode &= ~BW_OPMODE_20MHZ;
/* we have not verified whether this register works */
case HT_CHANNEL_WIDTH_20_40: write_nic_byte(dev, BW_OPMODE, regBwOpMode);
regBwOpMode &= ~BW_OPMODE_20MHZ; regRRSR_RSC = (regRRSR_RSC&0x90) | (priv->nCur40MhzPrimeSC<<5);
// 2007/02/07 Mark by Emily becasue we have not verify whether this register works write_nic_byte(dev, RRSR+2, regRRSR_RSC);
write_nic_byte(dev, BW_OPMODE, regBwOpMode); break;
regRRSR_RSC = (regRRSR_RSC&0x90) |(priv->nCur40MhzPrimeSC<<5); default:
write_nic_byte(dev, RRSR+2, regRRSR_RSC); RT_TRACE(COMP_DBG, "%s(): unknown Bandwidth: %#X", __func__,
priv->CurrentChannelBW);
break; break;
default:
RT_TRACE(COMP_DBG, "SetBWModeCallback8192SUsbWorkItem(): unknown Bandwidth: %#X\n",
priv->CurrentChannelBW);
break;
} }
/* Set PHY related register */
//3 <2>Set PHY related register switch (priv->CurrentChannelBW) {
switch(priv->CurrentChannelBW) case HT_CHANNEL_WIDTH_20:
{ rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
case HT_CHANNEL_WIDTH_20: rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0); rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x58);
rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0); break;
case HT_CHANNEL_WIDTH_20_40:
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x58); rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
break; /*
case HT_CHANNEL_WIDTH_20_40: * Set Control channel to upper or lower.
rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1); * These settings are required only for 40MHz
rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1); */
rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand,
// Set Control channel to upper or lower. These settings are required only for 40MHz (priv->nCur40MhzPrimeSC>>1));
rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1)); rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00,
rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC); priv->nCur40MhzPrimeSC);
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x18);
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x18); break;
default:
break; RT_TRACE(COMP_DBG, "%s(): unknown Bandwidth: %#X", __func__,
priv->CurrentChannelBW);
break;
default:
RT_TRACE(COMP_DBG, "SetBWModeCallback8192SUsbWorkItem(): unknown Bandwidth: %#X\n"\
,priv->CurrentChannelBW);
break;
} }
//Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315 /*
* Skip over setting of J-mode in BB register here.
//3<3>Set RF related register * Default value is "None J mode".
switch( priv->rf_chip ) */
{
case RF_8225:
PHY_SetRF8225Bandwidth(dev, priv->CurrentChannelBW);
break;
case RF_8256:
// Please implement this function in Hal8190PciPhy8256.c
//PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
break;
case RF_6052:
PHY_RF6052SetBandwidth(dev, priv->CurrentChannelBW);
break;
case RF_8258:
// Please implement this function in Hal8190PciPhy8258.c
// PHY_SetRF8258Bandwidth();
break;
case RF_PSEUDO_11N:
// Do Nothing
break;
default: /* Set RF related register */
//RT_ASSERT(FALSE, ("Unknown rf_chip: %d\n", priv->rf_chip)); switch (priv->rf_chip) {
break; case RF_8225:
PHY_SetRF8225Bandwidth(dev, priv->CurrentChannelBW);
break;
case RF_8256:
/* Please implement this function in Hal8190PciPhy8256.c */
/* PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW); */
break;
case RF_6052:
PHY_RF6052SetBandwidth(dev, priv->CurrentChannelBW);
break;
case RF_8258:
/* Please implement this function in Hal8190PciPhy8258.c */
/* PHY_SetRF8258Bandwidth(); */
break;
case RF_PSEUDO_11N:
/* Do Nothing */
break;
default:
RT_TRACE(COMP_DBG, "%s(): unknown rf_chip: %d", __func__,
priv->rf_chip);
break;
} }
priv->SetBWModeInProgress= FALSE; priv->SetBWModeInProgress= FALSE;
RT_TRACE(COMP_SCAN, "<==SetBWModeCallback8192SUsbWorkItem()" );
} }
//--------------------------Move to oter DIR later-------------------------------*/ //--------------------------Move to oter DIR later-------------------------------*/
......
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