Skip to content

L
linux
Commit e233cc59 authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Options

Merge tag 'arm-soc-6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc 

Pull ARM SoC updates from Arnd Bergmann:
 "The updates for arch/arm/mach-* platform code this time are mainly
  minor cleanups.

  Most notably, the DaVinci DM644x/DM646x SoC support gets removed. This
  was also scheduled for later removal early next year, but Linus
  Walleij asked for having them removed earlier to avoid problems for
  the GPIO subsystem"

* tag 'arm-soc-6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (38 commits)
  ARM: at91: setup outer cache .write_sec() callback if needed
  ARM: at91: add sam_linux_is_optee_available() function
  ARM: Marvell: Update PCIe fixup
  ARM: bcmbca: Include full family name in Kconfig
  ARM: bcm: NSP: Removed forced thermal selection
  ARM: debug: bcmbca: Replace ARCH_BCM_63XX with ARCH_BCMBCA
  arm: bcmbca: Add BCMBCA sub platforms
  arm: bcmbca: Move BCM63138 ARCH_BCM_63XX to ARCH_BCMBCA
  MAINTAINERS: Move BCM63138 to bcmbca arch entry
  ARM: shmobile: rcar-gen2: Increase refcount for new reference
  ARM: davinci: Delete DM646x board files
  ARM: davinci: Delete DM644x board files
  firmware: xilinx: Add TF_A_PM_REGISTER_SGI SMC call
  cpufreq: zynq: Fix refcount leak in zynq_get_revision
  ARM: OMAP2+: Kconfig: Fix indentation
  ARM: OMAP2+: Fix refcount leak in omap3xxx_prm_late_init
  ARM: OMAP2+: pdata-quirks: Fix refcount leak bug
  ARM: OMAP2+: display: Fix refcount leak bug
  ARM: OMAP2+: Fix refcount leak in omapdss_init_of
  ARM: imx25: support silicon revision 1.2
  ...
parents 9de1f9c8 755d0ebc
Hide whitespace changes
Inline Side-by-side
Showing with 186 additions and 3847 deletions
MAINTAINERS
View file @ e233cc59
......@@ -3875,15 +3875,28 @@ BROADCOM BCMBCA ARM ARCHITECTURE
M: William Zhang <william.zhang@broadcom.com>
M: Anand Gore <anand.gore@broadcom.com>
M: Kursad Oney <kursad.oney@broadcom.com>
M: Florian Fainelli <f.fainelli@gmail.com>
R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
T: git git://github.com/broadcom/stblinux.git
F: Documentation/devicetree/bindings/arm/bcm/brcm,bcmbca.yaml
F: arch/arm/boot/dts/bcm47622.dtsi
F: arch/arm/boot/dts/bcm947622.dts
F: arch/arm64/boot/dts/broadcom/bcmbca/*
N: bcmbca
N: bcm[9]?47622
N: bcm[9]?4912
N: bcm[9]?63138
N: bcm[9]?63146
N: bcm[9]?63148
N: bcm[9]?63158
N: bcm[9]?63178
N: bcm[9]?6756
N: bcm[9]?6813
N: bcm[9]?6846
N: bcm[9]?6855
N: bcm[9]?6856
N: bcm[9]?6858
N: bcm[9]?6878
BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE
M: Florian Fainelli <f.fainelli@gmail.com>
......@@ -3959,14 +3972,6 @@ S: Maintained
F: arch/arm/boot/dts/bcm47189*
F: arch/arm/boot/dts/bcm53573*
BROADCOM BCM63XX ARM ARCHITECTURE
M: Florian Fainelli <f.fainelli@gmail.com>
R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
T: git git://github.com/broadcom/stblinux.git
N: bcm63xx
BROADCOM BCM63XX/BCM33XX UDC DRIVER
M: Kevin Cernekee <cernekee@gmail.com>
L: linux-usb@vger.kernel.org
......
arch/arm/Kconfig.debug
View file @ e233cc59
......@@ -271,7 +271,7 @@ choice
config DEBUG_BCM63XX_UART
bool "Kernel low-level debugging on BCM63XX UART"
depends on ARCH_BCM_63XX
depends on ARCH_BCMBCA
config DEBUG_BERLIN_UART
bool "Marvell Berlin SoC Debug UART"
......
arch/arm/mach-at91/sam_secure.c
View file @ e233cc59
......@@ -27,6 +27,12 @@ struct arm_smccc_res sam_smccc_call(u32 fn, u32 arg0, u32 arg1)
return res;
}
bool sam_linux_is_optee_available(void)
{
/* If optee has been detected, then we are running in normal world */
return optee_available;
}
void __init sam_secure_init(void)
{
struct device_node *np;
......
arch/arm/mach-at91/sam_secure.h
View file @ e233cc59
......@@ -14,5 +14,6 @@
void __init sam_secure_init(void);
struct arm_smccc_res sam_smccc_call(u32 fn, u32 arg0, u32 arg1);
bool sam_linux_is_optee_available(void);
#endif /* SAM_SECURE_H */
arch/arm/mach-at91/sama5.c
View file @ e233cc59
......@@ -9,13 +9,27 @@
#include <linux/of.h>
#include <linux/of_platform.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/outercache.h>
#include <asm/system_misc.h>
#include "generic.h"
#include "sam_secure.h"
static void sama5_l2c310_write_sec(unsigned long val, unsigned reg)
{
/* OP-TEE configures the L2 cache and does not allow modifying it yet */
}
static void __init sama5_secure_cache_init(void)
{
sam_secure_init();
if (sam_linux_is_optee_available())
outer_cache.write_sec = sama5_l2c310_write_sec;
}
static void __init sama5_dt_device_init(void)
{
of_platform_default_populate(NULL, NULL, NULL);
......@@ -48,7 +62,6 @@ MACHINE_END
static void __init sama5d2_init(void)
{
of_platform_default_populate(NULL, NULL, NULL);
sam_secure_init();
sama5d2_pm_init();
}
......@@ -60,6 +73,7 @@ static const char *const sama5d2_compat[] __initconst = {
DT_MACHINE_START(sama5d2, "Atmel SAMA5")
/* Maintainer: Atmel */
.init_machine = sama5d2_init,
.init_early = sama5_secure_cache_init,
.dt_compat = sama5d2_compat,
.l2c_aux_mask = ~0UL,
MACHINE_END
arch/arm/mach-bcm/Kconfig
View file @ e233cc59
......@@ -54,8 +54,6 @@ config ARCH_BCM_NSP
select ARM_ERRATA_775420
select ARM_ERRATA_764369 if SMP
select ARM_TIMER_SP804
select THERMAL
select THERMAL_OF
help
Support for Broadcom Northstar Plus SoC.
Broadcom Northstar Plus family of SoCs are used for switching control
......@@ -182,23 +180,6 @@ config ARCH_BCM_53573
The base chip is BCM53573 and there are some packaging modifications
like BCM47189 and BCM47452.
config ARCH_BCM_63XX
bool "Broadcom BCM63xx DSL SoC"
depends on ARCH_MULTI_V7
select ARCH_HAS_RESET_CONTROLLER
select ARM_ERRATA_754322
select ARM_ERRATA_764369 if SMP
select ARM_GIC
select ARM_GLOBAL_TIMER
select CACHE_L2X0
select HAVE_ARM_ARCH_TIMER
select HAVE_ARM_TWD if SMP
select HAVE_ARM_SCU if SMP
help
This enables support for systems based on Broadcom DSL SoCs.
It currently supports the 'BCM63XX' ARM-based family, which includes
the BCM63138 variant.
config ARCH_BRCMSTB
bool "Broadcom BCM7XXX based boards"
depends on ARCH_MULTI_V7
......@@ -218,8 +199,8 @@ config ARCH_BRCMSTB
This enables support for Broadcom ARM-based set-top box chipsets,
including the 7445 family of chips.
config ARCH_BCMBCA
bool "Broadcom Broadband SoC"
menuconfig ARCH_BCMBCA
bool "Broadcom Broadband Carrier Access (BCA) origin SoC"
depends on ARCH_MULTI_V7
select ARM_AMBA
select ARM_GIC
......@@ -230,4 +211,46 @@ config ARCH_BCMBCA
This enables support for Broadcom BCA ARM-based broadband chipsets,
including the DSL, PON and Wireless family of chips.
comment "BCMBCA sub platforms"
if ARCH_BCMBCA
config ARCH_BCMBCA_CORTEXA7
bool "Cortex-A7 SoCs"
help
Say Y if you intend to run the kernel on a Broadcom Broadband ARM A7
based chipset.
This enables support for Broadcom BCA ARM A7 broadband chipsets,
including various DSL, PON and Wireless family of chips.
config ARCH_BCMBCA_CORTEXA9
bool "Cortex-A9 SoCS"
select ARM_ERRATA_754322
select ARM_ERRATA_764369 if SMP
select ARCH_HAS_RESET_CONTROLLER
select ARM_GLOBAL_TIMER
select CACHE_L2X0
select HAVE_ARM_TWD if SMP
select HAVE_ARM_SCU if SMP
help
Say Y if you intend to run the kernel on a Broadcom Broadband ARM A9
based BCA chipset.
This enables support for Broadcom BCA ARM A9 broadband chipset. Currently
only DSL chip BCM63138.
config ARCH_BCMBCA_BRAHMAB15
bool "Brahma-B15 SoCs"
select ARM_ERRATA_798181 if SMP
help
Say Y if you intend to run the kernel on a Broadcom Broadband ARM B15
based BCA chipset.
This enables support for Broadcom BCA ARM B15 broadband chipset. Currently
only DSL chip BCM63148.
endif
endif
arch/arm/mach-bcm/Makefile
View file @ e233cc59
......@@ -57,14 +57,13 @@ ifeq ($(CONFIG_ARCH_BCM_5301X),y)
obj-$(CONFIG_SMP) += platsmp.o
endif
# BCM63XXx
ifeq ($(CONFIG_ARCH_BCM_63XX),y)
obj-y += bcm63xx.o
obj-$(CONFIG_SMP) += bcm63xx_smp.o bcm63xx_pmb.o
endif
ifeq ($(CONFIG_ARCH_BRCMSTB),y)
CFLAGS_platsmp-brcmstb.o += -march=armv7-a
obj-y += brcmstb.o
obj-$(CONFIG_SMP) += platsmp-brcmstb.o
endif
# BCMBCA
ifeq ($(CONFIG_ARCH_BCMBCA),y)
obj-$(CONFIG_SMP) += bcm63xx_smp.o bcm63xx_pmb.o
endif
arch/arm/mach-bcm/bcm63xx.c deleted 100644 → 0
View file @ 9de1f9c8
/*
* Copyright (C) 2014 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/of_platform.h>
#include <asm/mach/arch.h>
static const char * const bcm63xx_dt_compat[] = {
"brcm,bcm63138",
NULL
};
DT_MACHINE_START(BCM63XXX_DT, "BCM63xx DSL SoC")
.dt_compat = bcm63xx_dt_compat,
.l2c_aux_val = 0,
.l2c_aux_mask = ~0,
MACHINE_END
arch/arm/mach-bcm/bcm_kona_smc.c
View file @ e233cc59
......@@ -52,6 +52,7 @@ int __init bcm_kona_smc_init(void)
return -ENODEV;
prop_val = of_get_address(node, 0, &prop_size, NULL);
of_node_put(node);
if (!prop_val)
return -EINVAL;
......
arch/arm/mach-davinci/Kconfig
View file @ e233cc59
......@@ -19,21 +19,11 @@ config ARCH_DAVINCI_DMx
comment "DaVinci Core Type"
config ARCH_DAVINCI_DM644x
bool "DaVinci 644x based system"
select DAVINCI_AINTC
select ARCH_DAVINCI_DMx
config ARCH_DAVINCI_DM355
bool "DaVinci 355 based system"
select DAVINCI_AINTC
select ARCH_DAVINCI_DMx
config ARCH_DAVINCI_DM646x
bool "DaVinci 646x based system"
select DAVINCI_AINTC
select ARCH_DAVINCI_DMx
config ARCH_DAVINCI_DA830
bool "DA830/OMAP-L137/AM17x based system"
depends on !ARCH_DAVINCI_DMx || (AUTO_ZRELADDR && ARM_PATCH_PHYS_VIRT)
......@@ -67,28 +57,6 @@ config MACH_DA8XX_DT
Say y here to include support for TI DaVinci DA850 based using
Flattened Device Tree. More information at Documentation/devicetree
config MACH_DAVINCI_EVM
bool "TI DM644x EVM"
default ARCH_DAVINCI_DM644x
depends on ARCH_DAVINCI_DM644x
help
Configure this option to specify the whether the board used
for development is a DM644x EVM
config MACH_SFFSDR
bool "Lyrtech SFFSDR"
depends on ARCH_DAVINCI_DM644x
help
Say Y here to select the Lyrtech Small Form Factor
Software Defined Radio (SFFSDR) board.
config MACH_NEUROS_OSD2
bool "Neuros OSD2 Open Television Set Top Box"
depends on ARCH_DAVINCI_DM644x
help
Configure this option to specify the whether the board used
for development is a Neuros OSD2 Open Set Top Box.
config MACH_DAVINCI_DM355_EVM
bool "TI DM355 EVM"
default ARCH_DAVINCI_DM355
......@@ -104,18 +72,6 @@ config MACH_DM355_LEOPARD
Configure this option to specify the whether the board used
for development is a DM355 Leopard board.
config MACH_DAVINCI_DM6467_EVM
bool "TI DM6467 EVM"
default ARCH_DAVINCI_DM646x
depends on ARCH_DAVINCI_DM646x
select MACH_DAVINCI_DM6467TEVM
help
Configure this option to specify the whether the board used
for development is a DM6467 EVM
config MACH_DAVINCI_DM6467TEVM
bool
config MACH_DAVINCI_DM365_EVM
bool "TI DM365 EVM"
default ARCH_DAVINCI_DM365
......
arch/arm/mach-davinci/Makefile
View file @ e233cc59
......@@ -10,21 +10,15 @@ obj-y := serial.o usb.o common.o sram.o
obj-$(CONFIG_DAVINCI_MUX) += mux.o
# Chip specific
obj-$(CONFIG_ARCH_DAVINCI_DM644x) += dm644x.o devices.o
obj-$(CONFIG_ARCH_DAVINCI_DM355) += dm355.o devices.o
obj-$(CONFIG_ARCH_DAVINCI_DM646x) += dm646x.o devices.o
obj-$(CONFIG_ARCH_DAVINCI_DM365) += dm365.o devices.o
obj-$(CONFIG_ARCH_DAVINCI_DA830) += da830.o devices-da8xx.o usb-da8xx.o
obj-$(CONFIG_ARCH_DAVINCI_DA850) += da850.o devices-da8xx.o usb-da8xx.o
# Board specific
obj-$(CONFIG_MACH_DA8XX_DT) += da8xx-dt.o pdata-quirks.o
obj-$(CONFIG_MACH_DAVINCI_EVM) += board-dm644x-evm.o
obj-$(CONFIG_MACH_SFFSDR) += board-sffsdr.o
obj-$(CONFIG_MACH_NEUROS_OSD2) += board-neuros-osd2.o
obj-$(CONFIG_MACH_DAVINCI_DM355_EVM) += board-dm355-evm.o
obj-$(CONFIG_MACH_DM355_LEOPARD) += board-dm355-leopard.o
obj-$(CONFIG_MACH_DAVINCI_DM6467_EVM) += board-dm646x-evm.o
obj-$(CONFIG_MACH_DAVINCI_DM365_EVM) += board-dm365-evm.o
obj-$(CONFIG_MACH_DAVINCI_DA830_EVM) += board-da830-evm.o
obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += board-da850-evm.o
......
arch/arm/mach-davinci/board-dm644x-evm.c deleted 100644 → 0
View file @ 9de1f9c8
/*
* TI DaVinci EVM board support
*
* Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
*
* 2007 (c) MontaVista Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/gpio/machine.h>
#include <linux/i2c.h>
#include <linux/platform_data/pcf857x.h>
#include <linux/platform_data/gpio-davinci.h>
#include <linux/property.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/rawnand.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/physmap.h>
#include <linux/nvmem-provider.h>
#include <linux/phy.h>
#include <linux/clk.h>
#include <linux/videodev2.h>
#include <linux/v4l2-dv-timings.h>
#include <linux/export.h>
#include <linux/leds.h>
#include <linux/regulator/fixed.h>
#include <linux/regulator/machine.h>
#include <media/i2c/tvp514x.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <linux/platform_data/i2c-davinci.h>
#include <linux/platform_data/mtd-davinci.h>
#include <linux/platform_data/mmc-davinci.h>
#include <linux/platform_data/usb-davinci.h>
#include <linux/platform_data/mtd-davinci-aemif.h>
#include <linux/platform_data/ti-aemif.h>
#include "davinci.h"
#include "common.h"
#include "mux.h"
#include "serial.h"
#include "irqs.h"
#define DM644X_EVM_PHY_ID "davinci_mdio-0:01"
#define LXT971_PHY_ID (0x001378e2)
#define LXT971_PHY_MASK (0xfffffff0)
static struct mtd_partition davinci_evm_norflash_partitions[] = {
/* bootloader (UBL, U-Boot, etc) in first 5 sectors */
{
.name = "bootloader",
.offset = 0,
.size = 5 * SZ_64K,
.mask_flags = MTD_WRITEABLE, /* force read-only */
},
/* bootloader params in the next 1 sectors */
{
.name = "params",
.offset = MTDPART_OFS_APPEND,
.size = SZ_64K,
.mask_flags = 0,
},
/* kernel */
{
.name = "kernel",
.offset = MTDPART_OFS_APPEND,
.size = SZ_2M,
.mask_flags = 0
},
/* file system */
{
.name = "filesystem",
.offset = MTDPART_OFS_APPEND,
.size = MTDPART_SIZ_FULL,
.mask_flags = 0
}
};
static struct physmap_flash_data davinci_evm_norflash_data = {
.width = 2,
.parts = davinci_evm_norflash_partitions,
.nr_parts = ARRAY_SIZE(davinci_evm_norflash_partitions),
};
/* NOTE: CFI probe will correctly detect flash part as 32M, but EMIF
* limits addresses to 16M, so using addresses past 16M will wrap */
static struct resource davinci_evm_norflash_resource = {
.start = DM644X_ASYNC_EMIF_DATA_CE0_BASE,
.end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
.flags = IORESOURCE_MEM,
};
static struct platform_device davinci_evm_norflash_device = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &davinci_evm_norflash_data,
},
.num_resources = 1,
.resource = &davinci_evm_norflash_resource,
};
/* DM644x EVM includes a 64 MByte small-page NAND flash (16K blocks).
* It may used instead of the (default) NOR chip to boot, using TI's
* tools to install the secondary boot loader (UBL) and U-Boot.
*/
static struct mtd_partition davinci_evm_nandflash_partition[] = {
/* Bootloader layout depends on whose u-boot is installed, but we
* can hide all the details.
* - block 0 for u-boot environment ... in mainline u-boot
* - block 1 for UBL (plus up to four backup copies in blocks 2..5)
* - blocks 6...? for u-boot
* - blocks 16..23 for u-boot environment ... in TI's u-boot
*/
{
.name = "bootloader",
.offset = 0,
.size = SZ_256K + SZ_128K,
.mask_flags = MTD_WRITEABLE, /* force read-only */
},
/* Kernel */
{
.name = "kernel",
.offset = MTDPART_OFS_APPEND,
.size = SZ_4M,
.mask_flags = 0,
},
/* File system (older GIT kernels started this on the 5MB mark) */
{
.name = "filesystem",
.offset = MTDPART_OFS_APPEND,
.size = MTDPART_SIZ_FULL,
.mask_flags = 0,
}
/* A few blocks at end hold a flash BBT ... created by TI's CCS
* using flashwriter_nand.out, but ignored by TI's versions of
* Linux and u-boot. We boot faster by using them.
*/
};
static struct davinci_aemif_timing davinci_evm_nandflash_timing = {
.wsetup = 20,
.wstrobe = 40,
.whold = 20,
.rsetup = 10,
.rstrobe = 40,
.rhold = 10,
.ta = 40,
};
static struct davinci_nand_pdata davinci_evm_nandflash_data = {
.core_chipsel = 0,
.parts = davinci_evm_nandflash_partition,
.nr_parts = ARRAY_SIZE(davinci_evm_nandflash_partition),
.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
.ecc_bits = 1,
.bbt_options = NAND_BBT_USE_FLASH,
.timing = &davinci_evm_nandflash_timing,
};
static struct resource davinci_evm_nandflash_resource[] = {
{
.start = DM644X_ASYNC_EMIF_DATA_CE0_BASE,
.end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
.flags = IORESOURCE_MEM,
}, {
.start = DM644X_ASYNC_EMIF_CONTROL_BASE,
.end = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
};
static struct resource davinci_evm_aemif_resource[] = {
{
.start = DM644X_ASYNC_EMIF_CONTROL_BASE,
.end = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
};
static struct aemif_abus_data davinci_evm_aemif_abus_data[] = {
{
.cs = 1,
},
};
static struct platform_device davinci_evm_nandflash_devices[] = {
{
.name = "davinci_nand",
.id = 0,
.dev = {
.platform_data = &davinci_evm_nandflash_data,
},
.num_resources = ARRAY_SIZE(davinci_evm_nandflash_resource),
.resource = davinci_evm_nandflash_resource,
},
};
static struct aemif_platform_data davinci_evm_aemif_pdata = {
.abus_data = davinci_evm_aemif_abus_data,
.num_abus_data = ARRAY_SIZE(davinci_evm_aemif_abus_data),
.sub_devices = davinci_evm_nandflash_devices,
.num_sub_devices = ARRAY_SIZE(davinci_evm_nandflash_devices),
};
static struct platform_device davinci_evm_aemif_device = {
.name = "ti-aemif",
.id = -1,
.dev = {
.platform_data = &davinci_evm_aemif_pdata,
},
.resource = davinci_evm_aemif_resource,
.num_resources = ARRAY_SIZE(davinci_evm_aemif_resource),
};
static u64 davinci_fb_dma_mask = DMA_BIT_MASK(32);
static struct platform_device davinci_fb_device = {
.name = "davincifb",
.id = -1,
.dev = {
.dma_mask = &davinci_fb_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.num_resources = 0,
};
static struct tvp514x_platform_data dm644xevm_tvp5146_pdata = {
.clk_polarity = 0,
.hs_polarity = 1,
.vs_polarity = 1
};
#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
/* Inputs available at the TVP5146 */
static struct v4l2_input dm644xevm_tvp5146_inputs[] = {
{
.index = 0,
.name = "Composite",
.type = V4L2_INPUT_TYPE_CAMERA,
.std = TVP514X_STD_ALL,
},
{
.index = 1,
.name = "S-Video",
.type = V4L2_INPUT_TYPE_CAMERA,
.std = TVP514X_STD_ALL,
},
};
/*
* this is the route info for connecting each input to decoder
* ouput that goes to vpfe. There is a one to one correspondence
* with tvp5146_inputs
*/
static struct vpfe_route dm644xevm_tvp5146_routes[] = {
{
.input = INPUT_CVBS_VI2B,
.output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
},
{
.input = INPUT_SVIDEO_VI2C_VI1C,
.output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
},
};
static struct vpfe_subdev_info dm644xevm_vpfe_sub_devs[] = {
{
.name = "tvp5146",
.grp_id = 0,
.num_inputs = ARRAY_SIZE(dm644xevm_tvp5146_inputs),
.inputs = dm644xevm_tvp5146_inputs,
.routes = dm644xevm_tvp5146_routes,
.can_route = 1,
.ccdc_if_params = {
.if_type = VPFE_BT656,
.hdpol = VPFE_PINPOL_POSITIVE,
.vdpol = VPFE_PINPOL_POSITIVE,
},
.board_info = {
I2C_BOARD_INFO("tvp5146", 0x5d),
.platform_data = &dm644xevm_tvp5146_pdata,
},
},
};
static struct vpfe_config dm644xevm_capture_cfg = {
.num_subdevs = ARRAY_SIZE(dm644xevm_vpfe_sub_devs),
.i2c_adapter_id = 1,
.sub_devs = dm644xevm_vpfe_sub_devs,
.card_name = "DM6446 EVM",
.ccdc = "DM6446 CCDC",
};
static struct platform_device rtc_dev = {
.name = "rtc_davinci_evm",
.id = -1,
};
/*----------------------------------------------------------------------*/
#ifdef CONFIG_I2C
/*
* I2C GPIO expanders
*/
#define PCF_Uxx_BASE(x) (DAVINCI_N_GPIO + ((x) * 8))
/* U2 -- LEDs */
static struct gpio_led evm_leds[] = {
{ .name = "DS8", .active_low = 1,
.default_trigger = "heartbeat", },
{ .name = "DS7", .active_low = 1, },
{ .name = "DS6", .active_low = 1, },
{ .name = "DS5", .active_low = 1, },
{ .name = "DS4", .active_low = 1, },
{ .name = "DS3", .active_low = 1, },
{ .name = "DS2", .active_low = 1,
.default_trigger = "mmc0", },
{ .name = "DS1", .active_low = 1,
.default_trigger = "disk-activity", },
};
static const struct gpio_led_platform_data evm_led_data = {
.num_leds = ARRAY_SIZE(evm_leds),
.leds = evm_leds,
};
static struct platform_device *evm_led_dev;
static int
evm_led_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
{
struct gpio_led *leds = evm_leds;
int status;
while (ngpio--) {
leds->gpio = gpio++;
leds++;
}
/* what an extremely annoying way to be forced to handle
* device unregistration ...
*/
evm_led_dev = platform_device_alloc("leds-gpio", 0);
platform_device_add_data(evm_led_dev,
&evm_led_data, sizeof evm_led_data);
evm_led_dev->dev.parent = &client->dev;
status = platform_device_add(evm_led_dev);
if (status < 0) {
platform_device_put(evm_led_dev);
evm_led_dev = NULL;
}
return status;
}
static void
evm_led_teardown(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
{
if (evm_led_dev) {
platform_device_unregister(evm_led_dev);
evm_led_dev = NULL;
}
}
static struct pcf857x_platform_data pcf_data_u2 = {
.gpio_base = PCF_Uxx_BASE(0),
.setup = evm_led_setup,
.teardown = evm_led_teardown,
};
/* U18 - A/V clock generator and user switch */
static int sw_gpio;
static ssize_t
sw_show(struct device *d, struct device_attribute *a, char *buf)
{
char *s = gpio_get_value_cansleep(sw_gpio) ? "on\n" : "off\n";
strcpy(buf, s);
return strlen(s);
}
static DEVICE_ATTR(user_sw, S_IRUGO, sw_show, NULL);
static int
evm_u18_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
{
int status;
/* export dip switch option */
sw_gpio = gpio + 7;
status = gpio_request(sw_gpio, "user_sw");
if (status == 0)
status = gpio_direction_input(sw_gpio);
if (status == 0)
status = device_create_file(&client->dev, &dev_attr_user_sw);
else
gpio_free(sw_gpio);
if (status != 0)
sw_gpio = -EINVAL;
/* audio PLL: 48 kHz (vs 44.1 or 32), single rate (vs double) */
gpio_request(gpio + 3, "pll_fs2");
gpio_direction_output(gpio + 3, 0);
gpio_request(gpio + 2, "pll_fs1");
gpio_direction_output(gpio + 2, 0);
gpio_request(gpio + 1, "pll_sr");
gpio_direction_output(gpio + 1, 0);
return 0;
}
static void
evm_u18_teardown(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
{
gpio_free(gpio + 1);
gpio_free(gpio + 2);
gpio_free(gpio + 3);
if (sw_gpio > 0) {
device_remove_file(&client->dev, &dev_attr_user_sw);
gpio_free(sw_gpio);
}
}
static struct pcf857x_platform_data pcf_data_u18 = {
.gpio_base = PCF_Uxx_BASE(1),
.n_latch = (1 << 3) | (1 << 2) | (1 << 1),
.setup = evm_u18_setup,
.teardown = evm_u18_teardown,
};
/* U35 - various I/O signals used to manage USB, CF, ATA, etc */
static int
evm_u35_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
{
/* p0 = nDRV_VBUS (initial: don't supply it) */
gpio_request(gpio + 0, "nDRV_VBUS");
gpio_direction_output(gpio + 0, 1);
/* p1 = VDDIMX_EN */
gpio_request(gpio + 1, "VDDIMX_EN");
gpio_direction_output(gpio + 1, 1);
/* p2 = VLYNQ_EN */
gpio_request(gpio + 2, "VLYNQ_EN");
gpio_direction_output(gpio + 2, 1);
/* p3 = n3V3_CF_RESET (initial: stay in reset) */
gpio_request(gpio + 3, "nCF_RESET");
gpio_direction_output(gpio + 3, 0);
/* (p4 unused) */
/* p5 = 1V8_WLAN_RESET (initial: stay in reset) */
gpio_request(gpio + 5, "WLAN_RESET");
gpio_direction_output(gpio + 5, 1);
/* p6 = nATA_SEL (initial: select) */
gpio_request(gpio + 6, "nATA_SEL");
gpio_direction_output(gpio + 6, 0);
/* p7 = nCF_SEL (initial: deselect) */
gpio_request(gpio + 7, "nCF_SEL");
gpio_direction_output(gpio + 7, 1);
return 0;
}
static void
evm_u35_teardown(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
{
gpio_free(gpio + 7);
gpio_free(gpio + 6);
gpio_free(gpio + 5);
gpio_free(gpio + 3);
gpio_free(gpio + 2);
gpio_free(gpio + 1);
gpio_free(gpio + 0);
}
static struct pcf857x_platform_data pcf_data_u35 = {
.gpio_base = PCF_Uxx_BASE(2),
.setup = evm_u35_setup,
.teardown = evm_u35_teardown,
};
/*----------------------------------------------------------------------*/
/* Most of this EEPROM is unused, but U-Boot uses some data:
* - 0x7f00, 6 bytes Ethernet Address
* - 0x0039, 1 byte NTSC vs PAL (bit 0x80 == PAL)
* - ... newer boards may have more
*/
static struct nvmem_cell_info dm644evm_nvmem_cells[] = {
{
.name = "macaddr",
.offset = 0x7f00,
.bytes = ETH_ALEN,
}
};
static struct nvmem_cell_table dm644evm_nvmem_cell_table = {
.nvmem_name = "1-00500",
.cells = dm644evm_nvmem_cells,
.ncells = ARRAY_SIZE(dm644evm_nvmem_cells),
};
static struct nvmem_cell_lookup dm644evm_nvmem_cell_lookup = {
.nvmem_name = "1-00500",
.cell_name = "macaddr",
.dev_id = "davinci_emac.1",
.con_id = "mac-address",
};
static const struct property_entry eeprom_properties[] = {
PROPERTY_ENTRY_U32("pagesize", 64),
{ }
};
static const struct software_node eeprom_node = {
.properties = eeprom_properties,
};
/*
* MSP430 supports RTC, card detection, input from IR remote, and
* a bit more. It triggers interrupts on GPIO(7) from pressing
* buttons on the IR remote, and for card detect switches.
*/
static struct i2c_client *dm6446evm_msp;
static int dm6446evm_msp_probe(struct i2c_client *client)
{
dm6446evm_msp = client;
return 0;
}
static int dm6446evm_msp_remove(struct i2c_client *client)
{
dm6446evm_msp = NULL;
return 0;
}
static const struct i2c_device_id dm6446evm_msp_ids[] = {
{ "dm6446evm_msp", 0, },
{ /* end of list */ },
};
static struct i2c_driver dm6446evm_msp_driver = {
.driver.name = "dm6446evm_msp",
.id_table = dm6446evm_msp_ids,
.probe_new = dm6446evm_msp_probe,
.remove = dm6446evm_msp_remove,
};
static int dm6444evm_msp430_get_pins(void)
{
static const char txbuf[2] = { 2, 4, };
char buf[4];
struct i2c_msg msg[2] = {
{
.flags = 0,
.len = 2,
.buf = (void __force *)txbuf,
},
{
.flags = I2C_M_RD,
.len = 4,
.buf = buf,
},
};
int status;
if (!dm6446evm_msp)
return -ENXIO;
msg[0].addr = dm6446evm_msp->addr;
msg[1].addr = dm6446evm_msp->addr;
/* Command 4 == get input state, returns port 2 and port3 data
* S Addr W [A] len=2 [A] cmd=4 [A]
* RS Addr R [A] [len=4] A [cmd=4] A [port2] A [port3] N P
*/
status = i2c_transfer(dm6446evm_msp->adapter, msg, 2);
if (status < 0)
return status;
dev_dbg(&dm6446evm_msp->dev, "PINS: %4ph\n", buf);
return (buf[3] << 8) | buf[2];
}
static int dm6444evm_mmc_get_cd(int module)
{
int status = dm6444evm_msp430_get_pins();
return (status < 0) ? status : !(status & BIT(1));
}
static int dm6444evm_mmc_get_ro(int module)
{
int status = dm6444evm_msp430_get_pins();
return (status < 0) ? status : status & BIT(6 + 8);
}
static struct davinci_mmc_config dm6446evm_mmc_config = {
.get_cd = dm6444evm_mmc_get_cd,
.get_ro = dm6444evm_mmc_get_ro,
.wires = 4,
};
static struct i2c_board_info __initdata i2c_info[] = {
{
I2C_BOARD_INFO("dm6446evm_msp", 0x23),
},
{
I2C_BOARD_INFO("pcf8574", 0x38),
.platform_data = &pcf_data_u2,
},
{
I2C_BOARD_INFO("pcf8574", 0x39),
.platform_data = &pcf_data_u18,
},
{
I2C_BOARD_INFO("pcf8574", 0x3a),
.platform_data = &pcf_data_u35,
},
{
I2C_BOARD_INFO("24c256", 0x50),
.swnode = &eeprom_node,
},
{
I2C_BOARD_INFO("tlv320aic33", 0x1b),
},
};
#define DM644X_I2C_SDA_PIN GPIO_TO_PIN(2, 12)
#define DM644X_I2C_SCL_PIN GPIO_TO_PIN(2, 11)
static struct gpiod_lookup_table i2c_recovery_gpiod_table = {
.dev_id = "i2c_davinci.1",
.table = {
GPIO_LOOKUP("davinci_gpio", DM644X_I2C_SDA_PIN, "sda",
GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
GPIO_LOOKUP("davinci_gpio", DM644X_I2C_SCL_PIN, "scl",
GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
{ }
},
};
/* The msp430 uses a slow bitbanged I2C implementation (ergo 20 KHz),
* which requires 100 usec of idle bus after i2c writes sent to it.
*/
static struct davinci_i2c_platform_data i2c_pdata = {
.bus_freq = 20 /* kHz */,
.bus_delay = 100 /* usec */,
.gpio_recovery = true,
};
static void __init evm_init_i2c(void)
{
gpiod_add_lookup_table(&i2c_recovery_gpiod_table);
davinci_init_i2c(&i2c_pdata);
i2c_add_driver(&dm6446evm_msp_driver);
i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
}
#endif
/* Fixed regulator support */
static struct regulator_consumer_supply fixed_supplies_3_3v[] = {
/* Baseboard 3.3V: 5V -> TPS54310PWP -> 3.3V */
REGULATOR_SUPPLY("AVDD", "1-001b"),
REGULATOR_SUPPLY("DRVDD", "1-001b"),
};
static struct regulator_consumer_supply fixed_supplies_1_8v[] = {
/* Baseboard 1.8V: 5V -> TPS54310PWP -> 1.8V */
REGULATOR_SUPPLY("IOVDD", "1-001b"),
REGULATOR_SUPPLY("DVDD", "1-001b"),
};
#define VENC_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
/* venc standard timings */
static struct vpbe_enc_mode_info dm644xevm_enc_std_timing[] = {
{
.name = "ntsc",
.timings_type = VPBE_ENC_STD,
.std_id = V4L2_STD_NTSC,
.interlaced = 1,
.xres = 720,
.yres = 480,
.aspect = {11, 10},
.fps = {30000, 1001},
.left_margin = 0x79,
.upper_margin = 0x10,
},
{
.name = "pal",
.timings_type = VPBE_ENC_STD,
.std_id = V4L2_STD_PAL,
.interlaced = 1,
.xres = 720,
.yres = 576,
.aspect = {54, 59},
.fps = {25, 1},
.left_margin = 0x7e,
.upper_margin = 0x16,
},
};
/* venc dv preset timings */
static struct vpbe_enc_mode_info dm644xevm_enc_preset_timing[] = {
{
.name = "480p59_94",
.timings_type = VPBE_ENC_DV_TIMINGS,
.dv_timings = V4L2_DV_BT_CEA_720X480P59_94,
.interlaced = 0,
.xres = 720,
.yres = 480,
.aspect = {1, 1},
.fps = {5994, 100},
.left_margin = 0x80,
.upper_margin = 0x20,
},
{
.name = "576p50",
.timings_type = VPBE_ENC_DV_TIMINGS,
.dv_timings = V4L2_DV_BT_CEA_720X576P50,
.interlaced = 0,
.xres = 720,
.yres = 576,
.aspect = {1, 1},
.fps = {50, 1},
.left_margin = 0x7e,
.upper_margin = 0x30,
},
};
/*
* The outputs available from VPBE + encoders. Keep the order same
* as that of encoders. First those from venc followed by that from
* encoders. Index in the output refers to index on a particular encoder.
* Driver uses this index to pass it to encoder when it supports more
* than one output. Userspace applications use index of the array to
* set an output.
*/
static struct vpbe_output dm644xevm_vpbe_outputs[] = {
{
.output = {
.index = 0,
.name = "Composite",
.type = V4L2_OUTPUT_TYPE_ANALOG,
.std = VENC_STD_ALL,
.capabilities = V4L2_OUT_CAP_STD,
},
.subdev_name = DM644X_VPBE_VENC_SUBDEV_NAME,
.default_mode = "ntsc",
.num_modes = ARRAY_SIZE(dm644xevm_enc_std_timing),
.modes = dm644xevm_enc_std_timing,
},
{
.output = {
.index = 1,
.name = "Component",
.type = V4L2_OUTPUT_TYPE_ANALOG,
.capabilities = V4L2_OUT_CAP_DV_TIMINGS,
},
.subdev_name = DM644X_VPBE_VENC_SUBDEV_NAME,
.default_mode = "480p59_94",
.num_modes = ARRAY_SIZE(dm644xevm_enc_preset_timing),
.modes = dm644xevm_enc_preset_timing,
},
};
static struct vpbe_config dm644xevm_display_cfg = {
.module_name = "dm644x-vpbe-display",
.i2c_adapter_id = 1,
.osd = {
.module_name = DM644X_VPBE_OSD_SUBDEV_NAME,
},
.venc = {
.module_name = DM644X_VPBE_VENC_SUBDEV_NAME,
},
.num_outputs = ARRAY_SIZE(dm644xevm_vpbe_outputs),
.outputs = dm644xevm_vpbe_outputs,
};
static struct platform_device *davinci_evm_devices[] __initdata = {
&davinci_fb_device,
&rtc_dev,
};
static void __init
davinci_evm_map_io(void)
{
dm644x_init();
}
static int davinci_phy_fixup(struct phy_device *phydev)
{
unsigned int control;
/* CRITICAL: Fix for increasing PHY signal drive strength for
* TX lockup issue. On DaVinci EVM, the Intel LXT971 PHY
* signal strength was low causing TX to fail randomly. The
* fix is to Set bit 11 (Increased MII drive strength) of PHY
* register 26 (Digital Config register) on this phy. */
control = phy_read(phydev, 26);
phy_write(phydev, 26, (control | 0x800));
return 0;
}
#define HAS_ATA (IS_ENABLED(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
IS_ENABLED(CONFIG_PATA_BK3710))
#define HAS_NOR IS_ENABLED(CONFIG_MTD_PHYSMAP)
#define HAS_NAND IS_ENABLED(CONFIG_MTD_NAND_DAVINCI)
#define GPIO_nVBUS_DRV 160
static struct gpiod_lookup_table dm644evm_usb_gpio_table = {
.dev_id = "musb-davinci",
.table = {
GPIO_LOOKUP("davinci_gpio", GPIO_nVBUS_DRV, NULL,
GPIO_ACTIVE_HIGH),
{ }
},
};
static __init void davinci_evm_init(void)
{
int ret;
struct clk *aemif_clk;
struct davinci_soc_info *soc_info = &davinci_soc_info;
dm644x_register_clocks();
regulator_register_always_on(0, "fixed-dummy", fixed_supplies_1_8v,
ARRAY_SIZE(fixed_supplies_1_8v), 1800000);
regulator_register_always_on(1, "fixed-dummy", fixed_supplies_3_3v,
ARRAY_SIZE(fixed_supplies_3_3v), 3300000);
dm644x_init_devices();
ret = dm644x_gpio_register();
if (ret)
pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
aemif_clk = clk_get(NULL, "aemif");
clk_prepare_enable(aemif_clk);
if (HAS_ATA) {
if (HAS_NAND || HAS_NOR)
pr_warn("WARNING: both IDE and Flash are enabled, but they share AEMIF pins\n"
"\tDisable IDE for NAND/NOR support\n");
davinci_init_ide();
} else if (HAS_NAND || HAS_NOR) {
davinci_cfg_reg(DM644X_HPIEN_DISABLE);
davinci_cfg_reg(DM644X_ATAEN_DISABLE);
/* only one device will be jumpered and detected */
if (HAS_NAND) {
platform_device_register(&davinci_evm_aemif_device);
#ifdef CONFIG_I2C
evm_leds[7].default_trigger = "nand-disk";
#endif
if (HAS_NOR)
pr_warn("WARNING: both NAND and NOR flash are enabled; disable one of them.\n");
} else if (HAS_NOR)
platform_device_register(&davinci_evm_norflash_device);
}
platform_add_devices(davinci_evm_devices,
ARRAY_SIZE(davinci_evm_devices));
#ifdef CONFIG_I2C
nvmem_add_cell_table(&dm644evm_nvmem_cell_table);
nvmem_add_cell_lookups(&dm644evm_nvmem_cell_lookup, 1);
evm_init_i2c();
davinci_setup_mmc(0, &dm6446evm_mmc_config);
#endif
dm644x_init_video(&dm644xevm_capture_cfg, &dm644xevm_display_cfg);
davinci_serial_init(dm644x_serial_device);
dm644x_init_asp();
/* irlml6401 switches over 1A, in under 8 msec */
gpiod_add_lookup_table(&dm644evm_usb_gpio_table);
davinci_setup_usb(1000, 8);
if (IS_BUILTIN(CONFIG_PHYLIB)) {
soc_info->emac_pdata->phy_id = DM644X_EVM_PHY_ID;
/* Register the fixup for PHY on DaVinci */
phy_register_fixup_for_uid(LXT971_PHY_ID, LXT971_PHY_MASK,
davinci_phy_fixup);
}
}
MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM")
/* Maintainer: MontaVista Software <source@mvista.com> */
.atag_offset = 0x100,
.map_io = davinci_evm_map_io,
.init_irq = dm644x_init_irq,
.init_time = dm644x_init_time,
.init_machine = davinci_evm_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
MACHINE_END
arch/arm/mach-davinci/board-dm646x-evm.c deleted 100644 → 0
View file @ 9de1f9c8
/*
* TI DaVinci DM646X EVM board
*
* Derived from: arch/arm/mach-davinci/board-evm.c
* Copyright (C) 2006 Texas Instruments.
*
* (C) 2007-2008, MontaVista Software, Inc.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*
*/
/**************************************************************************
* Included Files
**************************************************************************/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/leds.h>
#include <linux/gpio.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>
#include <linux/property.h>
#include <linux/platform_data/pcf857x.h>
#include <linux/platform_data/ti-aemif.h>
#include <media/i2c/tvp514x.h>
#include <media/i2c/adv7343.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/rawnand.h>
#include <linux/mtd/partitions.h>
#include <linux/nvmem-provider.h>
#include <linux/clk.h>
#include <linux/export.h>
#include <linux/platform_data/gpio-davinci.h>
#include <linux/platform_data/i2c-davinci.h>
#include <linux/platform_data/mtd-davinci.h>
#include <linux/platform_data/mtd-davinci-aemif.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include "common.h"
#include "serial.h"
#include "davinci.h"
#include "irqs.h"
#define NAND_BLOCK_SIZE SZ_128K
/* Note: We are setting first partition as 'bootloader' constituting UBL, U-Boot
* and U-Boot environment this avoids dependency on any particular combination
* of UBL, U-Boot or flashing tools etc.
*/
static struct mtd_partition davinci_nand_partitions[] = {
{
/* UBL, U-Boot with environment */
.name = "bootloader",
.offset = MTDPART_OFS_APPEND,
.size = 16 * NAND_BLOCK_SIZE,
.mask_flags = MTD_WRITEABLE, /* force read-only */
}, {
.name = "kernel",
.offset = MTDPART_OFS_APPEND,
.size = SZ_4M,
.mask_flags = 0,
}, {
.name = "filesystem",
.offset = MTDPART_OFS_APPEND,
.size = MTDPART_SIZ_FULL,
.mask_flags = 0,
}
};
static struct davinci_aemif_timing dm6467tevm_nandflash_timing = {
.wsetup = 29,
.wstrobe = 24,
.whold = 14,
.rsetup = 19,
.rstrobe = 33,
.rhold = 0,
.ta = 29,
};
static struct davinci_nand_pdata davinci_nand_data = {
.core_chipsel = 0,
.mask_cle = 0x80000,
.mask_ale = 0x40000,
.parts = davinci_nand_partitions,
.nr_parts = ARRAY_SIZE(davinci_nand_partitions),
.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
.ecc_bits = 1,
.options = 0,
};
static struct resource davinci_nand_resources[] = {
{
.start = DM646X_ASYNC_EMIF_CS2_SPACE_BASE,
.end = DM646X_ASYNC_EMIF_CS2_SPACE_BASE + SZ_32M - 1,
.flags = IORESOURCE_MEM,
}, {
.start = DM646X_ASYNC_EMIF_CONTROL_BASE,
.end = DM646X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device davinci_aemif_devices[] = {
{
.name = "davinci_nand",
.id = 0,
.num_resources = ARRAY_SIZE(davinci_nand_resources),
.resource = davinci_nand_resources,
.dev = {
.platform_data = &davinci_nand_data,
},
},
};
static struct resource davinci_aemif_resources[] = {
{
.start = DM646X_ASYNC_EMIF_CONTROL_BASE,
.end = DM646X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
};
static struct aemif_abus_data davinci_aemif_abus_data[] = {
{
.cs = 1,
},
};
static struct aemif_platform_data davinci_aemif_pdata = {
.abus_data = davinci_aemif_abus_data,
.num_abus_data = ARRAY_SIZE(davinci_aemif_abus_data),
.sub_devices = davinci_aemif_devices,
.num_sub_devices = ARRAY_SIZE(davinci_aemif_devices),
};
static struct platform_device davinci_aemif_device = {
.name = "ti-aemif",
.id = -1,
.dev = {
.platform_data = &davinci_aemif_pdata,
},
.resource = davinci_aemif_resources,
.num_resources = ARRAY_SIZE(davinci_aemif_resources),
};
#define HAS_ATA (IS_ENABLED(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
IS_ENABLED(CONFIG_PATA_BK3710))
#ifdef CONFIG_I2C
/* CPLD Register 0 bits to control ATA */
#define DM646X_EVM_ATA_RST BIT(0)
#define DM646X_EVM_ATA_PWD BIT(1)
/* CPLD Register 0 Client: used for I/O Control */
static int cpld_reg0_probe(struct i2c_client *client)
{
if (HAS_ATA) {
u8 data;
struct i2c_msg msg[2] = {
{
.addr = client->addr,
.flags = I2C_M_RD,
.len = 1,
.buf = &data,
},
{
.addr = client->addr,
.flags = 0,
.len = 1,
.buf = &data,
},
};
/* Clear ATA_RSTn and ATA_PWD bits to enable ATA operation. */
i2c_transfer(client->adapter, msg, 1);
data &= ~(DM646X_EVM_ATA_RST | DM646X_EVM_ATA_PWD);
i2c_transfer(client->adapter, msg + 1, 1);
}
return 0;
}
static const struct i2c_device_id cpld_reg_ids[] = {
{ "cpld_reg0", 0, },
{ },
};
static struct i2c_driver dm6467evm_cpld_driver = {
.driver.name = "cpld_reg0",
.id_table = cpld_reg_ids,
.probe_new = cpld_reg0_probe,
};
/* LEDS */
static struct gpio_led evm_leds[] = {
{ .name = "DS1", .active_low = 1, },
{ .name = "DS2", .active_low = 1, },
{ .name = "DS3", .active_low = 1, },
{ .name = "DS4", .active_low = 1, },
};
static const struct gpio_led_platform_data evm_led_data = {
.num_leds = ARRAY_SIZE(evm_leds),
.leds = evm_leds,
};
static struct platform_device *evm_led_dev;
static int evm_led_setup(struct i2c_client *client, int gpio,
unsigned int ngpio, void *c)
{
struct gpio_led *leds = evm_leds;
int status;
while (ngpio--) {
leds->gpio = gpio++;
leds++;
}
evm_led_dev = platform_device_alloc("leds-gpio", 0);
platform_device_add_data(evm_led_dev, &evm_led_data,
sizeof(evm_led_data));
evm_led_dev->dev.parent = &client->dev;
status = platform_device_add(evm_led_dev);
if (status < 0) {
platform_device_put(evm_led_dev);
evm_led_dev = NULL;
}
return status;
}
static int evm_led_teardown(struct i2c_client *client, int gpio,
unsigned ngpio, void *c)
{
if (evm_led_dev) {
platform_device_unregister(evm_led_dev);
evm_led_dev = NULL;
}
return 0;
}
static int evm_sw_gpio[4] = { -EINVAL, -EINVAL, -EINVAL, -EINVAL };
static int evm_sw_setup(struct i2c_client *client, int gpio,
unsigned ngpio, void *c)
{
int status;
int i;
char label[10];
for (i = 0; i < 4; ++i) {
snprintf(label, 10, "user_sw%d", i);
status = gpio_request(gpio, label);
if (status)
goto out_free;
evm_sw_gpio[i] = gpio++;
status = gpio_direction_input(evm_sw_gpio[i]);
if (status)
goto out_free;
status = gpio_export(evm_sw_gpio[i], 0);
if (status)
goto out_free;
}
return 0;
out_free:
for (i = 0; i < 4; ++i) {
if (evm_sw_gpio[i] != -EINVAL) {
gpio_free(evm_sw_gpio[i]);
evm_sw_gpio[i] = -EINVAL;
}
}
return status;
}
static int evm_sw_teardown(struct i2c_client *client, int gpio,
unsigned ngpio, void *c)
{
int i;
for (i = 0; i < 4; ++i) {
if (evm_sw_gpio[i] != -EINVAL) {
gpio_unexport(evm_sw_gpio[i]);
gpio_free(evm_sw_gpio[i]);
evm_sw_gpio[i] = -EINVAL;
}
}
return 0;
}
static int evm_pcf_setup(struct i2c_client *client, int gpio,
unsigned int ngpio, void *c)
{
int status;
if (ngpio < 8)
return -EINVAL;
status = evm_sw_setup(client, gpio, 4, c);
if (status)
return status;
return evm_led_setup(client, gpio+4, 4, c);
}
static void evm_pcf_teardown(struct i2c_client *client, int gpio,
unsigned int ngpio, void *c)
{
BUG_ON(ngpio < 8);
evm_sw_teardown(client, gpio, 4, c);
evm_led_teardown(client, gpio+4, 4, c);
}
static struct pcf857x_platform_data pcf_data = {
.gpio_base = DAVINCI_N_GPIO+1,
.setup = evm_pcf_setup,
.teardown = evm_pcf_teardown,
};
/* Most of this EEPROM is unused, but U-Boot uses some data:
* - 0x7f00, 6 bytes Ethernet Address
* - ... newer boards may have more
*/
static struct nvmem_cell_info dm646x_evm_nvmem_cells[] = {
{
.name = "macaddr",
.offset = 0x7f00,
.bytes = ETH_ALEN,
}
};
static struct nvmem_cell_table dm646x_evm_nvmem_cell_table = {
.nvmem_name = "1-00500",
.cells = dm646x_evm_nvmem_cells,
.ncells = ARRAY_SIZE(dm646x_evm_nvmem_cells),
};
static struct nvmem_cell_lookup dm646x_evm_nvmem_cell_lookup = {
.nvmem_name = "1-00500",
.cell_name = "macaddr",
.dev_id = "davinci_emac.1",
.con_id = "mac-address",
};
static const struct property_entry eeprom_properties[] = {
PROPERTY_ENTRY_U32("pagesize", 64),
{ }
};
static const struct software_node eeprom_node = {
.properties = eeprom_properties,
};
#endif
static u8 dm646x_iis_serializer_direction[] = {
TX_MODE, RX_MODE, INACTIVE_MODE, INACTIVE_MODE,
};
static u8 dm646x_dit_serializer_direction[] = {
TX_MODE,
};
static struct snd_platform_data dm646x_evm_snd_data[] = {
{
.tx_dma_offset = 0x400,
.rx_dma_offset = 0x400,
.op_mode = DAVINCI_MCASP_IIS_MODE,
.num_serializer = ARRAY_SIZE(dm646x_iis_serializer_direction),
.tdm_slots = 2,
.serial_dir = dm646x_iis_serializer_direction,
.asp_chan_q = EVENTQ_0,
},
{
.tx_dma_offset = 0x400,
.rx_dma_offset = 0,
.op_mode = DAVINCI_MCASP_DIT_MODE,
.num_serializer = ARRAY_SIZE(dm646x_dit_serializer_direction),
.tdm_slots = 32,
.serial_dir = dm646x_dit_serializer_direction,
.asp_chan_q = EVENTQ_0,
},
};
#ifdef CONFIG_I2C
static struct i2c_client *cpld_client;
static int cpld_video_probe(struct i2c_client *client)
{
cpld_client = client;
return 0;
}
static int cpld_video_remove(struct i2c_client *client)
{
cpld_client = NULL;
return 0;
}
static const struct i2c_device_id cpld_video_id[] = {
{ "cpld_video", 0 },
{ }
};
static struct i2c_driver cpld_video_driver = {
.driver = {
.name = "cpld_video",
},
.probe_new = cpld_video_probe,
.remove = cpld_video_remove,
.id_table = cpld_video_id,
};
static void evm_init_cpld(void)
{
i2c_add_driver(&cpld_video_driver);
}
static struct i2c_board_info __initdata i2c_info[] = {
{
I2C_BOARD_INFO("24c256", 0x50),
.swnode = &eeprom_node,
},
{
I2C_BOARD_INFO("pcf8574a", 0x38),
.platform_data = &pcf_data,
},
{
I2C_BOARD_INFO("cpld_reg0", 0x3a),
},
{
I2C_BOARD_INFO("tlv320aic33", 0x18),
},
{
I2C_BOARD_INFO("cpld_video", 0x3b),
},
};
static struct davinci_i2c_platform_data i2c_pdata = {
.bus_freq = 100 /* kHz */,
.bus_delay = 0 /* usec */,
};
#define VCH2CLK_MASK (BIT_MASK(10) | BIT_MASK(9) | BIT_MASK(8))
#define VCH2CLK_SYSCLK8 (BIT(9))
#define VCH2CLK_AUXCLK (BIT(9) | BIT(8))
#define VCH3CLK_MASK (BIT_MASK(14) | BIT_MASK(13) | BIT_MASK(12))
#define VCH3CLK_SYSCLK8 (BIT(13))
#define VCH3CLK_AUXCLK (BIT(14) | BIT(13))
#define VIDCH2CLK (BIT(10))
#define VIDCH3CLK (BIT(11))
#define VIDCH1CLK (BIT(4))
#define TVP7002_INPUT (BIT(4))
#define TVP5147_INPUT (~BIT(4))
#define VPIF_INPUT_ONE_CHANNEL (BIT(5))
#define VPIF_INPUT_TWO_CHANNEL (~BIT(5))
#define TVP5147_CH0 "tvp514x-0"
#define TVP5147_CH1 "tvp514x-1"
/* spin lock for updating above registers */
static spinlock_t vpif_reg_lock;
static int set_vpif_clock(int mux_mode, int hd)
{
unsigned long flags;
unsigned int value;
int val = 0;
int err = 0;
if (!cpld_client)
return -ENXIO;
/* disable the clock */
spin_lock_irqsave(&vpif_reg_lock, flags);
value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
value |= (VIDCH3CLK | VIDCH2CLK);
__raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
spin_unlock_irqrestore(&vpif_reg_lock, flags);
val = i2c_smbus_read_byte(cpld_client);
if (val < 0)
return val;
if (mux_mode == 1)
val &= ~0x40;
else
val |= 0x40;
err = i2c_smbus_write_byte(cpld_client, val);
if (err)
return err;
value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VIDCLKCTL));
value &= ~(VCH2CLK_MASK);
value &= ~(VCH3CLK_MASK);
if (hd >= 1)
value |= (VCH2CLK_SYSCLK8 | VCH3CLK_SYSCLK8);
else
value |= (VCH2CLK_AUXCLK | VCH3CLK_AUXCLK);
__raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VIDCLKCTL));
spin_lock_irqsave(&vpif_reg_lock, flags);
value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
/* enable the clock */
value &= ~(VIDCH3CLK | VIDCH2CLK);
__raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
spin_unlock_irqrestore(&vpif_reg_lock, flags);
return 0;
}
static struct vpif_subdev_info dm646x_vpif_subdev[] = {
{
.name = "adv7343",
.board_info = {
I2C_BOARD_INFO("adv7343", 0x2a),
},
},
{
.name = "ths7303",
.board_info = {
I2C_BOARD_INFO("ths7303", 0x2c),
},
},
};
static const struct vpif_output dm6467_ch0_outputs[] = {
{
.output = {
.index = 0,
.name = "Composite",
.type = V4L2_OUTPUT_TYPE_ANALOG,
.capabilities = V4L2_OUT_CAP_STD,
.std = V4L2_STD_ALL,
},
.subdev_name = "adv7343",
.output_route = ADV7343_COMPOSITE_ID,
},
{
.output = {
.index = 1,
.name = "Component",
.type = V4L2_OUTPUT_TYPE_ANALOG,
.capabilities = V4L2_OUT_CAP_DV_TIMINGS,
},
.subdev_name = "adv7343",
.output_route = ADV7343_COMPONENT_ID,
},
{
.output = {
.index = 2,
.name = "S-Video",
.type = V4L2_OUTPUT_TYPE_ANALOG,
.capabilities = V4L2_OUT_CAP_STD,
.std = V4L2_STD_ALL,
},
.subdev_name = "adv7343",
.output_route = ADV7343_SVIDEO_ID,
},
};
static struct vpif_display_config dm646x_vpif_display_config = {
.set_clock = set_vpif_clock,
.subdevinfo = dm646x_vpif_subdev,
.subdev_count = ARRAY_SIZE(dm646x_vpif_subdev),
.i2c_adapter_id = 1,
.chan_config[0] = {
.outputs = dm6467_ch0_outputs,
.output_count = ARRAY_SIZE(dm6467_ch0_outputs),
},
.card_name = "DM646x EVM Video Display",
};
/**
* setup_vpif_input_path()
* @channel: channel id (0 - CH0, 1 - CH1)
* @sub_dev_name: ptr sub device name
*
* This will set vpif input to capture data from tvp514x or
* tvp7002.
*/
static int setup_vpif_input_path(int channel, const char *sub_dev_name)
{
int err = 0;
int val;
/* for channel 1, we don't do anything */
if (channel != 0)
return 0;
if (!cpld_client)
return -ENXIO;
val = i2c_smbus_read_byte(cpld_client);
if (val < 0)
return val;
if (!strcmp(sub_dev_name, TVP5147_CH0) ||
!strcmp(sub_dev_name, TVP5147_CH1))
val &= TVP5147_INPUT;
else
val |= TVP7002_INPUT;
err = i2c_smbus_write_byte(cpld_client, val);
if (err)
return err;
return 0;
}
/**
* setup_vpif_input_channel_mode()
* @mux_mode: mux mode. 0 - 1 channel or (1) - 2 channel
*
* This will setup input mode to one channel (TVP7002) or 2 channel (TVP5147)
*/
static int setup_vpif_input_channel_mode(int mux_mode)
{
unsigned long flags;
int err = 0;
int val;
u32 value;
if (!cpld_client)
return -ENXIO;
val = i2c_smbus_read_byte(cpld_client);
if (val < 0)
return val;
spin_lock_irqsave(&vpif_reg_lock, flags);
value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VIDCLKCTL));
if (mux_mode) {
val &= VPIF_INPUT_TWO_CHANNEL;
value |= VIDCH1CLK;
} else {
val |= VPIF_INPUT_ONE_CHANNEL;
value &= ~VIDCH1CLK;
}
__raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VIDCLKCTL));
spin_unlock_irqrestore(&vpif_reg_lock, flags);
err = i2c_smbus_write_byte(cpld_client, val);
if (err)
return err;
return 0;
}
static struct tvp514x_platform_data tvp5146_pdata = {
.clk_polarity = 0,
.hs_polarity = 1,
.vs_polarity = 1
};
#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
static struct vpif_subdev_info vpif_capture_sdev_info[] = {
{
.name = TVP5147_CH0,
.board_info = {
I2C_BOARD_INFO("tvp5146", 0x5d),
.platform_data = &tvp5146_pdata,
},
},
{
.name = TVP5147_CH1,
.board_info = {
I2C_BOARD_INFO("tvp5146", 0x5c),
.platform_data = &tvp5146_pdata,
},
},
};
static struct vpif_input dm6467_ch0_inputs[] = {
{
.input = {
.index = 0,
.name = "Composite",
.type = V4L2_INPUT_TYPE_CAMERA,
.capabilities = V4L2_IN_CAP_STD,
.std = TVP514X_STD_ALL,
},
.subdev_name = TVP5147_CH0,
.input_route = INPUT_CVBS_VI2B,
.output_route = OUTPUT_10BIT_422_EMBEDDED_SYNC,
},
};
static struct vpif_input dm6467_ch1_inputs[] = {
{
.input = {
.index = 0,
.name = "S-Video",
.type = V4L2_INPUT_TYPE_CAMERA,
.capabilities = V4L2_IN_CAP_STD,
.std = TVP514X_STD_ALL,
},
.subdev_name = TVP5147_CH1,
.input_route = INPUT_SVIDEO_VI2C_VI1C,
.output_route = OUTPUT_10BIT_422_EMBEDDED_SYNC,
},
};
static struct vpif_capture_config dm646x_vpif_capture_cfg = {
.setup_input_path = setup_vpif_input_path,
.setup_input_channel_mode = setup_vpif_input_channel_mode,
.subdev_info = vpif_capture_sdev_info,
.subdev_count = ARRAY_SIZE(vpif_capture_sdev_info),
.i2c_adapter_id = 1,
.chan_config[0] = {
.inputs = dm6467_ch0_inputs,
.input_count = ARRAY_SIZE(dm6467_ch0_inputs),
.vpif_if = {
.if_type = VPIF_IF_BT656,
.hd_pol = 1,
.vd_pol = 1,
.fid_pol = 0,
},
},
.chan_config[1] = {
.inputs = dm6467_ch1_inputs,
.input_count = ARRAY_SIZE(dm6467_ch1_inputs),
.vpif_if = {
.if_type = VPIF_IF_BT656,
.hd_pol = 1,
.vd_pol = 1,
.fid_pol = 0,
},
},
.card_name = "DM646x EVM Video Capture",
};
static void __init evm_init_video(void)
{
spin_lock_init(&vpif_reg_lock);
dm646x_setup_vpif(&dm646x_vpif_display_config,
&dm646x_vpif_capture_cfg);
}
static void __init evm_init_i2c(void)
{
davinci_init_i2c(&i2c_pdata);
i2c_add_driver(&dm6467evm_cpld_driver);
i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
evm_init_cpld();
evm_init_video();
}
#endif
#define DM646X_REF_FREQ 27000000
#define DM646X_AUX_FREQ 24000000
#define DM6467T_EVM_REF_FREQ 33000000
static void __init davinci_map_io(void)
{
dm646x_init();
}
static void __init dm646x_evm_init_time(void)
{
dm646x_init_time(DM646X_REF_FREQ, DM646X_AUX_FREQ);
}
static void __init dm6467t_evm_init_time(void)
{
dm646x_init_time(DM6467T_EVM_REF_FREQ, DM646X_AUX_FREQ);
}
#define DM646X_EVM_PHY_ID "davinci_mdio-0:01"
/*
* The following EDMA channels/slots are not being used by drivers (for
* example: Timer, GPIO, UART events etc) on dm646x, hence they are being
* reserved for codecs on the DSP side.
*/
static const s16 dm646x_dma_rsv_chans[][2] = {
/* (offset, number) */
{ 0, 4},
{13, 3},
{24, 4},
{30, 2},
{54, 3},
{-1, -1}
};
static const s16 dm646x_dma_rsv_slots[][2] = {
/* (offset, number) */
{ 0, 4},
{13, 3},
{24, 4},
{30, 2},
{54, 3},
{128, 384},
{-1, -1}
};
static struct edma_rsv_info dm646x_edma_rsv[] = {
{
.rsv_chans = dm646x_dma_rsv_chans,
.rsv_slots = dm646x_dma_rsv_slots,
},
};
static __init void evm_init(void)
{
int ret;
struct davinci_soc_info *soc_info = &davinci_soc_info;
dm646x_register_clocks();
ret = dm646x_gpio_register();
if (ret)
pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
#ifdef CONFIG_I2C
nvmem_add_cell_table(&dm646x_evm_nvmem_cell_table);
nvmem_add_cell_lookups(&dm646x_evm_nvmem_cell_lookup, 1);
evm_init_i2c();
#endif
davinci_serial_init(dm646x_serial_device);
dm646x_init_mcasp0(&dm646x_evm_snd_data[0]);
dm646x_init_mcasp1(&dm646x_evm_snd_data[1]);
if (machine_is_davinci_dm6467tevm())
davinci_nand_data.timing = &dm6467tevm_nandflash_timing;
if (platform_device_register(&davinci_aemif_device))
pr_warn("%s: Cannot register AEMIF device.\n", __func__);
dm646x_init_edma(dm646x_edma_rsv);
if (HAS_ATA)
davinci_init_ide();
soc_info->emac_pdata->phy_id = DM646X_EVM_PHY_ID;
}
MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
.atag_offset = 0x100,
.map_io = davinci_map_io,
.init_irq = dm646x_init_irq,
.init_time = dm646x_evm_init_time,
.init_machine = evm_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
MACHINE_END
MACHINE_START(DAVINCI_DM6467TEVM, "DaVinci DM6467T EVM")
.atag_offset = 0x100,
.map_io = davinci_map_io,
.init_irq = dm646x_init_irq,
.init_time = dm6467t_evm_init_time,
.init_machine = evm_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
MACHINE_END
arch/arm/mach-davinci/board-neuros-osd2.c deleted 100644 → 0
View file @ 9de1f9c8
/*
* Neuros Technologies OSD2 board support
*
* Modified from original 644X-EVM board support.
* 2008 (c) Neuros Technology, LLC.
* 2009 (c) Jorge Luis Zapata Muga <jorgeluis.zapata@gmail.com>
* 2009 (c) Andrey A. Porodko <Andrey.Porodko@gmail.com>
*
* The Neuros OSD 2.0 is the hardware component of the Neuros Open
* Internet Television Platform. Hardware is very close to TI
* DM644X-EVM board. It has:
* DM6446M02 module with 256MB NAND, 256MB RAM, TLV320AIC32 AIC,
* USB, Ethernet, SD/MMC, UART, THS8200, TVP7000 for video.
* Additionally realtime clock, IR remote control receiver,
* IR Blaster based on MSP430 (firmware although is different
* from used in DM644X-EVM), internal ATA-6 3.5” HDD drive
* with PATA interface, two muxed red-green leds.
*
* For more information please refer to
* http://wiki.neurostechnology.com/index.php/OSD_2.0_HD
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/leds.h>
#include <linux/mtd/partitions.h>
#include <linux/platform_data/gpio-davinci.h>
#include <linux/platform_data/i2c-davinci.h>
#include <linux/platform_data/mmc-davinci.h>
#include <linux/platform_data/mtd-davinci.h>
#include <linux/platform_data/usb-davinci.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include "common.h"
#include "serial.h"
#include "mux.h"
#include "davinci.h"
#define NEUROS_OSD2_PHY_ID "davinci_mdio-0:01"
#define LXT971_PHY_ID 0x001378e2
#define LXT971_PHY_MASK 0xfffffff0
#define NTOSD2_AUDIOSOC_I2C_ADDR 0x18
#define NTOSD2_MSP430_I2C_ADDR 0x59
#define NTOSD2_MSP430_IRQ 2
/* Neuros OSD2 has a Samsung 256 MByte NAND flash (Dev ID of 0xAA,
* 2048 blocks in the device, 64 pages per block, 2048 bytes per
* page.
*/
#define NAND_BLOCK_SIZE SZ_128K
static struct mtd_partition davinci_ntosd2_nandflash_partition[] = {
{
/* UBL (a few copies) plus U-Boot */
.name = "bootloader",
.offset = 0,
.size = 15 * NAND_BLOCK_SIZE,
.mask_flags = MTD_WRITEABLE, /* force read-only */
}, {
/* U-Boot environment */
.name = "params",
.offset = MTDPART_OFS_APPEND,
.size = 1 * NAND_BLOCK_SIZE,
.mask_flags = 0,
}, {
/* Kernel */
.name = "kernel",
.offset = MTDPART_OFS_APPEND,
.size = SZ_4M,
.mask_flags = 0,
}, {
/* File System */
.name = "filesystem",
.offset = MTDPART_OFS_APPEND,
.size = MTDPART_SIZ_FULL,
.mask_flags = 0,
}
/* A few blocks at end hold a flash Bad Block Table. */
};
static struct davinci_nand_pdata davinci_ntosd2_nandflash_data = {
.core_chipsel = 0,
.parts = davinci_ntosd2_nandflash_partition,
.nr_parts = ARRAY_SIZE(davinci_ntosd2_nandflash_partition),
.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
.ecc_bits = 1,
.bbt_options = NAND_BBT_USE_FLASH,
};
static struct resource davinci_ntosd2_nandflash_resource[] = {
{
.start = DM644X_ASYNC_EMIF_DATA_CE0_BASE,
.end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
.flags = IORESOURCE_MEM,
}, {
.start = DM644X_ASYNC_EMIF_CONTROL_BASE,
.end = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device davinci_ntosd2_nandflash_device = {
.name = "davinci_nand",
.id = 0,
.dev = {
.platform_data = &davinci_ntosd2_nandflash_data,
},
.num_resources = ARRAY_SIZE(davinci_ntosd2_nandflash_resource),
.resource = davinci_ntosd2_nandflash_resource,
};
static u64 davinci_fb_dma_mask = DMA_BIT_MASK(32);
static struct platform_device davinci_fb_device = {
.name = "davincifb",
.id = -1,
.dev = {
.dma_mask = &davinci_fb_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.num_resources = 0,
};
static const struct gpio_led ntosd2_leds[] = {
{ .name = "led1_green", .gpio = 10, },
{ .name = "led1_red", .gpio = 11, },
{ .name = "led2_green", .gpio = 12, },
{ .name = "led2_red", .gpio = 13, },
};
static struct gpio_led_platform_data ntosd2_leds_data = {
.num_leds = ARRAY_SIZE(ntosd2_leds),
.leds = ntosd2_leds,
};
static struct platform_device ntosd2_leds_dev = {
.name = "leds-gpio",
.id = -1,
.dev = {
.platform_data = &ntosd2_leds_data,
},
};
static struct platform_device *davinci_ntosd2_devices[] __initdata = {
&davinci_fb_device,
&ntosd2_leds_dev,
};
static void __init davinci_ntosd2_map_io(void)
{
dm644x_init();
}
static struct davinci_mmc_config davinci_ntosd2_mmc_config = {
.wires = 4,
};
#define HAS_ATA (IS_ENABLED(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
IS_ENABLED(CONFIG_PATA_BK3710))
#define HAS_NAND IS_ENABLED(CONFIG_MTD_NAND_DAVINCI)
static __init void davinci_ntosd2_init(void)
{
int ret;
struct clk *aemif_clk;
struct davinci_soc_info *soc_info = &davinci_soc_info;
dm644x_register_clocks();
dm644x_init_devices();
ret = dm644x_gpio_register();
if (ret)
pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
aemif_clk = clk_get(NULL, "aemif");
clk_prepare_enable(aemif_clk);
if (HAS_ATA) {
if (HAS_NAND)
pr_warn("WARNING: both IDE and Flash are enabled, but they share AEMIF pins\n"
"\tDisable IDE for NAND/NOR support\n");
davinci_init_ide();
} else if (HAS_NAND) {
davinci_cfg_reg(DM644X_HPIEN_DISABLE);
davinci_cfg_reg(DM644X_ATAEN_DISABLE);
/* only one device will be jumpered and detected */
if (HAS_NAND)
platform_device_register(
&davinci_ntosd2_nandflash_device);
}
platform_add_devices(davinci_ntosd2_devices,
ARRAY_SIZE(davinci_ntosd2_devices));
davinci_serial_init(dm644x_serial_device);
dm644x_init_asp();
soc_info->emac_pdata->phy_id = NEUROS_OSD2_PHY_ID;
davinci_setup_usb(1000, 8);
/*
* Mux the pins to be GPIOs, VLYNQEN is already done at startup.
* The AEAWx are five new AEAW pins that can be muxed by separately.
* They are a bitmask for GPIO management. According TI
* documentation (https://www.ti.com/lit/gpn/tms320dm6446) to employ
* gpio(10,11,12,13) for leds any combination of bits works except
* four last. So we are to reset all five.
*/
davinci_cfg_reg(DM644X_AEAW0);
davinci_cfg_reg(DM644X_AEAW1);
davinci_cfg_reg(DM644X_AEAW2);
davinci_cfg_reg(DM644X_AEAW3);
davinci_cfg_reg(DM644X_AEAW4);
davinci_setup_mmc(0, &davinci_ntosd2_mmc_config);
}
MACHINE_START(NEUROS_OSD2, "Neuros OSD2")
/* Maintainer: Neuros Technologies <neuros@groups.google.com> */
.atag_offset = 0x100,
.map_io = davinci_ntosd2_map_io,
.init_irq = dm644x_init_irq,
.init_time = dm644x_init_time,
.init_machine = davinci_ntosd2_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
MACHINE_END
arch/arm/mach-davinci/board-sffsdr.c deleted 100644 → 0
View file @ 9de1f9c8
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Lyrtech SFFSDR board support.
*
* Copyright (C) 2008 Philip Balister, OpenSDR <philip@opensdr.com>
* Copyright (C) 2008 Lyrtech <www.lyrtech.com>
*
* Based on DV-EVM platform, original copyright follows:
*
* Copyright (C) 2007 MontaVista Software, Inc.
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>
#include <linux/property.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/rawnand.h>
#include <linux/mtd/partitions.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <linux/platform_data/i2c-davinci.h>
#include <linux/platform_data/usb-davinci.h>
#include "common.h"
#include "serial.h"
#include "mux.h"
#include "davinci.h"
#define SFFSDR_PHY_ID "davinci_mdio-0:01"
static struct mtd_partition davinci_sffsdr_nandflash_partition[] = {
/* U-Boot Environment: Block 0
* UBL: Block 1
* U-Boot: Blocks 6-7 (256 kb)
* Integrity Kernel: Blocks 8-31 (3 Mb)
* Integrity Data: Blocks 100-END
*/
{
.name = "Linux Kernel",
.offset = 32 * SZ_128K,
.size = 16 * SZ_128K, /* 2 Mb */
.mask_flags = MTD_WRITEABLE, /* Force read-only */
},
{
.name = "Linux ROOT",
.offset = MTDPART_OFS_APPEND,
.size = 256 * SZ_128K, /* 32 Mb */
.mask_flags = 0, /* R/W */
},
};
static struct flash_platform_data davinci_sffsdr_nandflash_data = {
.parts = davinci_sffsdr_nandflash_partition,
.nr_parts = ARRAY_SIZE(davinci_sffsdr_nandflash_partition),
};
static struct resource davinci_sffsdr_nandflash_resource[] = {
{
.start = DM644X_ASYNC_EMIF_DATA_CE0_BASE,
.end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
.flags = IORESOURCE_MEM,
}, {
.start = DM644X_ASYNC_EMIF_CONTROL_BASE,
.end = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device davinci_sffsdr_nandflash_device = {
.name = "davinci_nand", /* Name of driver */
.id = 0,
.dev = {
.platform_data = &davinci_sffsdr_nandflash_data,
},
.num_resources = ARRAY_SIZE(davinci_sffsdr_nandflash_resource),
.resource = davinci_sffsdr_nandflash_resource,
};
static const struct property_entry eeprom_properties[] = {
PROPERTY_ENTRY_U32("pagesize", 32),
{ }
};
static const struct software_node eeprom_node = {
.properties = eeprom_properties,
};
static struct i2c_board_info __initdata i2c_info[] = {
{
I2C_BOARD_INFO("24c64", 0x50),
.swnode = &eeprom_node,
},
/* Other I2C devices:
* MSP430, addr 0x23 (not used)
* PCA9543, addr 0x70 (setup done by U-Boot)
* ADS7828, addr 0x48 (ADC for voltage monitoring.)
*/
};
static struct davinci_i2c_platform_data i2c_pdata = {
.bus_freq = 20 /* kHz */,
.bus_delay = 100 /* usec */,
};
static void __init sffsdr_init_i2c(void)
{
davinci_init_i2c(&i2c_pdata);
i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
}
static struct platform_device *davinci_sffsdr_devices[] __initdata = {
&davinci_sffsdr_nandflash_device,
};
static void __init davinci_sffsdr_map_io(void)
{
dm644x_init();
}
static __init void davinci_sffsdr_init(void)
{
struct davinci_soc_info *soc_info = &davinci_soc_info;
dm644x_register_clocks();
dm644x_init_devices();
platform_add_devices(davinci_sffsdr_devices,
ARRAY_SIZE(davinci_sffsdr_devices));
sffsdr_init_i2c();
davinci_serial_init(dm644x_serial_device);
soc_info->emac_pdata->phy_id = SFFSDR_PHY_ID;
davinci_setup_usb(0, 0); /* We support only peripheral mode. */
/* mux VLYNQ pins */
davinci_cfg_reg(DM644X_VLYNQEN);
davinci_cfg_reg(DM644X_VLYNQWD);
}
MACHINE_START(SFFSDR, "Lyrtech SFFSDR")
.atag_offset = 0x100,
.map_io = davinci_sffsdr_map_io,
.init_irq = dm644x_init_irq,
.init_time = dm644x_init_time,
.init_machine = davinci_sffsdr_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
MACHINE_END
arch/arm/mach-davinci/dm644x.c deleted 100644 → 0
View file @ 9de1f9c8
/*
* TI DaVinci DM644x chip specific setup
*
* Author: Kevin Hilman, Deep Root Systems, LLC
*
* 2007 (c) Deep Root Systems, LLC. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#include <linux/clk-provider.h>
#include <linux/clk/davinci.h>
#include <linux/clkdev.h>
#include <linux/dmaengine.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irqchip/irq-davinci-aintc.h>
#include <linux/platform_data/edma.h>
#include <linux/platform_data/gpio-davinci.h>
#include <linux/platform_device.h>
#include <linux/serial_8250.h>
#include <clocksource/timer-davinci.h>
#include <asm/mach/map.h>
#include "common.h"
#include "cputype.h"
#include "serial.h"
#include "asp.h"
#include "davinci.h"
#include "irqs.h"
#include "mux.h"
/*
* Device specific clocks
*/
#define DM644X_REF_FREQ 27000000
#define DM644X_EMAC_BASE 0x01c80000
#define DM644X_EMAC_MDIO_BASE (DM644X_EMAC_BASE + 0x4000)
#define DM644X_EMAC_CNTRL_OFFSET 0x0000
#define DM644X_EMAC_CNTRL_MOD_OFFSET 0x1000
#define DM644X_EMAC_CNTRL_RAM_OFFSET 0x2000
#define DM644X_EMAC_CNTRL_RAM_SIZE 0x2000
static struct emac_platform_data dm644x_emac_pdata = {
.ctrl_reg_offset = DM644X_EMAC_CNTRL_OFFSET,
.ctrl_mod_reg_offset = DM644X_EMAC_CNTRL_MOD_OFFSET,
.ctrl_ram_offset = DM644X_EMAC_CNTRL_RAM_OFFSET,
.ctrl_ram_size = DM644X_EMAC_CNTRL_RAM_SIZE,
.version = EMAC_VERSION_1,
};
static struct resource dm644x_emac_resources[] = {
{
.start = DM644X_EMAC_BASE,
.end = DM644X_EMAC_BASE + SZ_16K - 1,
.flags = IORESOURCE_MEM,
},
{
.start = DAVINCI_INTC_IRQ(IRQ_EMACINT),
.end = DAVINCI_INTC_IRQ(IRQ_EMACINT),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device dm644x_emac_device = {
.name = "davinci_emac",
.id = 1,
.dev = {
.platform_data = &dm644x_emac_pdata,
},
.num_resources = ARRAY_SIZE(dm644x_emac_resources),
.resource = dm644x_emac_resources,
};
static struct resource dm644x_mdio_resources[] = {
{
.start = DM644X_EMAC_MDIO_BASE,
.end = DM644X_EMAC_MDIO_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device dm644x_mdio_device = {
.name = "davinci_mdio",
.id = 0,
.num_resources = ARRAY_SIZE(dm644x_mdio_resources),
.resource = dm644x_mdio_resources,
};
/*
* Device specific mux setup
*
* soc description mux mode mode mux dbg
* reg offset mask mode
*/
static const struct mux_config dm644x_pins[] = {
#ifdef CONFIG_DAVINCI_MUX
MUX_CFG(DM644X, HDIREN, 0, 16, 1, 1, true)
MUX_CFG(DM644X, ATAEN, 0, 17, 1, 1, true)
MUX_CFG(DM644X, ATAEN_DISABLE, 0, 17, 1, 0, true)
MUX_CFG(DM644X, HPIEN_DISABLE, 0, 29, 1, 0, true)
MUX_CFG(DM644X, AEAW, 0, 0, 31, 31, true)
MUX_CFG(DM644X, AEAW0, 0, 0, 1, 0, true)
MUX_CFG(DM644X, AEAW1, 0, 1, 1, 0, true)
MUX_CFG(DM644X, AEAW2, 0, 2, 1, 0, true)
MUX_CFG(DM644X, AEAW3, 0, 3, 1, 0, true)
MUX_CFG(DM644X, AEAW4, 0, 4, 1, 0, true)
MUX_CFG(DM644X, MSTK, 1, 9, 1, 0, false)
MUX_CFG(DM644X, I2C, 1, 7, 1, 1, false)
MUX_CFG(DM644X, MCBSP, 1, 10, 1, 1, false)
MUX_CFG(DM644X, UART1, 1, 1, 1, 1, true)
MUX_CFG(DM644X, UART2, 1, 2, 1, 1, true)
MUX_CFG(DM644X, PWM0, 1, 4, 1, 1, false)
MUX_CFG(DM644X, PWM1, 1, 5, 1, 1, false)
MUX_CFG(DM644X, PWM2, 1, 6, 1, 1, false)
MUX_CFG(DM644X, VLYNQEN, 0, 15, 1, 1, false)
MUX_CFG(DM644X, VLSCREN, 0, 14, 1, 1, false)
MUX_CFG(DM644X, VLYNQWD, 0, 12, 3, 3, false)
MUX_CFG(DM644X, EMACEN, 0, 31, 1, 1, true)
MUX_CFG(DM644X, GPIO3V, 0, 31, 1, 0, true)
MUX_CFG(DM644X, GPIO0, 0, 24, 1, 0, true)
MUX_CFG(DM644X, GPIO3, 0, 25, 1, 0, false)
MUX_CFG(DM644X, GPIO43_44, 1, 7, 1, 0, false)
MUX_CFG(DM644X, GPIO46_47, 0, 22, 1, 0, true)
MUX_CFG(DM644X, RGB666, 0, 22, 1, 1, true)
MUX_CFG(DM644X, LOEEN, 0, 24, 1, 1, true)
MUX_CFG(DM644X, LFLDEN, 0, 25, 1, 1, false)
#endif
};
/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
[IRQ_VDINT0] = 2,
[IRQ_VDINT1] = 6,
[IRQ_VDINT2] = 6,
[IRQ_HISTINT] = 6,
[IRQ_H3AINT] = 6,
[IRQ_PRVUINT] = 6,
[IRQ_RSZINT] = 6,
[7] = 7,
[IRQ_VENCINT] = 6,
[IRQ_ASQINT] = 6,
[IRQ_IMXINT] = 6,
[IRQ_VLCDINT] = 6,
[IRQ_USBINT] = 4,
[IRQ_EMACINT] = 4,
[14] = 7,
[15] = 7,
[IRQ_CCINT0] = 5, /* dma */
[IRQ_CCERRINT] = 5, /* dma */
[IRQ_TCERRINT0] = 5, /* dma */
[IRQ_TCERRINT] = 5, /* dma */
[IRQ_PSCIN] = 7,
[21] = 7,
[IRQ_IDE] = 4,
[23] = 7,
[IRQ_MBXINT] = 7,
[IRQ_MBRINT] = 7,
[IRQ_MMCINT] = 7,
[IRQ_SDIOINT] = 7,
[28] = 7,
[IRQ_DDRINT] = 7,
[IRQ_AEMIFINT] = 7,
[IRQ_VLQINT] = 4,
[IRQ_TINT0_TINT12] = 2, /* clockevent */
[IRQ_TINT0_TINT34] = 2, /* clocksource */
[IRQ_TINT1_TINT12] = 7, /* DSP timer */
[IRQ_TINT1_TINT34] = 7, /* system tick */
[IRQ_PWMINT0] = 7,
[IRQ_PWMINT1] = 7,
[IRQ_PWMINT2] = 7,
[IRQ_I2C] = 3,
[IRQ_UARTINT0] = 3,
[IRQ_UARTINT1] = 3,
[IRQ_UARTINT2] = 3,
[IRQ_SPINT0] = 3,
[IRQ_SPINT1] = 3,
[45] = 7,
[IRQ_DSP2ARM0] = 4,
[IRQ_DSP2ARM1] = 4,
[IRQ_GPIO0] = 7,
[IRQ_GPIO1] = 7,
[IRQ_GPIO2] = 7,
[IRQ_GPIO3] = 7,
[IRQ_GPIO4] = 7,
[IRQ_GPIO5] = 7,
[IRQ_GPIO6] = 7,
[IRQ_GPIO7] = 7,
[IRQ_GPIOBNK0] = 7,
[IRQ_GPIOBNK1] = 7,
[IRQ_GPIOBNK2] = 7,
[IRQ_GPIOBNK3] = 7,
[IRQ_GPIOBNK4] = 7,
[IRQ_COMMTX] = 7,
[IRQ_COMMRX] = 7,
[IRQ_EMUINT] = 7,
};
/*----------------------------------------------------------------------*/
static s8 queue_priority_mapping[][2] = {
/* {event queue no, Priority} */
{0, 3},
{1, 7},
{-1, -1},
};
static const struct dma_slave_map dm644x_edma_map[] = {
{ "davinci-mcbsp", "tx", EDMA_FILTER_PARAM(0, 2) },
{ "davinci-mcbsp", "rx", EDMA_FILTER_PARAM(0, 3) },
{ "spi_davinci", "tx", EDMA_FILTER_PARAM(0, 16) },
{ "spi_davinci", "rx", EDMA_FILTER_PARAM(0, 17) },
{ "dm6441-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) },
{ "dm6441-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) },
};
static struct edma_soc_info dm644x_edma_pdata = {
.queue_priority_mapping = queue_priority_mapping,
.default_queue = EVENTQ_1,
.slave_map = dm644x_edma_map,
.slavecnt = ARRAY_SIZE(dm644x_edma_map),
};
static struct resource edma_resources[] = {
{
.name = "edma3_cc",
.start = 0x01c00000,
.end = 0x01c00000 + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
{
.name = "edma3_tc0",
.start = 0x01c10000,
.end = 0x01c10000 + SZ_1K - 1,
.flags = IORESOURCE_MEM,
},
{
.name = "edma3_tc1",
.start = 0x01c10400,
.end = 0x01c10400 + SZ_1K - 1,
.flags = IORESOURCE_MEM,
},
{
.name = "edma3_ccint",
.start = DAVINCI_INTC_IRQ(IRQ_CCINT0),
.flags = IORESOURCE_IRQ,
},
{
.name = "edma3_ccerrint",
.start = DAVINCI_INTC_IRQ(IRQ_CCERRINT),
.flags = IORESOURCE_IRQ,
},
/* not using TC*_ERR */
};
static const struct platform_device_info dm644x_edma_device __initconst = {
.name = "edma",
.id = 0,
.dma_mask = DMA_BIT_MASK(32),
.res = edma_resources,
.num_res = ARRAY_SIZE(edma_resources),
.data = &dm644x_edma_pdata,
.size_data = sizeof(dm644x_edma_pdata),
};
/* DM6446 EVM uses ASP0; line-out is a pair of RCA jacks */
static struct resource dm644x_asp_resources[] = {
{
.name = "mpu",
.start = DAVINCI_ASP0_BASE,
.end = DAVINCI_ASP0_BASE + SZ_8K - 1,
.flags = IORESOURCE_MEM,
},
{
.start = DAVINCI_DMA_ASP0_TX,
.end = DAVINCI_DMA_ASP0_TX,
.flags = IORESOURCE_DMA,
},
{
.start = DAVINCI_DMA_ASP0_RX,
.end = DAVINCI_DMA_ASP0_RX,
.flags = IORESOURCE_DMA,
},
};
static struct platform_device dm644x_asp_device = {
.name = "davinci-mcbsp",
.id = -1,
.num_resources = ARRAY_SIZE(dm644x_asp_resources),
.resource = dm644x_asp_resources,
};
#define DM644X_VPSS_BASE 0x01c73400
static struct resource dm644x_vpss_resources[] = {
{
/* VPSS Base address */
.name = "vpss",
.start = DM644X_VPSS_BASE,
.end = DM644X_VPSS_BASE + 0xff,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device dm644x_vpss_device = {
.name = "vpss",
.id = -1,
.dev.platform_data = "dm644x_vpss",
.num_resources = ARRAY_SIZE(dm644x_vpss_resources),
.resource = dm644x_vpss_resources,
};
static struct resource dm644x_vpfe_resources[] = {
{
.start = DAVINCI_INTC_IRQ(IRQ_VDINT0),
.end = DAVINCI_INTC_IRQ(IRQ_VDINT0),
.flags = IORESOURCE_IRQ,
},
{
.start = DAVINCI_INTC_IRQ(IRQ_VDINT1),
.end = DAVINCI_INTC_IRQ(IRQ_VDINT1),
.flags = IORESOURCE_IRQ,
},
};
static u64 dm644x_video_dma_mask = DMA_BIT_MASK(32);
static struct resource dm644x_ccdc_resource[] = {
/* CCDC Base address */
{
.start = 0x01c70400,
.end = 0x01c70400 + 0xff,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device dm644x_ccdc_dev = {
.name = "dm644x_ccdc",
.id = -1,
.num_resources = ARRAY_SIZE(dm644x_ccdc_resource),
.resource = dm644x_ccdc_resource,
.dev = {
.dma_mask = &dm644x_video_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
static struct platform_device dm644x_vpfe_dev = {
.name = CAPTURE_DRV_NAME,
.id = -1,
.num_resources = ARRAY_SIZE(dm644x_vpfe_resources),
.resource = dm644x_vpfe_resources,
.dev = {
.dma_mask = &dm644x_video_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
#define DM644X_OSD_BASE 0x01c72600
static struct resource dm644x_osd_resources[] = {
{
.start = DM644X_OSD_BASE,
.end = DM644X_OSD_BASE + 0x1ff,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device dm644x_osd_dev = {
.name = DM644X_VPBE_OSD_SUBDEV_NAME,
.id = -1,
.num_resources = ARRAY_SIZE(dm644x_osd_resources),
.resource = dm644x_osd_resources,
.dev = {
.dma_mask = &dm644x_video_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
#define DM644X_VENC_BASE 0x01c72400
static struct resource dm644x_venc_resources[] = {
{
.start = DM644X_VENC_BASE,
.end = DM644X_VENC_BASE + 0x17f,
.flags = IORESOURCE_MEM,
},
};
#define DM644X_VPSS_MUXSEL_PLL2_MODE BIT(0)
#define DM644X_VPSS_MUXSEL_VPBECLK_MODE BIT(1)
#define DM644X_VPSS_VENCLKEN BIT(3)
#define DM644X_VPSS_DACCLKEN BIT(4)
static int dm644x_venc_setup_clock(enum vpbe_enc_timings_type type,
unsigned int pclock)
{
int ret = 0;
u32 v = DM644X_VPSS_VENCLKEN;
switch (type) {
case VPBE_ENC_STD:
v |= DM644X_VPSS_DACCLKEN;
writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
break;
case VPBE_ENC_DV_TIMINGS:
if (pclock <= 27000000) {
v |= DM644X_VPSS_DACCLKEN;
writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
} else {
/*
* For HD, use external clock source since
* HD requires higher clock rate
*/
v |= DM644X_VPSS_MUXSEL_VPBECLK_MODE;
writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
}
break;
default:
ret = -EINVAL;
}
return ret;
}
static struct resource dm644x_v4l2_disp_resources[] = {
{
.start = DAVINCI_INTC_IRQ(IRQ_VENCINT),
.end = DAVINCI_INTC_IRQ(IRQ_VENCINT),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device dm644x_vpbe_display = {
.name = "vpbe-v4l2",
.id = -1,
.num_resources = ARRAY_SIZE(dm644x_v4l2_disp_resources),
.resource = dm644x_v4l2_disp_resources,
.dev = {
.dma_mask = &dm644x_video_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
static struct venc_platform_data dm644x_venc_pdata = {
.setup_clock = dm644x_venc_setup_clock,
};
static struct platform_device dm644x_venc_dev = {
.name = DM644X_VPBE_VENC_SUBDEV_NAME,
.id = -1,
.num_resources = ARRAY_SIZE(dm644x_venc_resources),
.resource = dm644x_venc_resources,
.dev = {
.dma_mask = &dm644x_video_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &dm644x_venc_pdata,
},
};
static struct platform_device dm644x_vpbe_dev = {
.name = "vpbe_controller",
.id = -1,
.dev = {
.dma_mask = &dm644x_video_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
static struct resource dm644_gpio_resources[] = {
{ /* registers */
.start = DAVINCI_GPIO_BASE,
.end = DAVINCI_GPIO_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
{ /* interrupt */
.start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK0),
.end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK0),
.flags = IORESOURCE_IRQ,
},
{
.start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK1),
.end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK1),
.flags = IORESOURCE_IRQ,
},
{
.start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK2),
.end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK2),
.flags = IORESOURCE_IRQ,
},
{
.start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK3),
.end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK3),
.flags = IORESOURCE_IRQ,
},
{
.start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK4),
.end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK4),
.flags = IORESOURCE_IRQ,
},
};
static struct davinci_gpio_platform_data dm644_gpio_platform_data = {
.no_auto_base = true,
.base = 0,
.ngpio = 71,
};
int __init dm644x_gpio_register(void)
{
return davinci_gpio_register(dm644_gpio_resources,
ARRAY_SIZE(dm644_gpio_resources),
&dm644_gpio_platform_data);
}
/*----------------------------------------------------------------------*/
static struct map_desc dm644x_io_desc[] = {
{
.virtual = IO_VIRT,
.pfn = __phys_to_pfn(IO_PHYS),
.length = IO_SIZE,
.type = MT_DEVICE
},
};
/* Contents of JTAG ID register used to identify exact cpu type */
static struct davinci_id dm644x_ids[] = {
{
.variant = 0x0,
.part_no = 0xb700,
.manufacturer = 0x017,
.cpu_id = DAVINCI_CPU_ID_DM6446,
.name = "dm6446",
},
{
.variant = 0x1,
.part_no = 0xb700,
.manufacturer = 0x017,
.cpu_id = DAVINCI_CPU_ID_DM6446,
.name = "dm6446a",
},
};
/*
* Bottom half of timer0 is used for clockevent, top half is used for
* clocksource.
*/
static const struct davinci_timer_cfg dm644x_timer_cfg = {
.reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_4K),
.irq = {
DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12)),
DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34)),
},
};
static struct plat_serial8250_port dm644x_serial0_platform_data[] = {
{
.mapbase = DAVINCI_UART0_BASE,
.irq = DAVINCI_INTC_IRQ(IRQ_UARTINT0),
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
UPF_IOREMAP,
.iotype = UPIO_MEM,
.regshift = 2,
},
{
.flags = 0,
}
};
static struct plat_serial8250_port dm644x_serial1_platform_data[] = {
{
.mapbase = DAVINCI_UART1_BASE,
.irq = DAVINCI_INTC_IRQ(IRQ_UARTINT1),
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
UPF_IOREMAP,
.iotype = UPIO_MEM,
.regshift = 2,
},
{
.flags = 0,
}
};
static struct plat_serial8250_port dm644x_serial2_platform_data[] = {
{
.mapbase = DAVINCI_UART2_BASE,
.irq = DAVINCI_INTC_IRQ(IRQ_UARTINT2),
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
UPF_IOREMAP,
.iotype = UPIO_MEM,
.regshift = 2,
},
{
.flags = 0,
}
};
struct platform_device dm644x_serial_device[] = {
{
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM,
.dev = {
.platform_data = dm644x_serial0_platform_data,
}
},
{
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM1,
.dev = {
.platform_data = dm644x_serial1_platform_data,
}
},
{
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM2,
.dev = {
.platform_data = dm644x_serial2_platform_data,
}
},
{
}
};
static const struct davinci_soc_info davinci_soc_info_dm644x = {
.io_desc = dm644x_io_desc,
.io_desc_num = ARRAY_SIZE(dm644x_io_desc),
.jtag_id_reg = 0x01c40028,
.ids = dm644x_ids,
.ids_num = ARRAY_SIZE(dm644x_ids),
.pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
.pinmux_pins = dm644x_pins,
.pinmux_pins_num = ARRAY_SIZE(dm644x_pins),
.emac_pdata = &dm644x_emac_pdata,
.sram_dma = 0x00008000,
.sram_len = SZ_16K,
};
void __init dm644x_init_asp(void)
{
davinci_cfg_reg(DM644X_MCBSP);
platform_device_register(&dm644x_asp_device);
}
void __init dm644x_init(void)
{
davinci_common_init(&davinci_soc_info_dm644x);
davinci_map_sysmod();
}
void __init dm644x_init_time(void)
{
void __iomem *pll1, *psc;
struct clk *clk;
int rv;
clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM644X_REF_FREQ);
pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K);
dm644x_pll1_init(NULL, pll1, NULL);
psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K);
dm644x_psc_init(NULL, psc);
clk = clk_get(NULL, "timer0");
if (WARN_ON(IS_ERR(clk))) {
pr_err("Unable to get the timer clock\n");
return;
}
rv = davinci_timer_register(clk, &dm644x_timer_cfg);
WARN(rv, "Unable to register the timer: %d\n", rv);
}
static struct resource dm644x_pll2_resources[] = {
{
.start = DAVINCI_PLL2_BASE,
.end = DAVINCI_PLL2_BASE + SZ_1K - 1,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device dm644x_pll2_device = {
.name = "dm644x-pll2",
.id = -1,
.resource = dm644x_pll2_resources,
.num_resources = ARRAY_SIZE(dm644x_pll2_resources),
};
void __init dm644x_register_clocks(void)
{
/* PLL1 and PSC are registered in dm644x_init_time() */
platform_device_register(&dm644x_pll2_device);
}
int __init dm644x_init_video(struct vpfe_config *vpfe_cfg,
struct vpbe_config *vpbe_cfg)
{
if (vpfe_cfg || vpbe_cfg)
platform_device_register(&dm644x_vpss_device);
if (vpfe_cfg) {
dm644x_vpfe_dev.dev.platform_data = vpfe_cfg;
platform_device_register(&dm644x_ccdc_dev);
platform_device_register(&dm644x_vpfe_dev);
}
if (vpbe_cfg) {
dm644x_vpbe_dev.dev.platform_data = vpbe_cfg;
platform_device_register(&dm644x_osd_dev);
platform_device_register(&dm644x_venc_dev);
platform_device_register(&dm644x_vpbe_dev);
platform_device_register(&dm644x_vpbe_display);
}
return 0;
}
static const struct davinci_aintc_config dm644x_aintc_config = {
.reg = {
.start = DAVINCI_ARM_INTC_BASE,
.end = DAVINCI_ARM_INTC_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
.num_irqs = 64,
.prios = dm644x_default_priorities,
};
void __init dm644x_init_irq(void)
{
davinci_aintc_init(&dm644x_aintc_config);
}
void __init dm644x_init_devices(void)
{
struct platform_device *edma_pdev;
int ret;
edma_pdev = platform_device_register_full(&dm644x_edma_device);
if (IS_ERR(edma_pdev))
pr_warn("%s: Failed to register eDMA\n", __func__);
platform_device_register(&dm644x_mdio_device);
platform_device_register(&dm644x_emac_device);
ret = davinci_init_wdt();
if (ret)
pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
}
arch/arm/mach-davinci/dm646x.c deleted 100644 → 0
View file @ 9de1f9c8
/*
* TI DaVinci DM646x chip specific setup
*
* Author: Kevin Hilman, Deep Root Systems, LLC
*
* 2007 (c) Deep Root Systems, LLC. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#include <linux/clk-provider.h>
#include <linux/clk/davinci.h>
#include <linux/clkdev.h>
#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irqchip/irq-davinci-aintc.h>
#include <linux/platform_data/edma.h>
#include <linux/platform_data/gpio-davinci.h>
#include <linux/platform_device.h>
#include <linux/serial_8250.h>
#include <clocksource/timer-davinci.h>
#include <asm/mach/map.h>
#include "common.h"
#include "cputype.h"
#include "serial.h"
#include "asp.h"
#include "davinci.h"
#include "irqs.h"
#include "mux.h"
#define DAVINCI_VPIF_BASE (0x01C12000)
#define VDD3P3V_VID_MASK (BIT_MASK(3) | BIT_MASK(2) | BIT_MASK(1) |\
BIT_MASK(0))
#define VSCLKDIS_MASK (BIT_MASK(11) | BIT_MASK(10) | BIT_MASK(9) |\
BIT_MASK(8))
#define DM646X_EMAC_BASE 0x01c80000
#define DM646X_EMAC_MDIO_BASE (DM646X_EMAC_BASE + 0x4000)
#define DM646X_EMAC_CNTRL_OFFSET 0x0000
#define DM646X_EMAC_CNTRL_MOD_OFFSET 0x1000
#define DM646X_EMAC_CNTRL_RAM_OFFSET 0x2000
#define DM646X_EMAC_CNTRL_RAM_SIZE 0x2000
static struct emac_platform_data dm646x_emac_pdata = {
.ctrl_reg_offset = DM646X_EMAC_CNTRL_OFFSET,
.ctrl_mod_reg_offset = DM646X_EMAC_CNTRL_MOD_OFFSET,
.ctrl_ram_offset = DM646X_EMAC_CNTRL_RAM_OFFSET,
.ctrl_ram_size = DM646X_EMAC_CNTRL_RAM_SIZE,
.version = EMAC_VERSION_2,
};
static struct resource dm646x_emac_resources[] = {
{
.start = DM646X_EMAC_BASE,
.end = DM646X_EMAC_BASE + SZ_16K - 1,
.flags = IORESOURCE_MEM,
},
{
.start = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACRXTHINT),
.end = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACRXTHINT),
.flags = IORESOURCE_IRQ,
},
{
.start = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACRXINT),
.end = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACRXINT),
.flags = IORESOURCE_IRQ,
},
{
.start = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACTXINT),
.end = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACTXINT),
.flags = IORESOURCE_IRQ,
},
{
.start = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACMISCINT),
.end = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACMISCINT),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device dm646x_emac_device = {
.name = "davinci_emac",
.id = 1,
.dev = {
.platform_data = &dm646x_emac_pdata,
},
.num_resources = ARRAY_SIZE(dm646x_emac_resources),
.resource = dm646x_emac_resources,
};
static struct resource dm646x_mdio_resources[] = {
{
.start = DM646X_EMAC_MDIO_BASE,
.end = DM646X_EMAC_MDIO_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device dm646x_mdio_device = {
.name = "davinci_mdio",
.id = 0,
.num_resources = ARRAY_SIZE(dm646x_mdio_resources),
.resource = dm646x_mdio_resources,
};
/*
* Device specific mux setup
*
* soc description mux mode mode mux dbg
* reg offset mask mode
*/
static const struct mux_config dm646x_pins[] = {
#ifdef CONFIG_DAVINCI_MUX
MUX_CFG(DM646X, ATAEN, 0, 0, 5, 1, true)
MUX_CFG(DM646X, AUDCK1, 0, 29, 1, 0, false)
MUX_CFG(DM646X, AUDCK0, 0, 28, 1, 0, false)
MUX_CFG(DM646X, CRGMUX, 0, 24, 7, 5, true)
MUX_CFG(DM646X, STSOMUX_DISABLE, 0, 22, 3, 0, true)
MUX_CFG(DM646X, STSIMUX_DISABLE, 0, 20, 3, 0, true)
MUX_CFG(DM646X, PTSOMUX_DISABLE, 0, 18, 3, 0, true)
MUX_CFG(DM646X, PTSIMUX_DISABLE, 0, 16, 3, 0, true)
MUX_CFG(DM646X, STSOMUX, 0, 22, 3, 2, true)
MUX_CFG(DM646X, STSIMUX, 0, 20, 3, 2, true)
MUX_CFG(DM646X, PTSOMUX_PARALLEL, 0, 18, 3, 2, true)
MUX_CFG(DM646X, PTSIMUX_PARALLEL, 0, 16, 3, 2, true)
MUX_CFG(DM646X, PTSOMUX_SERIAL, 0, 18, 3, 3, true)
MUX_CFG(DM646X, PTSIMUX_SERIAL, 0, 16, 3, 3, true)
#endif
};
static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
[IRQ_DM646X_VP_VERTINT0] = 7,
[IRQ_DM646X_VP_VERTINT1] = 7,
[IRQ_DM646X_VP_VERTINT2] = 7,
[IRQ_DM646X_VP_VERTINT3] = 7,
[IRQ_DM646X_VP_ERRINT] = 7,
[IRQ_DM646X_RESERVED_1] = 7,
[IRQ_DM646X_RESERVED_2] = 7,
[IRQ_DM646X_WDINT] = 7,
[IRQ_DM646X_CRGENINT0] = 7,
[IRQ_DM646X_CRGENINT1] = 7,
[IRQ_DM646X_TSIFINT0] = 7,
[IRQ_DM646X_TSIFINT1] = 7,
[IRQ_DM646X_VDCEINT] = 7,
[IRQ_DM646X_USBINT] = 7,
[IRQ_DM646X_USBDMAINT] = 7,
[IRQ_DM646X_PCIINT] = 7,
[IRQ_CCINT0] = 7, /* dma */
[IRQ_CCERRINT] = 7, /* dma */
[IRQ_TCERRINT0] = 7, /* dma */
[IRQ_TCERRINT] = 7, /* dma */
[IRQ_DM646X_TCERRINT2] = 7,
[IRQ_DM646X_TCERRINT3] = 7,
[IRQ_DM646X_IDE] = 7,
[IRQ_DM646X_HPIINT] = 7,
[IRQ_DM646X_EMACRXTHINT] = 7,
[IRQ_DM646X_EMACRXINT] = 7,
[IRQ_DM646X_EMACTXINT] = 7,
[IRQ_DM646X_EMACMISCINT] = 7,
[IRQ_DM646X_MCASP0TXINT] = 7,
[IRQ_DM646X_MCASP0RXINT] = 7,
[IRQ_DM646X_RESERVED_3] = 7,
[IRQ_DM646X_MCASP1TXINT] = 7,
[IRQ_TINT0_TINT12] = 7, /* clockevent */
[IRQ_TINT0_TINT34] = 7, /* clocksource */
[IRQ_TINT1_TINT12] = 7, /* DSP timer */
[IRQ_TINT1_TINT34] = 7, /* system tick */
[IRQ_PWMINT0] = 7,
[IRQ_PWMINT1] = 7,
[IRQ_DM646X_VLQINT] = 7,
[IRQ_I2C] = 7,
[IRQ_UARTINT0] = 7,
[IRQ_UARTINT1] = 7,
[IRQ_DM646X_UARTINT2] = 7,
[IRQ_DM646X_SPINT0] = 7,
[IRQ_DM646X_SPINT1] = 7,
[IRQ_DM646X_DSP2ARMINT] = 7,
[IRQ_DM646X_RESERVED_4] = 7,
[IRQ_DM646X_PSCINT] = 7,
[IRQ_DM646X_GPIO0] = 7,
[IRQ_DM646X_GPIO1] = 7,
[IRQ_DM646X_GPIO2] = 7,
[IRQ_DM646X_GPIO3] = 7,
[IRQ_DM646X_GPIO4] = 7,
[IRQ_DM646X_GPIO5] = 7,
[IRQ_DM646X_GPIO6] = 7,
[IRQ_DM646X_GPIO7] = 7,
[IRQ_DM646X_GPIOBNK0] = 7,
[IRQ_DM646X_GPIOBNK1] = 7,
[IRQ_DM646X_GPIOBNK2] = 7,
[IRQ_DM646X_DDRINT] = 7,
[IRQ_DM646X_AEMIFINT] = 7,
[IRQ_COMMTX] = 7,
[IRQ_COMMRX] = 7,
[IRQ_EMUINT] = 7,
};
/*----------------------------------------------------------------------*/
/* Four Transfer Controllers on DM646x */
static s8 dm646x_queue_priority_mapping[][2] = {
/* {event queue no, Priority} */
{0, 4},
{1, 0},
{2, 5},
{3, 1},
{-1, -1},
};
static const struct dma_slave_map dm646x_edma_map[] = {
{ "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 6) },
{ "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 9) },
{ "davinci-mcasp.1", "tx", EDMA_FILTER_PARAM(0, 12) },
{ "spi_davinci", "tx", EDMA_FILTER_PARAM(0, 16) },
{ "spi_davinci", "rx", EDMA_FILTER_PARAM(0, 17) },
};
static struct edma_soc_info dm646x_edma_pdata = {
.queue_priority_mapping = dm646x_queue_priority_mapping,
.default_queue = EVENTQ_1,
.slave_map = dm646x_edma_map,
.slavecnt = ARRAY_SIZE(dm646x_edma_map),
};
static struct resource edma_resources[] = {
{
.name = "edma3_cc",
.start = 0x01c00000,
.end = 0x01c00000 + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
{
.name = "edma3_tc0",
.start = 0x01c10000,
.end = 0x01c10000 + SZ_1K - 1,
.flags = IORESOURCE_MEM,
},
{
.name = "edma3_tc1",
.start = 0x01c10400,
.end = 0x01c10400 + SZ_1K - 1,
.flags = IORESOURCE_MEM,
},
{
.name = "edma3_tc2",
.start = 0x01c10800,
.end = 0x01c10800 + SZ_1K - 1,
.flags = IORESOURCE_MEM,
},
{
.name = "edma3_tc3",
.start = 0x01c10c00,
.end = 0x01c10c00 + SZ_1K - 1,
.flags = IORESOURCE_MEM,
},
{
.name = "edma3_ccint",
.start = DAVINCI_INTC_IRQ(IRQ_CCINT0),
.flags = IORESOURCE_IRQ,
},
{
.name = "edma3_ccerrint",
.start = DAVINCI_INTC_IRQ(IRQ_CCERRINT),
.flags = IORESOURCE_IRQ,
},
/* not using TC*_ERR */
};
static const struct platform_device_info dm646x_edma_device __initconst = {
.name = "edma",
.id = 0,
.dma_mask = DMA_BIT_MASK(32),
.res = edma_resources,
.num_res = ARRAY_SIZE(edma_resources),
.data = &dm646x_edma_pdata,
.size_data = sizeof(dm646x_edma_pdata),
};
static struct resource dm646x_mcasp0_resources[] = {
{
.name = "mpu",
.start = DAVINCI_DM646X_MCASP0_REG_BASE,
.end = DAVINCI_DM646X_MCASP0_REG_BASE + (SZ_1K << 1) - 1,
.flags = IORESOURCE_MEM,
},
{
.name = "tx",
.start = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
.end = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
.flags = IORESOURCE_DMA,
},
{
.name = "rx",
.start = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
.end = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
.flags = IORESOURCE_DMA,
},
{
.name = "tx",
.start = DAVINCI_INTC_IRQ(IRQ_DM646X_MCASP0TXINT),
.flags = IORESOURCE_IRQ,
},
{
.name = "rx",
.start = DAVINCI_INTC_IRQ(IRQ_DM646X_MCASP0RXINT),
.flags = IORESOURCE_IRQ,
},
};
/* DIT mode only, rx is not supported */
static struct resource dm646x_mcasp1_resources[] = {
{
.name = "mpu",
.start = DAVINCI_DM646X_MCASP1_REG_BASE,
.end = DAVINCI_DM646X_MCASP1_REG_BASE + (SZ_1K << 1) - 1,
.flags = IORESOURCE_MEM,
},
{
.name = "tx",
.start = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
.end = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
.flags = IORESOURCE_DMA,
},
{
.name = "tx",
.start = DAVINCI_INTC_IRQ(IRQ_DM646X_MCASP1TXINT),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device dm646x_mcasp0_device = {
.name = "davinci-mcasp",
.id = 0,
.num_resources = ARRAY_SIZE(dm646x_mcasp0_resources),
.resource = dm646x_mcasp0_resources,
};
static struct platform_device dm646x_mcasp1_device = {
.name = "davinci-mcasp",
.id = 1,
.num_resources = ARRAY_SIZE(dm646x_mcasp1_resources),
.resource = dm646x_mcasp1_resources,
};
static struct platform_device dm646x_dit_device = {
.name = "spdif-dit",
.id = -1,
};
static u64 vpif_dma_mask = DMA_BIT_MASK(32);
static struct resource vpif_resource[] = {
{
.start = DAVINCI_VPIF_BASE,
.end = DAVINCI_VPIF_BASE + 0x03ff,
.flags = IORESOURCE_MEM,
}
};
static struct platform_device vpif_dev = {
.name = "vpif",
.id = -1,
.dev = {
.dma_mask = &vpif_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.resource = vpif_resource,
.num_resources = ARRAY_SIZE(vpif_resource),
};
static struct resource vpif_display_resource[] = {
{
.start = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT2),
.end = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT2),
.flags = IORESOURCE_IRQ,
},
{
.start = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT3),
.end = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT3),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device vpif_display_dev = {
.name = "vpif_display",
.id = -1,
.dev = {
.dma_mask = &vpif_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.resource = vpif_display_resource,
.num_resources = ARRAY_SIZE(vpif_display_resource),
};
static struct resource vpif_capture_resource[] = {
{
.start = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT0),
.end = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT0),
.flags = IORESOURCE_IRQ,
},
{
.start = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT1),
.end = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT1),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device vpif_capture_dev = {
.name = "vpif_capture",
.id = -1,
.dev = {
.dma_mask = &vpif_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.resource = vpif_capture_resource,
.num_resources = ARRAY_SIZE(vpif_capture_resource),
};
static struct resource dm646x_gpio_resources[] = {
{ /* registers */
.start = DAVINCI_GPIO_BASE,
.end = DAVINCI_GPIO_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
{ /* interrupt */
.start = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK0),
.end = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK0),
.flags = IORESOURCE_IRQ,
},
{
.start = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK1),
.end = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK1),
.flags = IORESOURCE_IRQ,
},
{
.start = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK2),
.end = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK2),
.flags = IORESOURCE_IRQ,
},
};
static struct davinci_gpio_platform_data dm646x_gpio_platform_data = {
.no_auto_base = true,
.base = 0,
.ngpio = 43,
};
int __init dm646x_gpio_register(void)
{
return davinci_gpio_register(dm646x_gpio_resources,
ARRAY_SIZE(dm646x_gpio_resources),
&dm646x_gpio_platform_data);
}
/*----------------------------------------------------------------------*/
static struct map_desc dm646x_io_desc[] = {
{
.virtual = IO_VIRT,
.pfn = __phys_to_pfn(IO_PHYS),
.length = IO_SIZE,
.type = MT_DEVICE
},
};
/* Contents of JTAG ID register used to identify exact cpu type */
static struct davinci_id dm646x_ids[] = {
{
.variant = 0x0,
.part_no = 0xb770,
.manufacturer = 0x017,
.cpu_id = DAVINCI_CPU_ID_DM6467,
.name = "dm6467_rev1.x",
},
{
.variant = 0x1,
.part_no = 0xb770,
.manufacturer = 0x017,
.cpu_id = DAVINCI_CPU_ID_DM6467,
.name = "dm6467_rev3.x",
},
};
/*
* Bottom half of timer0 is used for clockevent, top half is used for
* clocksource.
*/
static const struct davinci_timer_cfg dm646x_timer_cfg = {
.reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_4K),
.irq = {
DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12)),
DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34)),
},
};
static struct plat_serial8250_port dm646x_serial0_platform_data[] = {
{
.mapbase = DAVINCI_UART0_BASE,
.irq = DAVINCI_INTC_IRQ(IRQ_UARTINT0),
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
UPF_IOREMAP,
.iotype = UPIO_MEM32,
.regshift = 2,
},
{
.flags = 0,
}
};
static struct plat_serial8250_port dm646x_serial1_platform_data[] = {
{
.mapbase = DAVINCI_UART1_BASE,
.irq = DAVINCI_INTC_IRQ(IRQ_UARTINT1),
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
UPF_IOREMAP,
.iotype = UPIO_MEM32,
.regshift = 2,
},
{
.flags = 0,
}
};
static struct plat_serial8250_port dm646x_serial2_platform_data[] = {
{
.mapbase = DAVINCI_UART2_BASE,
.irq = DAVINCI_INTC_IRQ(IRQ_DM646X_UARTINT2),
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
UPF_IOREMAP,
.iotype = UPIO_MEM32,
.regshift = 2,
},
{
.flags = 0,
}
};
struct platform_device dm646x_serial_device[] = {
{
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM,
.dev = {
.platform_data = dm646x_serial0_platform_data,
}
},
{
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM1,
.dev = {
.platform_data = dm646x_serial1_platform_data,
}
},
{
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM2,
.dev = {
.platform_data = dm646x_serial2_platform_data,
}
},
{
}
};
static const struct davinci_soc_info davinci_soc_info_dm646x = {
.io_desc = dm646x_io_desc,
.io_desc_num = ARRAY_SIZE(dm646x_io_desc),
.jtag_id_reg = 0x01c40028,
.ids = dm646x_ids,
.ids_num = ARRAY_SIZE(dm646x_ids),
.pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
.pinmux_pins = dm646x_pins,
.pinmux_pins_num = ARRAY_SIZE(dm646x_pins),
.emac_pdata = &dm646x_emac_pdata,
.sram_dma = 0x10010000,
.sram_len = SZ_32K,
};
void __init dm646x_init_mcasp0(struct snd_platform_data *pdata)
{
dm646x_mcasp0_device.dev.platform_data = pdata;
platform_device_register(&dm646x_mcasp0_device);
}
void __init dm646x_init_mcasp1(struct snd_platform_data *pdata)
{
dm646x_mcasp1_device.dev.platform_data = pdata;
platform_device_register(&dm646x_mcasp1_device);
platform_device_register(&dm646x_dit_device);
}
void dm646x_setup_vpif(struct vpif_display_config *display_config,
struct vpif_capture_config *capture_config)
{
unsigned int value;
value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
value &= ~VSCLKDIS_MASK;
__raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN));
value &= ~VDD3P3V_VID_MASK;
__raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN));
davinci_cfg_reg(DM646X_STSOMUX_DISABLE);
davinci_cfg_reg(DM646X_STSIMUX_DISABLE);
davinci_cfg_reg(DM646X_PTSOMUX_DISABLE);
davinci_cfg_reg(DM646X_PTSIMUX_DISABLE);
vpif_display_dev.dev.platform_data = display_config;
vpif_capture_dev.dev.platform_data = capture_config;
platform_device_register(&vpif_dev);
platform_device_register(&vpif_display_dev);
platform_device_register(&vpif_capture_dev);
}
int __init dm646x_init_edma(struct edma_rsv_info *rsv)
{
struct platform_device *edma_pdev;
dm646x_edma_pdata.rsv = rsv;
edma_pdev = platform_device_register_full(&dm646x_edma_device);
return PTR_ERR_OR_ZERO(edma_pdev);
}
void __init dm646x_init(void)
{
davinci_common_init(&davinci_soc_info_dm646x);
davinci_map_sysmod();
}
void __init dm646x_init_time(unsigned long ref_clk_rate,
unsigned long aux_clkin_rate)
{
void __iomem *pll1, *psc;
struct clk *clk;
int rv;
clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, ref_clk_rate);
clk_register_fixed_rate(NULL, "aux_clkin", NULL, 0, aux_clkin_rate);
pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K);
dm646x_pll1_init(NULL, pll1, NULL);
psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K);
dm646x_psc_init(NULL, psc);
clk = clk_get(NULL, "timer0");
if (WARN_ON(IS_ERR(clk))) {
pr_err("Unable to get the timer clock\n");
return;
}
rv = davinci_timer_register(clk, &dm646x_timer_cfg);
WARN(rv, "Unable to register the timer: %d\n", rv);
}
static struct resource dm646x_pll2_resources[] = {
{
.start = DAVINCI_PLL2_BASE,
.end = DAVINCI_PLL2_BASE + SZ_1K - 1,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device dm646x_pll2_device = {
.name = "dm646x-pll2",
.id = -1,
.resource = dm646x_pll2_resources,
.num_resources = ARRAY_SIZE(dm646x_pll2_resources),
};
void __init dm646x_register_clocks(void)
{
/* PLL1 and PSC are registered in dm646x_init_time() */
platform_device_register(&dm646x_pll2_device);
}
static const struct davinci_aintc_config dm646x_aintc_config = {
.reg = {
.start = DAVINCI_ARM_INTC_BASE,
.end = DAVINCI_ARM_INTC_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
.num_irqs = 64,
.prios = dm646x_default_priorities,
};
void __init dm646x_init_irq(void)
{
davinci_aintc_init(&dm646x_aintc_config);
}
static int __init dm646x_init_devices(void)
{
int ret = 0;
if (!cpu_is_davinci_dm646x())
return 0;
platform_device_register(&dm646x_mdio_device);
platform_device_register(&dm646x_emac_device);
ret = davinci_init_wdt();
if (ret)
pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
return ret;
}
postcore_initcall(dm646x_init_devices);
arch/arm/mach-dove/Kconfig
View file @ e233cc59
......@@ -8,6 +8,7 @@ menuconfig ARCH_DOVE
select PINCTRL_DOVE
select PLAT_ORION_LEGACY
select PM_GENERIC_DOMAINS if PM
select PCI_QUIRKS if PCI
help
Support for the Marvell Dove SoC 88AP510
......
arch/arm/mach-dove/pcie.c
View file @ e233cc59
......@@ -136,14 +136,19 @@ static struct pci_ops pcie_ops = {
.write = pcie_wr_conf,
};
/*
* The root complex has a hardwired class of PCI_CLASS_MEMORY_OTHER, when it
* is operating as a root complex this needs to be switched to
* PCI_CLASS_BRIDGE_HOST or Linux will errantly try to process the BAR's on
* the device. Decoding setup is handled by the orion code.
*/
static void rc_pci_fixup(struct pci_dev *dev)
{
/*
* Prevent enumeration of root complex.
*/
if (dev->bus->parent == NULL && dev->devfn == 0) {
int i;
dev->class &= 0xff;
dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
dev->resource[i].start = 0;
dev->resource[i].end = 0;
......
arch/arm/mach-imx/Kconfig
View file @ e233cc59
......@@ -96,7 +96,7 @@ config SOC_IMX5
select HAVE_IMX_SRC
select MXC_TZIC
config SOC_IMX50
config SOC_IMX50
bool "i.MX50 support"
select PINCTRL_IMX50
select SOC_IMX5
......@@ -111,7 +111,7 @@ config SOC_IMX51
help
This enables support for Freescale i.MX51 processor
config SOC_IMX53
config SOC_IMX53
bool "i.MX53 support"
select PINCTRL_IMX53
select SOC_IMX5
......@@ -216,7 +216,7 @@ config SOC_IMX7D
select SOC_IMX7D_CM4 if ARM_SINGLE_ARMV7M
select ARM_ERRATA_814220 if ARCH_MULTI_V7
help
This enables support for Freescale i.MX7 Dual processor.
This enables support for Freescale i.MX7 Dual processor.
config SOC_IMX7ULP
bool "i.MX7ULP support"
......
arch/arm/mach-imx/cpu-imx25.c
View file @ e233cc59
......@@ -32,6 +32,8 @@ static int mx25_read_cpu_rev(void)
return IMX_CHIP_REVISION_1_0;
case 0x01:
return IMX_CHIP_REVISION_1_1;
case 0x02:
return IMX_CHIP_REVISION_1_2;
default:
return IMX_CHIP_REVISION_UNKNOWN;
}
......
arch/arm/mach-mv78xx0/pcie.c
View file @ e233cc59
......@@ -180,14 +180,19 @@ static struct pci_ops pcie_ops = {
.write = pcie_wr_conf,
};
/*
* The root complex has a hardwired class of PCI_CLASS_MEMORY_OTHER, when it
* is operating as a root complex this needs to be switched to
* PCI_CLASS_BRIDGE_HOST or Linux will errantly try to process the BAR's on
* the device. Decoding setup is handled by the orion code.
*/
static void rc_pci_fixup(struct pci_dev *dev)
{
/*
* Prevent enumeration of root complex.
*/
if (dev->bus->parent == NULL && dev->devfn == 0) {
int i;
dev->class &= 0xff;
dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
dev->resource[i].start = 0;
dev->resource[i].end = 0;
......
arch/arm/mach-omap2/Kconfig
View file @ e233cc59
......@@ -123,7 +123,7 @@ config ARCH_OMAP2PLUS
config OMAP_INTERCONNECT_BARRIER
bool
select ARM_HEAVY_MB
config ARCH_OMAP
bool
......@@ -243,10 +243,10 @@ config MACH_OMAP2_TUSB6010
default y if MACH_NOKIA_N8X0
config MACH_NOKIA_N810
bool
bool
config MACH_NOKIA_N810_WIMAX
bool
bool
config MACH_NOKIA_N8X0
bool "Nokia N800/N810"
......
arch/arm/mach-omap2/display.c
View file @ e233cc59
......@@ -211,6 +211,7 @@ static int __init omapdss_init_fbdev(void)
node = of_find_node_by_name(NULL, "omap4_padconf_global");
if (node)
omap4_dsi_mux_syscon = syscon_node_to_regmap(node);
of_node_put(node);
return 0;
}
......@@ -259,11 +260,13 @@ static int __init omapdss_init_of(void)
if (!pdev) {
pr_err("Unable to find DSS platform device\n");
of_node_put(node);
return -ENODEV;
}
r = of_platform_populate(node, NULL, NULL, &pdev->dev);
put_device(&pdev->dev);
of_node_put(node);
if (r) {
pr_err("Unable to populate DSS submodule devices\n");
return r;
......
arch/arm/mach-omap2/pdata-quirks.c
View file @ e233cc59
......@@ -540,6 +540,8 @@ pdata_quirks_init_clocks(const struct of_device_id *omap_dt_match_table)
of_platform_populate(np, omap_dt_match_table,
omap_auxdata_lookup, NULL);
of_node_put(np);
}
}
......
arch/arm/mach-omap2/prm3xxx.c
View file @ e233cc59
......@@ -708,6 +708,7 @@ static int omap3xxx_prm_late_init(void)
}
irq_num = of_irq_get(np, 0);
of_node_put(np);
if (irq_num == -EPROBE_DEFER)
return irq_num;
......
arch/arm/mach-orion5x/Kconfig
View file @ e233cc59
......@@ -7,6 +7,7 @@ menuconfig ARCH_ORION5X
select GPIOLIB
select MVEBU_MBUS
select FORCE_PCI
select PCI_QUIRKS
select PHYLIB if NETDEVICES
select PLAT_ORION_LEGACY
help
......
arch/arm/mach-orion5x/pci.c
View file @ e233cc59
......@@ -515,14 +515,20 @@ static int __init pci_setup(struct pci_sys_data *sys)
/*****************************************************************************
* General PCIe + PCI
****************************************************************************/
/*
* The root complex has a hardwired class of PCI_CLASS_MEMORY_OTHER, when it
* is operating as a root complex this needs to be switched to
* PCI_CLASS_BRIDGE_HOST or Linux will errantly try to process the BAR's on
* the device. Decoding setup is handled by the orion code.
*/
static void rc_pci_fixup(struct pci_dev *dev)
{
/*
* Prevent enumeration of root complex.
*/
if (dev->bus->parent == NULL && dev->devfn == 0) {
int i;
dev->class &= 0xff;
dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
dev->resource[i].start = 0;
dev->resource[i].end = 0;
......
arch/arm/mach-s3c/Kconfig
View file @ e233cc59
......@@ -43,12 +43,12 @@ config SAMSUNG_ATAGS
def_bool n
depends on ATAGS
help
This option enables ATAGS based boot support code for
Samsung platforms, including static platform devices, legacy
clock, timer and interrupt initialization, etc.
This option enables ATAGS based boot support code for
Samsung platforms, including static platform devices, legacy
clock, timer and interrupt initialization, etc.
Platforms that support only DT based boot need not to select
this option.
Platforms that support only DT based boot need not to select
this option.
if SAMSUNG_ATAGS
......@@ -102,7 +102,7 @@ config S3C_DEV_HSMMC3
config S3C_DEV_HWMON
bool
help
Compile in platform device definitions for HWMON
Compile in platform device definitions for HWMON
config S3C_DEV_I2C1
bool
......@@ -194,7 +194,7 @@ config S3C64XX_DEV_SPI0
config SAMSUNG_DEV_TS
bool
help
Common in platform device definitions for touchscreen device
Common in platform device definitions for touchscreen device
config SAMSUNG_DEV_KEYPAD
bool
......
arch/arm/mach-s3c/Kconfig.s3c24xx
View file @ e233cc59
......@@ -37,8 +37,6 @@ config PLAT_S3C24XX
help
Base platform code for any Samsung S3C24XX device
menu "Samsung S3C24XX SoCs Support"
comment "S3C24XX SoCs"
......@@ -293,7 +291,7 @@ config MACH_VR1000
help
Say Y here if you are using the Thorcom VR1000 board.
endif # CPU_S3C2410
endif # CPU_S3C2410
config S3C2412_PM_SLEEP
bool
......@@ -367,7 +365,7 @@ config MACH_VSTMS
help
Say Y here if you are using an VSTMS board
endif # CPU_S3C2412
endif # CPU_S3C2412
if CPU_S3C2416
......@@ -415,7 +413,7 @@ config MACH_S3C2416_DT
Note: This is under development and not all peripherals can be supported
with this machine file.
endif # CPU_S3C2416
endif # CPU_S3C2416
if CPU_S3C2440 || CPU_S3C2442
......@@ -444,7 +442,7 @@ config S3C2440_PLL_16934400
default y if S3C24XX_PLL
help
PLL tables for S3C2440 or S3C2442 CPUs with 16.934MHz crystals.
endif
endif # CPU_S3C2440 || CPU_S3C2442
if CPU_S3C2440
......@@ -540,7 +538,7 @@ config SMDK2440_CPU2440
default y if ARCH_S3C2440
select S3C2440_XTAL_16934400
endif # CPU_S3C2440
endif # CPU_S3C2440
if CPU_S3C2442
......@@ -559,7 +557,7 @@ config MACH_NEO1973_GTA02
select POWER_SUPPLY
select S3C_DEV_USB_HOST
help
Say Y here if you are using the Openmoko GTA02 / Freerunner GSM Phone
Say Y here if you are using the Openmoko GTA02 / Freerunner GSM Phone
config MACH_RX1950
bool "HP iPAQ rx1950"
......@@ -570,9 +568,9 @@ config MACH_RX1950
select S3C2440_XTAL_16934400
select S3C_DEV_NAND
help
Say Y here if you're using HP iPAQ rx1950
Say Y here if you're using HP iPAQ rx1950
endif # CPU_S3C2442
endif # CPU_S3C2442
if CPU_S3C2443 || CPU_S3C2416
......@@ -581,7 +579,7 @@ config S3C2443_SETUP_SPI
help
Common setup code for SPI GPIO configurations
endif # CPU_S3C2443 || CPU_S3C2416
endif # CPU_S3C2443 || CPU_S3C2416
if CPU_S3C2443
......@@ -594,13 +592,13 @@ config MACH_SMDK2443
help
Say Y here if you are using an SMDK2443
endif # CPU_S3C2443
endif # CPU_S3C2443
config PM_H1940
bool
help
Internal node for H1940 and related PM
endmenu # Samsung S3C24XX SoCs Support
endmenu # "Samsung S3C24XX SoCs Support"
endif # ARCH_S3C24XX
endif # ARCH_S3C24XX
arch/arm/mach-s3c/Kconfig.s3c64xx
View file @ e233cc59
......@@ -104,7 +104,7 @@ config S3C64XX_SETUP_SDHCI_GPIO
config S3C64XX_SETUP_SPI
bool
help
Common setup code for SPI GPIO configurations
Common setup code for SPI GPIO configurations
config S3C64XX_SETUP_USB_PHY
bool
......@@ -114,7 +114,7 @@ config S3C64XX_SETUP_USB_PHY
# S36400 Macchine support
config MACH_SMDK6400
bool "SMDK6400"
bool "SMDK6400"
depends on ATAGS
select CPU_S3C6400
select S3C64XX_SETUP_SDHCI
......@@ -205,7 +205,7 @@ config SMDK6410_SD_CH0
bool "Use channel 0 only"
depends on MACH_SMDK6410
help
Select CON7 (channel 0) as the MMC/SD slot, as
Select CON7 (channel 0) as the MMC/SD slot, as
at least some SMDK6410 boards come with the
resistors fitted so that the card detects for
channels 0 and 1 are the same.
......@@ -214,7 +214,7 @@ config SMDK6410_SD_CH1
bool "Use channel 1 only"
depends on MACH_SMDK6410
help
Select CON6 (channel 1) as the MMC/SD slot, as
Select CON6 (channel 1) as the MMC/SD slot, as
at least some SMDK6410 boards come with the
resistors fitted so that the card detects for
channels 0 and 1 are the same.
......@@ -260,7 +260,7 @@ config MACH_NCP
select S3C_DEV_HSMMC1
select S3C_DEV_I2C1
help
Machine support for the Samsung NCP
Machine support for the Samsung NCP
config MACH_HMT
bool "Airgoo HMT"
......@@ -292,21 +292,21 @@ config MACH_SMARTQ
select SAMSUNG_DEV_PWM
select SAMSUNG_DEV_TS
help
Shared machine support for SmartQ 5/7
Shared machine support for SmartQ 5/7
config MACH_SMARTQ5
bool "SmartQ 5"
depends on ATAGS
select MACH_SMARTQ
help
Machine support for the SmartQ 5
Machine support for the SmartQ 5
config MACH_SMARTQ7
bool "SmartQ 7"
depends on ATAGS
select MACH_SMARTQ
help
Machine support for the SmartQ 7
Machine support for the SmartQ 7
config MACH_WLF_CRAGG_6410
bool "Wolfson Cragganmore 6410"
......
arch/arm/mach-s3c/mach-mini2440.c
View file @ e233cc59
......@@ -624,7 +624,7 @@ static char mini2440_features_str[12] __initdata = "0tb";
static int __init mini2440_features_setup(char *str)
{
if (str)
strlcpy(mini2440_features_str, str,
strscpy(mini2440_features_str, str,
sizeof(mini2440_features_str));
return 1;
}
......
arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c
View file @ e233cc59
......@@ -125,6 +125,7 @@ static int regulator_quirk_notify(struct notifier_block *nb,
list_for_each_entry_safe(pos, tmp, &quirk_list, list) {
list_del(&pos->list);
of_node_put(pos->np);
kfree(pos);
}
......@@ -174,11 +175,12 @@ static int __init rcar_gen2_regulator_quirk(void)
memcpy(&quirk->i2c_msg, id->data, sizeof(quirk->i2c_msg));
quirk->id = id;
quirk->np = np;
quirk->np = of_node_get(np);
quirk->i2c_msg.addr = addr;
ret = of_irq_parse_one(np, 0, argsa);
if (ret) { /* Skip invalid entry and continue */
of_node_put(np);
kfree(quirk);
continue;
}
......@@ -225,6 +227,7 @@ static int __init rcar_gen2_regulator_quirk(void)
err_mem:
list_for_each_entry_safe(pos, tmp, &quirk_list, list) {
list_del(&pos->list);
of_node_put(pos->np);
kfree(pos);
}
......
arch/arm/mach-zynq/common.c
View file @ e233cc59
......@@ -77,6 +77,7 @@ static int __init zynq_get_revision(void)
}
zynq_devcfg_base = of_iomap(np, 0);
of_node_put(np);
if (!zynq_devcfg_base) {
pr_err("%s: Unable to map I/O memory\n", __func__);
return -1;
......
drivers/firmware/xilinx/zynqmp.c
View file @ e233cc59
......@@ -2,7 +2,7 @@
/*
* Xilinx Zynq MPSoC Firmware layer
*
* Copyright (C) 2014-2021 Xilinx, Inc.
* Copyright (C) 2014-2022 Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Davorin Mista <davorin.mista@aggios.com>
......@@ -340,6 +340,20 @@ int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1,
static u32 pm_api_version;
static u32 pm_tz_version;
int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset)
{
int ret;
ret = zynqmp_pm_invoke_fn(TF_A_PM_REGISTER_SGI, sgi_num, reset, 0, 0,
NULL);
if (!ret)
return ret;
/* try old implementation as fallback strategy if above fails */
return zynqmp_pm_invoke_fn(PM_IOCTL, 0, IOCTL_REGISTER_SGI, sgi_num,
reset, NULL);
}
/**
* zynqmp_pm_get_api_version() - Get version number of PMU PM firmware
* @version: Returned version value
......
drivers/soc/xilinx/xlnx_event_manager.c
View file @ e233cc59
......@@ -647,8 +647,7 @@ static int xlnx_event_manager_probe(struct platform_device *pdev)
cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "soc/event:starting",
xlnx_event_cpuhp_start, xlnx_event_cpuhp_down);
ret = zynqmp_pm_invoke_fn(PM_IOCTL, 0, IOCTL_REGISTER_SGI, sgi_num,
0, NULL);
ret = zynqmp_pm_register_sgi(sgi_num, 0);
if (ret) {
dev_err(&pdev->dev, "SGI %d Registration over TF-A failed with %d\n", sgi_num, ret);
xlnx_event_cleanup_sgi(pdev);
......@@ -681,7 +680,7 @@ static int xlnx_event_manager_remove(struct platform_device *pdev)
kfree(eve_data);
}
ret = zynqmp_pm_invoke_fn(PM_IOCTL, 0, IOCTL_REGISTER_SGI, 0, 1, NULL);
ret = zynqmp_pm_register_sgi(0, 1);
if (ret)
dev_err(&pdev->dev, "SGI unregistration over TF-A failed with %d\n", ret);
......
include/linux/firmware/xlnx-zynqmp.h
View file @ e233cc59
......@@ -34,6 +34,7 @@
#define PM_API_VERSION_2 2
/* ATF only commands */
#define TF_A_PM_REGISTER_SGI 0xa04
#define PM_GET_TRUSTZONE_VERSION 0xa03
#define PM_SET_SUSPEND_MODE 0xa02
#define GET_CALLBACK_DATA 0xa01
......@@ -468,6 +469,7 @@ int zynqmp_pm_feature(const u32 api_id);
int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id);
int zynqmp_pm_set_feature_config(enum pm_feature_config_id id, u32 value);
int zynqmp_pm_get_feature_config(enum pm_feature_config_id id, u32 *payload);
int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset);
#else
static inline int zynqmp_pm_get_api_version(u32 *version)
{
......@@ -733,6 +735,11 @@ static inline int zynqmp_pm_get_feature_config(enum pm_feature_config_id id,
{
return -ENODEV;
}
static inline int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset)
{
return -ENODEV;
}
#endif
#endif /* __FIRMWARE_ZYNQMP_H__ */
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7