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Commit e2ebc659 authored by Bjorn Andersson's avatar Bjorn Andersson
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Merge branch '20240602114439.1611-1-quic_jkona@quicinc.com' into arm64-for-6.11 

Merge the SM8650 video and clock controller drivers to gain access to
the constants from the DeviceTree binding.
parents b7a28d8a 09ea4216
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Showing with 3979 additions and 8 deletions
Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
View file @ e2ebc659
......@@ -8,15 +8,17 @@ title: Qualcomm Camera Clock & Reset Controller on SM8450
maintainers:
- Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
- Jagadeesh Kona <quic_jkona@quicinc.com>
description: |
Qualcomm camera clock control module provides the clocks, resets and power
domains on SM8450.
See also::
See also:
include/dt-bindings/clock/qcom,sc8280xp-camcc.h
include/dt-bindings/clock/qcom,sm8450-camcc.h
include/dt-bindings/clock/qcom,sm8550-camcc.h
include/dt-bindings/clock/qcom,sc8280xp-camcc.h
include/dt-bindings/clock/qcom,sm8650-camcc.h
include/dt-bindings/clock/qcom,x1e80100-camcc.h
allOf:
......@@ -28,6 +30,7 @@ properties:
- qcom,sc8280xp-camcc
- qcom,sm8450-camcc
- qcom,sm8550-camcc
- qcom,sm8650-camcc
- qcom,x1e80100-camcc
clocks:
......
Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
View file @ e2ebc659
......@@ -8,18 +8,22 @@ title: Qualcomm Video Clock & Reset Controller on SM8450
maintainers:
- Taniya Das <quic_tdas@quicinc.com>
- Jagadeesh Kona <quic_jkona@quicinc.com>
description: |
Qualcomm video clock control module provides the clocks, resets and power
domains on SM8450.
See also:: include/dt-bindings/clock/qcom,videocc-sm8450.h
See also:
include/dt-bindings/clock/qcom,sm8450-videocc.h
include/dt-bindings/clock/qcom,sm8650-videocc.h
properties:
compatible:
enum:
- qcom,sm8450-videocc
- qcom,sm8550-videocc
- qcom,sm8650-videocc
reg:
maxItems: 1
......
drivers/clk/qcom/Kconfig
View file @ e2ebc659
......@@ -827,6 +827,14 @@ config SM_CAMCC_8550
Support for the camera clock controller on SM8550 devices.
Say Y if you want to support camera devices and camera functionality.
config SM_CAMCC_8650
tristate "SM8650 Camera Clock Controller"
depends on ARM64 || COMPILE_TEST
select SM_GCC_8650
help
Support for the camera clock controller on SM8650 devices.
Say Y if you want to support camera devices and camera functionality.
config SM_DISPCC_6115
tristate "SM6115 Display Clock Controller"
depends on ARM64 || COMPILE_TEST
......
drivers/clk/qcom/Makefile
View file @ e2ebc659
......@@ -109,6 +109,7 @@ obj-$(CONFIG_SM_CAMCC_6350) += camcc-sm6350.o
obj-$(CONFIG_SM_CAMCC_8250) += camcc-sm8250.o
obj-$(CONFIG_SM_CAMCC_8450) += camcc-sm8450.o
obj-$(CONFIG_SM_CAMCC_8550) += camcc-sm8550.o
obj-$(CONFIG_SM_CAMCC_8650) += camcc-sm8650.o
obj-$(CONFIG_SM_DISPCC_6115) += dispcc-sm6115.o
obj-$(CONFIG_SM_DISPCC_6125) += dispcc-sm6125.o
obj-$(CONFIG_SM_DISPCC_6350) += dispcc-sm6350.o
......
drivers/clk/qcom/camcc-sm8650.c 0 → 100644
View file @ e2ebc659
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,sm8650-camcc.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
enum {
DT_IFACE,
DT_BI_TCXO,
DT_BI_TCXO_AO,
DT_SLEEP_CLK,
};
enum {
P_BI_TCXO,
P_BI_TCXO_AO,
P_CAM_CC_PLL0_OUT_EVEN,
P_CAM_CC_PLL0_OUT_MAIN,
P_CAM_CC_PLL0_OUT_ODD,
P_CAM_CC_PLL1_OUT_EVEN,
P_CAM_CC_PLL2_OUT_EVEN,
P_CAM_CC_PLL2_OUT_MAIN,
P_CAM_CC_PLL3_OUT_EVEN,
P_CAM_CC_PLL4_OUT_EVEN,
P_CAM_CC_PLL5_OUT_EVEN,
P_CAM_CC_PLL6_OUT_EVEN,
P_CAM_CC_PLL7_OUT_EVEN,
P_CAM_CC_PLL8_OUT_EVEN,
P_CAM_CC_PLL9_OUT_EVEN,
P_CAM_CC_PLL9_OUT_ODD,
P_CAM_CC_PLL10_OUT_EVEN,
P_SLEEP_CLK,
};
static const struct pll_vco lucid_ole_vco[] = {
{ 249600000, 2300000000, 0 },
};
static const struct pll_vco rivian_ole_vco[] = {
{ 777000000, 1285000000, 0 },
};
static const struct alpha_pll_config cam_cc_pll0_config = {
.l = 0x3e,
.alpha = 0x8000,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x82aa299c,
.test_ctl_val = 0x00000000,
.test_ctl_hi_val = 0x00000003,
.test_ctl_hi1_val = 0x00009000,
.test_ctl_hi2_val = 0x00000034,
.user_ctl_val = 0x00008400,
.user_ctl_hi_val = 0x00000005,
};
static struct clk_alpha_pll cam_cc_pll0 = {
.offset = 0x0,
.vco_table = lucid_ole_vco,
.num_vco = ARRAY_SIZE(lucid_ole_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll0",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = {
.offset = 0x0,
.post_div_shift = 10,
.post_div_table = post_div_table_cam_cc_pll0_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll0_out_even",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_pll0.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
},
};
static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = {
{ 0x2, 3 },
{ }
};
static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = {
.offset = 0x0,
.post_div_shift = 14,
.post_div_table = post_div_table_cam_cc_pll0_out_odd,
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll0_out_odd",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_pll0.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
},
};
static const struct alpha_pll_config cam_cc_pll1_config = {
.l = 0x31,
.alpha = 0x7aaa,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x82aa299c,
.test_ctl_val = 0x00000000,
.test_ctl_hi_val = 0x00000003,
.test_ctl_hi1_val = 0x00009000,
.test_ctl_hi2_val = 0x00000034,
.user_ctl_val = 0x00000400,
.user_ctl_hi_val = 0x00000005,
};
static struct clk_alpha_pll cam_cc_pll1 = {
.offset = 0x1000,
.vco_table = lucid_ole_vco,
.num_vco = ARRAY_SIZE(lucid_ole_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll1",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = {
.offset = 0x1000,
.post_div_shift = 10,
.post_div_table = post_div_table_cam_cc_pll1_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll1_out_even",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_pll1.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
},
};
static const struct alpha_pll_config cam_cc_pll2_config = {
.l = 0x32,
.alpha = 0x0,
.config_ctl_val = 0x10000030,
.config_ctl_hi_val = 0x80890263,
.config_ctl_hi1_val = 0x00000217,
.user_ctl_val = 0x00000001,
.user_ctl_hi_val = 0x00000000,
};
static struct clk_alpha_pll cam_cc_pll2 = {
.offset = 0x2000,
.vco_table = rivian_ole_vco,
.num_vco = ARRAY_SIZE(rivian_ole_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll2",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_rivian_evo_ops,
},
},
};
static const struct alpha_pll_config cam_cc_pll3_config = {
.l = 0x30,
.alpha = 0x8aaa,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x82aa299c,
.test_ctl_val = 0x00000000,
.test_ctl_hi_val = 0x00000003,
.test_ctl_hi1_val = 0x00009000,
.test_ctl_hi2_val = 0x00000034,
.user_ctl_val = 0x00000400,
.user_ctl_hi_val = 0x00000005,
};
static struct clk_alpha_pll cam_cc_pll3 = {
.offset = 0x3000,
.vco_table = lucid_ole_vco,
.num_vco = ARRAY_SIZE(lucid_ole_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll3",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = {
.offset = 0x3000,
.post_div_shift = 10,
.post_div_table = post_div_table_cam_cc_pll3_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll3_out_even",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_pll3.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
},
};
static const struct alpha_pll_config cam_cc_pll4_config = {
.l = 0x30,
.alpha = 0x8aaa,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x82aa299c,
.test_ctl_val = 0x00000000,
.test_ctl_hi_val = 0x00000003,
.test_ctl_hi1_val = 0x00009000,
.test_ctl_hi2_val = 0x00000034,
.user_ctl_val = 0x00000400,
.user_ctl_hi_val = 0x00000005,
};
static struct clk_alpha_pll cam_cc_pll4 = {
.offset = 0x4000,
.vco_table = lucid_ole_vco,
.num_vco = ARRAY_SIZE(lucid_ole_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll4",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = {
.offset = 0x4000,
.post_div_shift = 10,
.post_div_table = post_div_table_cam_cc_pll4_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll4_out_even",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_pll4.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
},
};
static const struct alpha_pll_config cam_cc_pll5_config = {
.l = 0x30,
.alpha = 0x8aaa,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x82aa299c,
.test_ctl_val = 0x00000000,
.test_ctl_hi_val = 0x00000003,
.test_ctl_hi1_val = 0x00009000,
.test_ctl_hi2_val = 0x00000034,
.user_ctl_val = 0x00000400,
.user_ctl_hi_val = 0x00000005,
};
static struct clk_alpha_pll cam_cc_pll5 = {
.offset = 0x5000,
.vco_table = lucid_ole_vco,
.num_vco = ARRAY_SIZE(lucid_ole_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll5",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
static const struct clk_div_table post_div_table_cam_cc_pll5_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even = {
.offset = 0x5000,
.post_div_shift = 10,
.post_div_table = post_div_table_cam_cc_pll5_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll5_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll5_out_even",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_pll5.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
},
};
static const struct alpha_pll_config cam_cc_pll6_config = {
.l = 0x30,
.alpha = 0x8aaa,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x82aa299c,
.test_ctl_val = 0x00000000,
.test_ctl_hi_val = 0x00000003,
.test_ctl_hi1_val = 0x00009000,
.test_ctl_hi2_val = 0x00000034,
.user_ctl_val = 0x00000400,
.user_ctl_hi_val = 0x00000005,
};
static struct clk_alpha_pll cam_cc_pll6 = {
.offset = 0x6000,
.vco_table = lucid_ole_vco,
.num_vco = ARRAY_SIZE(lucid_ole_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll6",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
static const struct clk_div_table post_div_table_cam_cc_pll6_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even = {
.offset = 0x6000,
.post_div_shift = 10,
.post_div_table = post_div_table_cam_cc_pll6_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll6_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll6_out_even",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_pll6.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
},
};
static const struct alpha_pll_config cam_cc_pll7_config = {
.l = 0x30,
.alpha = 0x8aaa,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x82aa299c,
.test_ctl_val = 0x00000000,
.test_ctl_hi_val = 0x00000003,
.test_ctl_hi1_val = 0x00009000,
.test_ctl_hi2_val = 0x00000034,
.user_ctl_val = 0x00000400,
.user_ctl_hi_val = 0x00000005,
};
static struct clk_alpha_pll cam_cc_pll7 = {
.offset = 0x7000,
.vco_table = lucid_ole_vco,
.num_vco = ARRAY_SIZE(lucid_ole_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll7",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
static const struct clk_div_table post_div_table_cam_cc_pll7_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv cam_cc_pll7_out_even = {
.offset = 0x7000,
.post_div_shift = 10,
.post_div_table = post_div_table_cam_cc_pll7_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll7_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll7_out_even",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_pll7.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
},
};
static const struct alpha_pll_config cam_cc_pll8_config = {
.l = 0x14,
.alpha = 0xd555,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x82aa299c,
.test_ctl_val = 0x00000000,
.test_ctl_hi_val = 0x00000003,
.test_ctl_hi1_val = 0x00009000,
.test_ctl_hi2_val = 0x00000034,
.user_ctl_val = 0x00000400,
.user_ctl_hi_val = 0x00000005,
};
static struct clk_alpha_pll cam_cc_pll8 = {
.offset = 0x8000,
.vco_table = lucid_ole_vco,
.num_vco = ARRAY_SIZE(lucid_ole_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll8",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
static const struct clk_div_table post_div_table_cam_cc_pll8_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv cam_cc_pll8_out_even = {
.offset = 0x8000,
.post_div_shift = 10,
.post_div_table = post_div_table_cam_cc_pll8_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll8_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll8_out_even",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_pll8.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
},
};
static const struct alpha_pll_config cam_cc_pll9_config = {
.l = 0x32,
.alpha = 0x0,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x82aa299c,
.test_ctl_val = 0x00000000,
.test_ctl_hi_val = 0x00000003,
.test_ctl_hi1_val = 0x00009000,
.test_ctl_hi2_val = 0x00000034,
.user_ctl_val = 0x00008400,
.user_ctl_hi_val = 0x00000005,
};
static struct clk_alpha_pll cam_cc_pll9 = {
.offset = 0x9000,
.vco_table = lucid_ole_vco,
.num_vco = ARRAY_SIZE(lucid_ole_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll9",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
static const struct clk_div_table post_div_table_cam_cc_pll9_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv cam_cc_pll9_out_even = {
.offset = 0x9000,
.post_div_shift = 10,
.post_div_table = post_div_table_cam_cc_pll9_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll9_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll9_out_even",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_pll9.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
},
};
static const struct clk_div_table post_div_table_cam_cc_pll9_out_odd[] = {
{ 0x2, 3 },
{ }
};
static struct clk_alpha_pll_postdiv cam_cc_pll9_out_odd = {
.offset = 0x9000,
.post_div_shift = 14,
.post_div_table = post_div_table_cam_cc_pll9_out_odd,
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll9_out_odd),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll9_out_odd",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_pll9.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
},
};
static const struct alpha_pll_config cam_cc_pll10_config = {
.l = 0x30,
.alpha = 0x8aaa,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x82aa299c,
.test_ctl_val = 0x00000000,
.test_ctl_hi_val = 0x00000003,
.test_ctl_hi1_val = 0x00009000,
.test_ctl_hi2_val = 0x00000034,
.user_ctl_val = 0x00000400,
.user_ctl_hi_val = 0x00000005,
};
static struct clk_alpha_pll cam_cc_pll10 = {
.offset = 0xa000,
.vco_table = lucid_ole_vco,
.num_vco = ARRAY_SIZE(lucid_ole_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll10",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
static const struct clk_div_table post_div_table_cam_cc_pll10_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv cam_cc_pll10_out_even = {
.offset = 0xa000,
.post_div_shift = 10,
.post_div_table = post_div_table_cam_cc_pll10_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll10_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll10_out_even",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_pll10.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
},
};
static const struct parent_map cam_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_CAM_CC_PLL0_OUT_MAIN, 1 },
{ P_CAM_CC_PLL0_OUT_EVEN, 2 },
{ P_CAM_CC_PLL0_OUT_ODD, 3 },
{ P_CAM_CC_PLL9_OUT_ODD, 4 },
{ P_CAM_CC_PLL9_OUT_EVEN, 5 },
};
static const struct clk_parent_data cam_cc_parent_data_0[] = {
{ .index = DT_BI_TCXO },
{ .hw = &cam_cc_pll0.clkr.hw },
{ .hw = &cam_cc_pll0_out_even.clkr.hw },
{ .hw = &cam_cc_pll0_out_odd.clkr.hw },
{ .hw = &cam_cc_pll9_out_odd.clkr.hw },
{ .hw = &cam_cc_pll9_out_even.clkr.hw },
};
static const struct parent_map cam_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_CAM_CC_PLL2_OUT_EVEN, 3 },
{ P_CAM_CC_PLL2_OUT_MAIN, 5 },
};
static const struct clk_parent_data cam_cc_parent_data_1[] = {
{ .index = DT_BI_TCXO },
{ .hw = &cam_cc_pll2.clkr.hw },
{ .hw = &cam_cc_pll2.clkr.hw },
};
static const struct parent_map cam_cc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_CAM_CC_PLL8_OUT_EVEN, 6 },
};
static const struct clk_parent_data cam_cc_parent_data_2[] = {
{ .index = DT_BI_TCXO },
{ .hw = &cam_cc_pll8_out_even.clkr.hw },
};
static const struct parent_map cam_cc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
{ P_CAM_CC_PLL3_OUT_EVEN, 6 },
};
static const struct clk_parent_data cam_cc_parent_data_3[] = {
{ .index = DT_BI_TCXO },
{ .hw = &cam_cc_pll3_out_even.clkr.hw },
};
static const struct parent_map cam_cc_parent_map_4[] = {
{ P_BI_TCXO, 0 },
{ P_CAM_CC_PLL4_OUT_EVEN, 6 },
};
static const struct clk_parent_data cam_cc_parent_data_4[] = {
{ .index = DT_BI_TCXO },
{ .hw = &cam_cc_pll4_out_even.clkr.hw },
};
static const struct parent_map cam_cc_parent_map_5[] = {
{ P_BI_TCXO, 0 },
{ P_CAM_CC_PLL5_OUT_EVEN, 6 },
};
static const struct clk_parent_data cam_cc_parent_data_5[] = {
{ .index = DT_BI_TCXO },
{ .hw = &cam_cc_pll5_out_even.clkr.hw },
};
static const struct parent_map cam_cc_parent_map_6[] = {
{ P_BI_TCXO, 0 },
{ P_CAM_CC_PLL1_OUT_EVEN, 4 },
};
static const struct clk_parent_data cam_cc_parent_data_6[] = {
{ .index = DT_BI_TCXO },
{ .hw = &cam_cc_pll1_out_even.clkr.hw },
};
static const struct parent_map cam_cc_parent_map_7[] = {
{ P_BI_TCXO, 0 },
{ P_CAM_CC_PLL6_OUT_EVEN, 6 },
};
static const struct clk_parent_data cam_cc_parent_data_7[] = {
{ .index = DT_BI_TCXO },
{ .hw = &cam_cc_pll6_out_even.clkr.hw },
};
static const struct parent_map cam_cc_parent_map_8[] = {
{ P_BI_TCXO, 0 },
{ P_CAM_CC_PLL7_OUT_EVEN, 6 },
};
static const struct clk_parent_data cam_cc_parent_data_8[] = {
{ .index = DT_BI_TCXO },
{ .hw = &cam_cc_pll7_out_even.clkr.hw },
};
static const struct parent_map cam_cc_parent_map_9[] = {
{ P_BI_TCXO, 0 },
{ P_CAM_CC_PLL10_OUT_EVEN, 6 },
};
static const struct clk_parent_data cam_cc_parent_data_9[] = {
{ .index = DT_BI_TCXO },
{ .hw = &cam_cc_pll10_out_even.clkr.hw },
};
static const struct parent_map cam_cc_parent_map_10[] = {
{ P_SLEEP_CLK, 0 },
};
static const struct clk_parent_data cam_cc_parent_data_10[] = {
{ .index = DT_SLEEP_CLK },
};
static const struct parent_map cam_cc_parent_map_11_ao[] = {
{ P_BI_TCXO_AO, 0 },
};
static const struct clk_parent_data cam_cc_parent_data_11_ao[] = {
{ .index = DT_BI_TCXO_AO },
};
static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(200000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0),
F(400000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0),
F(480000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0),
F(785000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_bps_clk_src = {
.cmd_rcgr = 0x10050,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_2,
.freq_tbl = ftbl_cam_cc_bps_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_bps_clk_src",
.parent_data = cam_cc_parent_data_2,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_camnoc_axi_rt_clk_src[] = {
F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_camnoc_axi_rt_clk_src = {
.cmd_rcgr = 0x1325c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_camnoc_axi_rt_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_camnoc_axi_rt_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_cci_0_clk_src = {
.cmd_rcgr = 0x131cc,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_cci_0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cci_0_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_cc_cci_1_clk_src = {
.cmd_rcgr = 0x131e8,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_cci_0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cci_1_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_cc_cci_2_clk_src = {
.cmd_rcgr = 0x13204,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_cci_0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cci_2_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_cphy_rx_clk_src = {
.cmd_rcgr = 0x1104c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cphy_rx_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_cre_clk_src[] = {
F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0),
F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
F(480000000, P_CAM_CC_PLL9_OUT_EVEN, 1, 0, 0),
F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_cre_clk_src = {
.cmd_rcgr = 0x13144,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_cre_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cre_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = {
.cmd_rcgr = 0x150e0,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csi0phytimer_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = {
.cmd_rcgr = 0x15104,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csi1phytimer_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = {
.cmd_rcgr = 0x15124,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csi2phytimer_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = {
.cmd_rcgr = 0x15144,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csi3phytimer_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_cc_csi4phytimer_clk_src = {
.cmd_rcgr = 0x15164,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csi4phytimer_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_cc_csi5phytimer_clk_src = {
.cmd_rcgr = 0x15184,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csi5phytimer_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_cc_csi6phytimer_clk_src = {
.cmd_rcgr = 0x151a4,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csi6phytimer_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_cc_csi7phytimer_clk_src = {
.cmd_rcgr = 0x151c4,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csi7phytimer_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_csid_clk_src[] = {
F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_csid_clk_src = {
.cmd_rcgr = 0x13238,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_csid_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csid_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_fast_ahb_clk_src = {
.cmd_rcgr = 0x10018,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_fast_ahb_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_fast_ahb_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
F(480000000, P_CAM_CC_PLL9_OUT_EVEN, 1, 0, 0),
F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_icp_clk_src = {
.cmd_rcgr = 0x131a4,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_icp_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_icp_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(466000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
F(594000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
F(675000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
F(785000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_ife_0_clk_src = {
.cmd_rcgr = 0x11018,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_3,
.freq_tbl = ftbl_cam_cc_ife_0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ife_0_clk_src",
.parent_data = cam_cc_parent_data_3,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_ife_1_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(466000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
F(594000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
F(675000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
F(785000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_ife_1_clk_src = {
.cmd_rcgr = 0x12018,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_4,
.freq_tbl = ftbl_cam_cc_ife_1_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ife_1_clk_src",
.parent_data = cam_cc_parent_data_4,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_4),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_ife_2_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(466000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
F(594000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
F(675000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
F(785000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_ife_2_clk_src = {
.cmd_rcgr = 0x12068,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_5,
.freq_tbl = ftbl_cam_cc_ife_2_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ife_2_clk_src",
.parent_data = cam_cc_parent_data_5,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_5),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_cc_ife_lite_clk_src = {
.cmd_rcgr = 0x13000,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_csid_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ife_lite_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = {
.cmd_rcgr = 0x13028,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_csid_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ife_lite_csid_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_ipe_nps_clk_src[] = {
F(475000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
F(575000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
F(675000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
F(825000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_ipe_nps_clk_src = {
.cmd_rcgr = 0x10094,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_6,
.freq_tbl = ftbl_cam_cc_ipe_nps_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ipe_nps_clk_src",
.parent_data = cam_cc_parent_data_6,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_6),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_jpeg_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0),
F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
F(480000000, P_CAM_CC_PLL9_OUT_EVEN, 1, 0, 0),
F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_jpeg_clk_src = {
.cmd_rcgr = 0x13168,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_jpeg_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_jpeg_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(24000000, P_CAM_CC_PLL2_OUT_EVEN, 10, 1, 4),
F(68571429, P_CAM_CC_PLL2_OUT_MAIN, 14, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_mclk0_clk_src = {
.cmd_rcgr = 0x15000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_1,
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_mclk0_clk_src",
.parent_data = cam_cc_parent_data_1,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_cc_mclk1_clk_src = {
.cmd_rcgr = 0x1501c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_1,
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_mclk1_clk_src",
.parent_data = cam_cc_parent_data_1,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_cc_mclk2_clk_src = {
.cmd_rcgr = 0x15038,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_1,
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_mclk2_clk_src",
.parent_data = cam_cc_parent_data_1,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_cc_mclk3_clk_src = {
.cmd_rcgr = 0x15054,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_1,
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_mclk3_clk_src",
.parent_data = cam_cc_parent_data_1,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_cc_mclk4_clk_src = {
.cmd_rcgr = 0x15070,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_1,
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_mclk4_clk_src",
.parent_data = cam_cc_parent_data_1,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_cc_mclk5_clk_src = {
.cmd_rcgr = 0x1508c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_1,
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_mclk5_clk_src",
.parent_data = cam_cc_parent_data_1,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_cc_mclk6_clk_src = {
.cmd_rcgr = 0x150a8,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_1,
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_mclk6_clk_src",
.parent_data = cam_cc_parent_data_1,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_cc_mclk7_clk_src = {
.cmd_rcgr = 0x150c4,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_1,
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_mclk7_clk_src",
.parent_data = cam_cc_parent_data_1,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_qdss_debug_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(75000000, P_CAM_CC_PLL0_OUT_EVEN, 8, 0, 0),
F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0),
F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_qdss_debug_clk_src = {
.cmd_rcgr = 0x1329c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_qdss_debug_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_qdss_debug_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_sfe_0_clk_src[] = {
F(466000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
F(594000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
F(675000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
F(785000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_sfe_0_clk_src = {
.cmd_rcgr = 0x1306c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_7,
.freq_tbl = ftbl_cam_cc_sfe_0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_sfe_0_clk_src",
.parent_data = cam_cc_parent_data_7,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_7),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_sfe_1_clk_src[] = {
F(466000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0),
F(594000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0),
F(675000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0),
F(785000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_sfe_1_clk_src = {
.cmd_rcgr = 0x130bc,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_8,
.freq_tbl = ftbl_cam_cc_sfe_1_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_sfe_1_clk_src",
.parent_data = cam_cc_parent_data_8,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_8),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_sfe_2_clk_src[] = {
F(466000000, P_CAM_CC_PLL10_OUT_EVEN, 1, 0, 0),
F(594000000, P_CAM_CC_PLL10_OUT_EVEN, 1, 0, 0),
F(675000000, P_CAM_CC_PLL10_OUT_EVEN, 1, 0, 0),
F(785000000, P_CAM_CC_PLL10_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_sfe_2_clk_src = {
.cmd_rcgr = 0x1310c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_9,
.freq_tbl = ftbl_cam_cc_sfe_2_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_sfe_2_clk_src",
.parent_data = cam_cc_parent_data_9,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_9),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_sleep_clk_src[] = {
F(32000, P_SLEEP_CLK, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_sleep_clk_src = {
.cmd_rcgr = 0x132f0,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_10,
.freq_tbl = ftbl_cam_cc_sleep_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_sleep_clk_src",
.parent_data = cam_cc_parent_data_10,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_10),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_slow_ahb_clk_src = {
.cmd_rcgr = 0x10034,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_slow_ahb_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_slow_ahb_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] = {
F(19200000, P_BI_TCXO_AO, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_xo_clk_src = {
.cmd_rcgr = 0x132d4,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_11_ao,
.freq_tbl = ftbl_cam_cc_xo_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_xo_clk_src",
.parent_data = cam_cc_parent_data_11_ao,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_11_ao),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_branch cam_cc_bps_ahb_clk = {
.halt_reg = 0x1004c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1004c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_bps_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_slow_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_bps_clk = {
.halt_reg = 0x10068,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x10068,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_bps_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_bps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_bps_fast_ahb_clk = {
.halt_reg = 0x10030,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x10030,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_bps_fast_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_fast_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_bps_shift_clk = {
.halt_reg = 0x10078,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x10078,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_bps_shift_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_camnoc_axi_nrt_clk = {
.halt_reg = 0x13284,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x13284,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_camnoc_axi_nrt_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_camnoc_axi_rt_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_camnoc_axi_rt_clk = {
.halt_reg = 0x13274,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x13274,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_camnoc_axi_rt_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_camnoc_axi_rt_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_camnoc_dcd_xo_clk = {
.halt_reg = 0x13290,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x13290,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_camnoc_dcd_xo_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_camnoc_xo_clk = {
.halt_reg = 0x13294,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x13294,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_camnoc_xo_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cci_0_clk = {
.halt_reg = 0x131e4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x131e4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cci_0_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_cci_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cci_1_clk = {
.halt_reg = 0x13200,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x13200,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cci_1_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_cci_1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cci_2_clk = {
.halt_reg = 0x1321c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1321c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cci_2_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_cci_2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_core_ahb_clk = {
.halt_reg = 0x132d0,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x132d0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_core_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_slow_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cpas_ahb_clk = {
.halt_reg = 0x13220,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x13220,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cpas_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_slow_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cpas_bps_clk = {
.halt_reg = 0x10074,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x10074,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cpas_bps_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_bps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cpas_cre_clk = {
.halt_reg = 0x13160,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x13160,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cpas_cre_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_cre_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cpas_fast_ahb_clk = {
.halt_reg = 0x1322c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1322c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cpas_fast_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_fast_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cpas_ife_0_clk = {
.halt_reg = 0x1103c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1103c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cpas_ife_0_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ife_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cpas_ife_1_clk = {
.halt_reg = 0x1203c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1203c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cpas_ife_1_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ife_1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cpas_ife_2_clk = {
.halt_reg = 0x1208c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1208c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cpas_ife_2_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ife_2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cpas_ife_lite_clk = {
.halt_reg = 0x13024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x13024,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cpas_ife_lite_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ife_lite_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cpas_ipe_nps_clk = {
.halt_reg = 0x100b8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x100b8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cpas_ipe_nps_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ipe_nps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cpas_sbi_clk = {
.halt_reg = 0x10104,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x10104,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cpas_sbi_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ife_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cpas_sfe_0_clk = {
.halt_reg = 0x13090,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x13090,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cpas_sfe_0_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_sfe_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cpas_sfe_1_clk = {
.halt_reg = 0x130e0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x130e0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cpas_sfe_1_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_sfe_1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cpas_sfe_2_clk = {
.halt_reg = 0x13130,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x13130,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cpas_sfe_2_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_sfe_2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cre_ahb_clk = {
.halt_reg = 0x13164,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x13164,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cre_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_slow_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cre_clk = {
.halt_reg = 0x1315c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1315c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cre_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_cre_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csi0phytimer_clk = {
.halt_reg = 0x150f8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x150f8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csi0phytimer_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_csi0phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csi1phytimer_clk = {
.halt_reg = 0x1511c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1511c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csi1phytimer_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_csi1phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csi2phytimer_clk = {
.halt_reg = 0x1513c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1513c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csi2phytimer_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_csi2phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csi3phytimer_clk = {
.halt_reg = 0x1515c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1515c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csi3phytimer_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_csi3phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csi4phytimer_clk = {
.halt_reg = 0x1517c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1517c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csi4phytimer_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_csi4phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csi5phytimer_clk = {
.halt_reg = 0x1519c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1519c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csi5phytimer_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_csi5phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csi6phytimer_clk = {
.halt_reg = 0x151bc,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x151bc,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csi6phytimer_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_csi6phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csi7phytimer_clk = {
.halt_reg = 0x151dc,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x151dc,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csi7phytimer_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_csi7phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csid_clk = {
.halt_reg = 0x13250,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x13250,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csid_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_csid_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csid_csiphy_rx_clk = {
.halt_reg = 0x15100,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x15100,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csid_csiphy_rx_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csiphy0_clk = {
.halt_reg = 0x150fc,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x150fc,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csiphy0_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csiphy1_clk = {
.halt_reg = 0x15120,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x15120,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csiphy1_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csiphy2_clk = {
.halt_reg = 0x15140,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x15140,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csiphy2_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csiphy3_clk = {
.halt_reg = 0x15160,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x15160,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csiphy3_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csiphy4_clk = {
.halt_reg = 0x15180,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x15180,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csiphy4_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csiphy5_clk = {
.halt_reg = 0x151a0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x151a0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csiphy5_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csiphy6_clk = {
.halt_reg = 0x151c0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x151c0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csiphy6_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csiphy7_clk = {
.halt_reg = 0x151e0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x151e0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csiphy7_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_icp_ahb_clk = {
.halt_reg = 0x131c8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x131c8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_icp_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_slow_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_icp_clk = {
.halt_reg = 0x131bc,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x131bc,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_icp_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_icp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_0_clk = {
.halt_reg = 0x11030,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x11030,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ife_0_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ife_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_0_fast_ahb_clk = {
.halt_reg = 0x11048,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x11048,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ife_0_fast_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_fast_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_0_shift_clk = {
.halt_reg = 0x11064,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x11064,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ife_0_shift_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_1_clk = {
.halt_reg = 0x12030,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x12030,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ife_1_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ife_1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_1_fast_ahb_clk = {
.halt_reg = 0x12048,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x12048,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ife_1_fast_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_fast_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_1_shift_clk = {
.halt_reg = 0x1204c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1204c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ife_1_shift_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_2_clk = {
.halt_reg = 0x12080,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x12080,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ife_2_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ife_2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_2_fast_ahb_clk = {
.halt_reg = 0x12098,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x12098,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ife_2_fast_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_fast_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_2_shift_clk = {
.halt_reg = 0x1209c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1209c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ife_2_shift_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_lite_ahb_clk = {
.halt_reg = 0x13050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x13050,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ife_lite_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_slow_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_lite_clk = {
.halt_reg = 0x13018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x13018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ife_lite_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ife_lite_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = {
.halt_reg = 0x1304c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1304c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ife_lite_cphy_rx_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_lite_csid_clk = {
.halt_reg = 0x13040,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x13040,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ife_lite_csid_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ife_lite_csid_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ipe_nps_ahb_clk = {
.halt_reg = 0x100d0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x100d0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ipe_nps_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_slow_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ipe_nps_clk = {
.halt_reg = 0x100ac,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x100ac,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ipe_nps_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ipe_nps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ipe_nps_fast_ahb_clk = {
.halt_reg = 0x100d4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x100d4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ipe_nps_fast_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_fast_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ipe_pps_clk = {
.halt_reg = 0x100bc,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x100bc,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ipe_pps_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ipe_nps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ipe_pps_fast_ahb_clk = {
.halt_reg = 0x100d8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x100d8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ipe_pps_fast_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_fast_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ipe_shift_clk = {
.halt_reg = 0x100dc,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x100dc,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ipe_shift_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_jpeg_1_clk = {
.halt_reg = 0x1318c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1318c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_jpeg_1_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_jpeg_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_jpeg_clk = {
.halt_reg = 0x13180,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x13180,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_jpeg_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_jpeg_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_mclk0_clk = {
.halt_reg = 0x15018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x15018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_mclk0_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_mclk0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_mclk1_clk = {
.halt_reg = 0x15034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x15034,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_mclk1_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_mclk1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_mclk2_clk = {
.halt_reg = 0x15050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x15050,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_mclk2_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_mclk2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_mclk3_clk = {
.halt_reg = 0x1506c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1506c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_mclk3_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_mclk3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_mclk4_clk = {
.halt_reg = 0x15088,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x15088,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_mclk4_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_mclk4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_mclk5_clk = {
.halt_reg = 0x150a4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x150a4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_mclk5_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_mclk5_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_mclk6_clk = {
.halt_reg = 0x150c0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x150c0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_mclk6_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_mclk6_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_mclk7_clk = {
.halt_reg = 0x150dc,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x150dc,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_mclk7_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_mclk7_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_qdss_debug_clk = {
.halt_reg = 0x132b4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x132b4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_qdss_debug_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_qdss_debug_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_qdss_debug_xo_clk = {
.halt_reg = 0x132b8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x132b8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_qdss_debug_xo_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_sbi_clk = {
.halt_reg = 0x100f8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x100f8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_sbi_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ife_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_sbi_fast_ahb_clk = {
.halt_reg = 0x10108,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x10108,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_sbi_fast_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_fast_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_sbi_shift_clk = {
.halt_reg = 0x1010c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1010c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_sbi_shift_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_sfe_0_clk = {
.halt_reg = 0x13084,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x13084,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_sfe_0_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_sfe_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_sfe_0_fast_ahb_clk = {
.halt_reg = 0x1309c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1309c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_sfe_0_fast_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_fast_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_sfe_0_shift_clk = {
.halt_reg = 0x130a0,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x130a0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_sfe_0_shift_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_sfe_1_clk = {
.halt_reg = 0x130d4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x130d4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_sfe_1_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_sfe_1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_sfe_1_fast_ahb_clk = {
.halt_reg = 0x130ec,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x130ec,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_sfe_1_fast_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_fast_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_sfe_1_shift_clk = {
.halt_reg = 0x130f0,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x130f0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_sfe_1_shift_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_sfe_2_clk = {
.halt_reg = 0x13124,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x13124,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_sfe_2_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_sfe_2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_sfe_2_fast_ahb_clk = {
.halt_reg = 0x1313c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1313c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_sfe_2_fast_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_fast_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_sfe_2_shift_clk = {
.halt_reg = 0x13140,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x13140,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_sfe_2_shift_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_titan_top_shift_clk = {
.halt_reg = 0x1330c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1330c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_titan_top_shift_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc cam_cc_titan_top_gdsc = {
.gdscr = 0x132bc,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "cam_cc_titan_top_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct gdsc cam_cc_bps_gdsc = {
.gdscr = 0x10004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "cam_cc_bps_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.parent = &cam_cc_titan_top_gdsc.pd,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct gdsc cam_cc_ife_0_gdsc = {
.gdscr = 0x11004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "cam_cc_ife_0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.parent = &cam_cc_titan_top_gdsc.pd,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct gdsc cam_cc_ife_1_gdsc = {
.gdscr = 0x12004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "cam_cc_ife_1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.parent = &cam_cc_titan_top_gdsc.pd,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct gdsc cam_cc_ife_2_gdsc = {
.gdscr = 0x12054,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "cam_cc_ife_2_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.parent = &cam_cc_titan_top_gdsc.pd,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct gdsc cam_cc_ipe_0_gdsc = {
.gdscr = 0x10080,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "cam_cc_ipe_0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.parent = &cam_cc_titan_top_gdsc.pd,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct gdsc cam_cc_sbi_gdsc = {
.gdscr = 0x100e4,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "cam_cc_sbi_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.parent = &cam_cc_titan_top_gdsc.pd,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct gdsc cam_cc_sfe_0_gdsc = {
.gdscr = 0x13058,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "cam_cc_sfe_0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.parent = &cam_cc_titan_top_gdsc.pd,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct gdsc cam_cc_sfe_1_gdsc = {
.gdscr = 0x130a8,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "cam_cc_sfe_1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.parent = &cam_cc_titan_top_gdsc.pd,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct gdsc cam_cc_sfe_2_gdsc = {
.gdscr = 0x130f8,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "cam_cc_sfe_2_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.parent = &cam_cc_titan_top_gdsc.pd,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct clk_regmap *cam_cc_sm8650_clocks[] = {
[CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr,
[CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr,
[CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr,
[CAM_CC_BPS_FAST_AHB_CLK] = &cam_cc_bps_fast_ahb_clk.clkr,
[CAM_CC_BPS_SHIFT_CLK] = &cam_cc_bps_shift_clk.clkr,
[CAM_CC_CAMNOC_AXI_NRT_CLK] = &cam_cc_camnoc_axi_nrt_clk.clkr,
[CAM_CC_CAMNOC_AXI_RT_CLK] = &cam_cc_camnoc_axi_rt_clk.clkr,
[CAM_CC_CAMNOC_AXI_RT_CLK_SRC] = &cam_cc_camnoc_axi_rt_clk_src.clkr,
[CAM_CC_CAMNOC_DCD_XO_CLK] = &cam_cc_camnoc_dcd_xo_clk.clkr,
[CAM_CC_CAMNOC_XO_CLK] = &cam_cc_camnoc_xo_clk.clkr,
[CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr,
[CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr,
[CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr,
[CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr,
[CAM_CC_CCI_2_CLK] = &cam_cc_cci_2_clk.clkr,
[CAM_CC_CCI_2_CLK_SRC] = &cam_cc_cci_2_clk_src.clkr,
[CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr,
[CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr,
[CAM_CC_CPAS_BPS_CLK] = &cam_cc_cpas_bps_clk.clkr,
[CAM_CC_CPAS_CRE_CLK] = &cam_cc_cpas_cre_clk.clkr,
[CAM_CC_CPAS_FAST_AHB_CLK] = &cam_cc_cpas_fast_ahb_clk.clkr,
[CAM_CC_CPAS_IFE_0_CLK] = &cam_cc_cpas_ife_0_clk.clkr,
[CAM_CC_CPAS_IFE_1_CLK] = &cam_cc_cpas_ife_1_clk.clkr,
[CAM_CC_CPAS_IFE_2_CLK] = &cam_cc_cpas_ife_2_clk.clkr,
[CAM_CC_CPAS_IFE_LITE_CLK] = &cam_cc_cpas_ife_lite_clk.clkr,
[CAM_CC_CPAS_IPE_NPS_CLK] = &cam_cc_cpas_ipe_nps_clk.clkr,
[CAM_CC_CPAS_SBI_CLK] = &cam_cc_cpas_sbi_clk.clkr,
[CAM_CC_CPAS_SFE_0_CLK] = &cam_cc_cpas_sfe_0_clk.clkr,
[CAM_CC_CPAS_SFE_1_CLK] = &cam_cc_cpas_sfe_1_clk.clkr,
[CAM_CC_CPAS_SFE_2_CLK] = &cam_cc_cpas_sfe_2_clk.clkr,
[CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr,
[CAM_CC_CRE_AHB_CLK] = &cam_cc_cre_ahb_clk.clkr,
[CAM_CC_CRE_CLK] = &cam_cc_cre_clk.clkr,
[CAM_CC_CRE_CLK_SRC] = &cam_cc_cre_clk_src.clkr,
[CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr,
[CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr,
[CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr,
[CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr,
[CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr,
[CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr,
[CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr,
[CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr,
[CAM_CC_CSI4PHYTIMER_CLK] = &cam_cc_csi4phytimer_clk.clkr,
[CAM_CC_CSI4PHYTIMER_CLK_SRC] = &cam_cc_csi4phytimer_clk_src.clkr,
[CAM_CC_CSI5PHYTIMER_CLK] = &cam_cc_csi5phytimer_clk.clkr,
[CAM_CC_CSI5PHYTIMER_CLK_SRC] = &cam_cc_csi5phytimer_clk_src.clkr,
[CAM_CC_CSI6PHYTIMER_CLK] = &cam_cc_csi6phytimer_clk.clkr,
[CAM_CC_CSI6PHYTIMER_CLK_SRC] = &cam_cc_csi6phytimer_clk_src.clkr,
[CAM_CC_CSI7PHYTIMER_CLK] = &cam_cc_csi7phytimer_clk.clkr,
[CAM_CC_CSI7PHYTIMER_CLK_SRC] = &cam_cc_csi7phytimer_clk_src.clkr,
[CAM_CC_CSID_CLK] = &cam_cc_csid_clk.clkr,
[CAM_CC_CSID_CLK_SRC] = &cam_cc_csid_clk_src.clkr,
[CAM_CC_CSID_CSIPHY_RX_CLK] = &cam_cc_csid_csiphy_rx_clk.clkr,
[CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr,
[CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr,
[CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr,
[CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr,
[CAM_CC_CSIPHY4_CLK] = &cam_cc_csiphy4_clk.clkr,
[CAM_CC_CSIPHY5_CLK] = &cam_cc_csiphy5_clk.clkr,
[CAM_CC_CSIPHY6_CLK] = &cam_cc_csiphy6_clk.clkr,
[CAM_CC_CSIPHY7_CLK] = &cam_cc_csiphy7_clk.clkr,
[CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr,
[CAM_CC_ICP_AHB_CLK] = &cam_cc_icp_ahb_clk.clkr,
[CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr,
[CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr,
[CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr,
[CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr,
[CAM_CC_IFE_0_FAST_AHB_CLK] = &cam_cc_ife_0_fast_ahb_clk.clkr,
[CAM_CC_IFE_0_SHIFT_CLK] = &cam_cc_ife_0_shift_clk.clkr,
[CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr,
[CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr,
[CAM_CC_IFE_1_FAST_AHB_CLK] = &cam_cc_ife_1_fast_ahb_clk.clkr,
[CAM_CC_IFE_1_SHIFT_CLK] = &cam_cc_ife_1_shift_clk.clkr,
[CAM_CC_IFE_2_CLK] = &cam_cc_ife_2_clk.clkr,
[CAM_CC_IFE_2_CLK_SRC] = &cam_cc_ife_2_clk_src.clkr,
[CAM_CC_IFE_2_FAST_AHB_CLK] = &cam_cc_ife_2_fast_ahb_clk.clkr,
[CAM_CC_IFE_2_SHIFT_CLK] = &cam_cc_ife_2_shift_clk.clkr,
[CAM_CC_IFE_LITE_AHB_CLK] = &cam_cc_ife_lite_ahb_clk.clkr,
[CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr,
[CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr,
[CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr,
[CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr,
[CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr,
[CAM_CC_IPE_NPS_AHB_CLK] = &cam_cc_ipe_nps_ahb_clk.clkr,
[CAM_CC_IPE_NPS_CLK] = &cam_cc_ipe_nps_clk.clkr,
[CAM_CC_IPE_NPS_CLK_SRC] = &cam_cc_ipe_nps_clk_src.clkr,
[CAM_CC_IPE_NPS_FAST_AHB_CLK] = &cam_cc_ipe_nps_fast_ahb_clk.clkr,
[CAM_CC_IPE_PPS_CLK] = &cam_cc_ipe_pps_clk.clkr,
[CAM_CC_IPE_PPS_FAST_AHB_CLK] = &cam_cc_ipe_pps_fast_ahb_clk.clkr,
[CAM_CC_IPE_SHIFT_CLK] = &cam_cc_ipe_shift_clk.clkr,
[CAM_CC_JPEG_1_CLK] = &cam_cc_jpeg_1_clk.clkr,
[CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr,
[CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr,
[CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr,
[CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr,
[CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr,
[CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr,
[CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr,
[CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr,
[CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr,
[CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr,
[CAM_CC_MCLK4_CLK] = &cam_cc_mclk4_clk.clkr,
[CAM_CC_MCLK4_CLK_SRC] = &cam_cc_mclk4_clk_src.clkr,
[CAM_CC_MCLK5_CLK] = &cam_cc_mclk5_clk.clkr,
[CAM_CC_MCLK5_CLK_SRC] = &cam_cc_mclk5_clk_src.clkr,
[CAM_CC_MCLK6_CLK] = &cam_cc_mclk6_clk.clkr,
[CAM_CC_MCLK6_CLK_SRC] = &cam_cc_mclk6_clk_src.clkr,
[CAM_CC_MCLK7_CLK] = &cam_cc_mclk7_clk.clkr,
[CAM_CC_MCLK7_CLK_SRC] = &cam_cc_mclk7_clk_src.clkr,
[CAM_CC_PLL0] = &cam_cc_pll0.clkr,
[CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr,
[CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr,
[CAM_CC_PLL1] = &cam_cc_pll1.clkr,
[CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr,
[CAM_CC_PLL2] = &cam_cc_pll2.clkr,
[CAM_CC_PLL3] = &cam_cc_pll3.clkr,
[CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr,
[CAM_CC_PLL4] = &cam_cc_pll4.clkr,
[CAM_CC_PLL4_OUT_EVEN] = &cam_cc_pll4_out_even.clkr,
[CAM_CC_PLL5] = &cam_cc_pll5.clkr,
[CAM_CC_PLL5_OUT_EVEN] = &cam_cc_pll5_out_even.clkr,
[CAM_CC_PLL6] = &cam_cc_pll6.clkr,
[CAM_CC_PLL6_OUT_EVEN] = &cam_cc_pll6_out_even.clkr,
[CAM_CC_PLL7] = &cam_cc_pll7.clkr,
[CAM_CC_PLL7_OUT_EVEN] = &cam_cc_pll7_out_even.clkr,
[CAM_CC_PLL8] = &cam_cc_pll8.clkr,
[CAM_CC_PLL8_OUT_EVEN] = &cam_cc_pll8_out_even.clkr,
[CAM_CC_PLL9] = &cam_cc_pll9.clkr,
[CAM_CC_PLL9_OUT_EVEN] = &cam_cc_pll9_out_even.clkr,
[CAM_CC_PLL9_OUT_ODD] = &cam_cc_pll9_out_odd.clkr,
[CAM_CC_PLL10] = &cam_cc_pll10.clkr,
[CAM_CC_PLL10_OUT_EVEN] = &cam_cc_pll10_out_even.clkr,
[CAM_CC_QDSS_DEBUG_CLK] = &cam_cc_qdss_debug_clk.clkr,
[CAM_CC_QDSS_DEBUG_CLK_SRC] = &cam_cc_qdss_debug_clk_src.clkr,
[CAM_CC_QDSS_DEBUG_XO_CLK] = &cam_cc_qdss_debug_xo_clk.clkr,
[CAM_CC_SBI_CLK] = &cam_cc_sbi_clk.clkr,
[CAM_CC_SBI_FAST_AHB_CLK] = &cam_cc_sbi_fast_ahb_clk.clkr,
[CAM_CC_SBI_SHIFT_CLK] = &cam_cc_sbi_shift_clk.clkr,
[CAM_CC_SFE_0_CLK] = &cam_cc_sfe_0_clk.clkr,
[CAM_CC_SFE_0_CLK_SRC] = &cam_cc_sfe_0_clk_src.clkr,
[CAM_CC_SFE_0_FAST_AHB_CLK] = &cam_cc_sfe_0_fast_ahb_clk.clkr,
[CAM_CC_SFE_0_SHIFT_CLK] = &cam_cc_sfe_0_shift_clk.clkr,
[CAM_CC_SFE_1_CLK] = &cam_cc_sfe_1_clk.clkr,
[CAM_CC_SFE_1_CLK_SRC] = &cam_cc_sfe_1_clk_src.clkr,
[CAM_CC_SFE_1_FAST_AHB_CLK] = &cam_cc_sfe_1_fast_ahb_clk.clkr,
[CAM_CC_SFE_1_SHIFT_CLK] = &cam_cc_sfe_1_shift_clk.clkr,
[CAM_CC_SFE_2_CLK] = &cam_cc_sfe_2_clk.clkr,
[CAM_CC_SFE_2_CLK_SRC] = &cam_cc_sfe_2_clk_src.clkr,
[CAM_CC_SFE_2_FAST_AHB_CLK] = &cam_cc_sfe_2_fast_ahb_clk.clkr,
[CAM_CC_SFE_2_SHIFT_CLK] = &cam_cc_sfe_2_shift_clk.clkr,
[CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr,
[CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr,
[CAM_CC_TITAN_TOP_SHIFT_CLK] = &cam_cc_titan_top_shift_clk.clkr,
[CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr,
};
static struct gdsc *cam_cc_sm8650_gdscs[] = {
[CAM_CC_TITAN_TOP_GDSC] = &cam_cc_titan_top_gdsc,
[CAM_CC_BPS_GDSC] = &cam_cc_bps_gdsc,
[CAM_CC_IFE_0_GDSC] = &cam_cc_ife_0_gdsc,
[CAM_CC_IFE_1_GDSC] = &cam_cc_ife_1_gdsc,
[CAM_CC_IFE_2_GDSC] = &cam_cc_ife_2_gdsc,
[CAM_CC_IPE_0_GDSC] = &cam_cc_ipe_0_gdsc,
[CAM_CC_SBI_GDSC] = &cam_cc_sbi_gdsc,
[CAM_CC_SFE_0_GDSC] = &cam_cc_sfe_0_gdsc,
[CAM_CC_SFE_1_GDSC] = &cam_cc_sfe_1_gdsc,
[CAM_CC_SFE_2_GDSC] = &cam_cc_sfe_2_gdsc,
};
static const struct qcom_reset_map cam_cc_sm8650_resets[] = {
[CAM_CC_BPS_BCR] = { 0x10000 },
[CAM_CC_DRV_BCR] = { 0x13310 },
[CAM_CC_ICP_BCR] = { 0x131a0 },
[CAM_CC_IFE_0_BCR] = { 0x11000 },
[CAM_CC_IFE_1_BCR] = { 0x12000 },
[CAM_CC_IFE_2_BCR] = { 0x12050 },
[CAM_CC_IPE_0_BCR] = { 0x1007c },
[CAM_CC_QDSS_DEBUG_BCR] = { 0x13298 },
[CAM_CC_SBI_BCR] = { 0x100e0 },
[CAM_CC_SFE_0_BCR] = { 0x13054 },
[CAM_CC_SFE_1_BCR] = { 0x130a4 },
[CAM_CC_SFE_2_BCR] = { 0x130f4 },
};
static const struct regmap_config cam_cc_sm8650_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x1603c,
.fast_io = true,
};
static struct qcom_cc_desc cam_cc_sm8650_desc = {
.config = &cam_cc_sm8650_regmap_config,
.clks = cam_cc_sm8650_clocks,
.num_clks = ARRAY_SIZE(cam_cc_sm8650_clocks),
.resets = cam_cc_sm8650_resets,
.num_resets = ARRAY_SIZE(cam_cc_sm8650_resets),
.gdscs = cam_cc_sm8650_gdscs,
.num_gdscs = ARRAY_SIZE(cam_cc_sm8650_gdscs),
};
static const struct of_device_id cam_cc_sm8650_match_table[] = {
{ .compatible = "qcom,sm8650-camcc" },
{ }
};
MODULE_DEVICE_TABLE(of, cam_cc_sm8650_match_table);
static int cam_cc_sm8650_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
ret = devm_pm_runtime_enable(&pdev->dev);
if (ret)
return ret;
ret = pm_runtime_resume_and_get(&pdev->dev);
if (ret)
return ret;
regmap = qcom_cc_map(pdev, &cam_cc_sm8650_desc);
if (IS_ERR(regmap)) {
pm_runtime_put(&pdev->dev);
return PTR_ERR(regmap);
}
clk_lucid_ole_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config);
clk_lucid_ole_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config);
clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config);
clk_lucid_ole_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config);
clk_lucid_ole_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config);
clk_lucid_ole_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config);
clk_lucid_ole_pll_configure(&cam_cc_pll6, regmap, &cam_cc_pll6_config);
clk_lucid_ole_pll_configure(&cam_cc_pll7, regmap, &cam_cc_pll7_config);
clk_lucid_ole_pll_configure(&cam_cc_pll8, regmap, &cam_cc_pll8_config);
clk_lucid_ole_pll_configure(&cam_cc_pll9, regmap, &cam_cc_pll9_config);
clk_lucid_ole_pll_configure(&cam_cc_pll10, regmap, &cam_cc_pll10_config);
/* Keep clocks always enabled */
qcom_branch_set_clk_en(regmap, 0x13318); /* CAM_CC_DRV_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x13314); /* CAM_CC_DRV_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x132ec); /* CAM_CC_GDSC_CLK */
qcom_branch_set_clk_en(regmap, 0x13308); /* CAM_CC_SLEEP_CLK */
ret = qcom_cc_really_probe(&pdev->dev, &cam_cc_sm8650_desc, regmap);
pm_runtime_put(&pdev->dev);
return ret;
}
static struct platform_driver cam_cc_sm8650_driver = {
.probe = cam_cc_sm8650_probe,
.driver = {
.name = "camcc-sm8650",
.of_match_table = cam_cc_sm8650_match_table,
},
};
module_platform_driver(cam_cc_sm8650_driver);
MODULE_DESCRIPTION("QTI CAMCC SM8650 Driver");
MODULE_LICENSE("GPL");
drivers/clk/qcom/videocc-sm8550.c
View file @ e2ebc659
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/clk-provider.h>
......@@ -10,7 +10,7 @@
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,sm8450-videocc.h>
#include <dt-bindings/clock/qcom,sm8650-videocc.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
......@@ -35,7 +35,7 @@ static const struct pll_vco lucid_ole_vco[] = {
{ 249600000, 2300000000, 0 },
};
static const struct alpha_pll_config video_cc_pll0_config = {
static struct alpha_pll_config video_cc_pll0_config = {
.l = 0x25,
.alpha = 0x8000,
.config_ctl_val = 0x20485699,
......@@ -66,7 +66,7 @@ static struct clk_alpha_pll video_cc_pll0 = {
},
};
static const struct alpha_pll_config video_cc_pll1_config = {
static struct alpha_pll_config video_cc_pll1_config = {
.l = 0x36,
.alpha = 0xb000,
.config_ctl_val = 0x20485699,
......@@ -117,6 +117,14 @@ static const struct clk_parent_data video_cc_parent_data_1[] = {
{ .hw = &video_cc_pll1.clkr.hw },
};
static const struct parent_map video_cc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
};
static const struct clk_parent_data video_cc_parent_data_2[] = {
{ .index = DT_BI_TCXO },
};
static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = {
F(720000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
F(1014000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
......@@ -126,6 +134,16 @@ static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = {
{ }
};
static const struct freq_tbl ftbl_video_cc_mvs0_clk_src_sm8650[] = {
F(588000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
F(900000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
F(1140000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
F(1305000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
F(1440000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
F(1600000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
{ }
};
static struct clk_rcg2 video_cc_mvs0_clk_src = {
.cmd_rcgr = 0x8000,
.mnd_width = 0,
......@@ -149,6 +167,15 @@ static const struct freq_tbl ftbl_video_cc_mvs1_clk_src[] = {
{ }
};
static const struct freq_tbl ftbl_video_cc_mvs1_clk_src_sm8650[] = {
F(840000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
F(1110000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
F(1350000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
F(1500000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
F(1650000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
{ }
};
static struct clk_rcg2 video_cc_mvs1_clk_src = {
.cmd_rcgr = 0x8018,
.mnd_width = 0,
......@@ -164,6 +191,26 @@ static struct clk_rcg2 video_cc_mvs1_clk_src = {
},
};
static const struct freq_tbl ftbl_video_cc_xo_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 video_cc_xo_clk_src = {
.cmd_rcgr = 0x810c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = video_cc_parent_map_2,
.freq_tbl = ftbl_video_cc_xo_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "video_cc_xo_clk_src",
.parent_data = video_cc_parent_data_2,
.num_parents = ARRAY_SIZE(video_cc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_regmap_div video_cc_mvs0_div_clk_src = {
.reg = 0x80c4,
.shift = 0,
......@@ -244,6 +291,26 @@ static struct clk_branch video_cc_mvs0_clk = {
},
};
static struct clk_branch video_cc_mvs0_shift_clk = {
.halt_reg = 0x8128,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x8128,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x8128,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0_shift_clk",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvs0c_clk = {
.halt_reg = 0x8064,
.halt_check = BRANCH_HALT,
......@@ -262,6 +329,26 @@ static struct clk_branch video_cc_mvs0c_clk = {
},
};
static struct clk_branch video_cc_mvs0c_shift_clk = {
.halt_reg = 0x812c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x812c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x812c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0c_shift_clk",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvs1_clk = {
.halt_reg = 0x80e0,
.halt_check = BRANCH_HALT_SKIP,
......@@ -282,6 +369,26 @@ static struct clk_branch video_cc_mvs1_clk = {
},
};
static struct clk_branch video_cc_mvs1_shift_clk = {
.halt_reg = 0x8130,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x8130,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x8130,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs1_shift_clk",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvs1c_clk = {
.halt_reg = 0x8090,
.halt_check = BRANCH_HALT,
......@@ -300,6 +407,26 @@ static struct clk_branch video_cc_mvs1c_clk = {
},
};
static struct clk_branch video_cc_mvs1c_shift_clk = {
.halt_reg = 0x8134,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x8134,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x8134,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs1c_shift_clk",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc video_cc_mvs0c_gdsc = {
.gdscr = 0x804c,
.en_rest_wait_val = 0x2,
......@@ -363,6 +490,7 @@ static struct clk_regmap *video_cc_sm8550_clocks[] = {
[VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC] = &video_cc_mvs1c_div2_div_clk_src.clkr,
[VIDEO_CC_PLL0] = &video_cc_pll0.clkr,
[VIDEO_CC_PLL1] = &video_cc_pll1.clkr,
[VIDEO_CC_XO_CLK_SRC] = NULL,
};
static struct gdsc *video_cc_sm8550_gdscs[] = {
......@@ -380,6 +508,7 @@ static const struct qcom_reset_map video_cc_sm8550_resets[] = {
[CVP_VIDEO_CC_MVS1C_BCR] = { 0x8074 },
[VIDEO_CC_MVS0C_CLK_ARES] = { .reg = 0x8064, .bit = 2, .udelay = 1000 },
[VIDEO_CC_MVS1C_CLK_ARES] = { .reg = 0x8090, .bit = 2, .udelay = 1000 },
[VIDEO_CC_XO_CLK_ARES] = { .reg = 0x8124, .bit = 2, .udelay = 100 },
};
static const struct regmap_config video_cc_sm8550_regmap_config = {
......@@ -402,6 +531,7 @@ static struct qcom_cc_desc video_cc_sm8550_desc = {
static const struct of_device_id video_cc_sm8550_match_table[] = {
{ .compatible = "qcom,sm8550-videocc" },
{ .compatible = "qcom,sm8650-videocc" },
{ }
};
MODULE_DEVICE_TABLE(of, video_cc_sm8550_match_table);
......@@ -410,6 +540,7 @@ static int video_cc_sm8550_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
u32 sleep_clk_offset = 0x8140;
ret = devm_pm_runtime_enable(&pdev->dev);
if (ret)
......@@ -425,12 +556,27 @@ static int video_cc_sm8550_probe(struct platform_device *pdev)
return PTR_ERR(regmap);
}
if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8650-videocc")) {
sleep_clk_offset = 0x8150;
video_cc_pll0_config.l = 0x1e;
video_cc_pll0_config.alpha = 0xa000;
video_cc_pll1_config.l = 0x2b;
video_cc_pll1_config.alpha = 0xc000;
video_cc_mvs0_clk_src.freq_tbl = ftbl_video_cc_mvs0_clk_src_sm8650;
video_cc_mvs1_clk_src.freq_tbl = ftbl_video_cc_mvs1_clk_src_sm8650;
video_cc_sm8550_clocks[VIDEO_CC_MVS0_SHIFT_CLK] = &video_cc_mvs0_shift_clk.clkr;
video_cc_sm8550_clocks[VIDEO_CC_MVS0C_SHIFT_CLK] = &video_cc_mvs0c_shift_clk.clkr;
video_cc_sm8550_clocks[VIDEO_CC_MVS1_SHIFT_CLK] = &video_cc_mvs1_shift_clk.clkr;
video_cc_sm8550_clocks[VIDEO_CC_MVS1C_SHIFT_CLK] = &video_cc_mvs1c_shift_clk.clkr;
video_cc_sm8550_clocks[VIDEO_CC_XO_CLK_SRC] = &video_cc_xo_clk_src.clkr;
}
clk_lucid_ole_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config);
clk_lucid_ole_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config);
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x80f4); /* VIDEO_CC_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x8140); /* VIDEO_CC_SLEEP_CLK */
qcom_branch_set_clk_en(regmap, sleep_clk_offset); /* VIDEO_CC_SLEEP_CLK */
qcom_branch_set_clk_en(regmap, 0x8124); /* VIDEO_CC_XO_CLK */
ret = qcom_cc_really_probe(pdev, &video_cc_sm8550_desc, regmap);
......
include/dt-bindings/clock/qcom,sm8650-camcc.h 0 → 100644
View file @ e2ebc659
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8650_H
#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8650_H
/* CAM_CC clocks */
#define CAM_CC_BPS_AHB_CLK 0
#define CAM_CC_BPS_CLK 1
#define CAM_CC_BPS_CLK_SRC 2
#define CAM_CC_BPS_FAST_AHB_CLK 3
#define CAM_CC_BPS_SHIFT_CLK 4
#define CAM_CC_CAMNOC_AXI_NRT_CLK 5
#define CAM_CC_CAMNOC_AXI_RT_CLK 6
#define CAM_CC_CAMNOC_AXI_RT_CLK_SRC 7
#define CAM_CC_CAMNOC_DCD_XO_CLK 8
#define CAM_CC_CAMNOC_XO_CLK 9
#define CAM_CC_CCI_0_CLK 10
#define CAM_CC_CCI_0_CLK_SRC 11
#define CAM_CC_CCI_1_CLK 12
#define CAM_CC_CCI_1_CLK_SRC 13
#define CAM_CC_CCI_2_CLK 14
#define CAM_CC_CCI_2_CLK_SRC 15
#define CAM_CC_CORE_AHB_CLK 16
#define CAM_CC_CPAS_AHB_CLK 17
#define CAM_CC_CPAS_BPS_CLK 18
#define CAM_CC_CPAS_CRE_CLK 19
#define CAM_CC_CPAS_FAST_AHB_CLK 20
#define CAM_CC_CPAS_IFE_0_CLK 21
#define CAM_CC_CPAS_IFE_1_CLK 22
#define CAM_CC_CPAS_IFE_2_CLK 23
#define CAM_CC_CPAS_IFE_LITE_CLK 24
#define CAM_CC_CPAS_IPE_NPS_CLK 25
#define CAM_CC_CPAS_SBI_CLK 26
#define CAM_CC_CPAS_SFE_0_CLK 27
#define CAM_CC_CPAS_SFE_1_CLK 28
#define CAM_CC_CPAS_SFE_2_CLK 29
#define CAM_CC_CPHY_RX_CLK_SRC 30
#define CAM_CC_CRE_AHB_CLK 31
#define CAM_CC_CRE_CLK 32
#define CAM_CC_CRE_CLK_SRC 33
#define CAM_CC_CSI0PHYTIMER_CLK 34
#define CAM_CC_CSI0PHYTIMER_CLK_SRC 35
#define CAM_CC_CSI1PHYTIMER_CLK 36
#define CAM_CC_CSI1PHYTIMER_CLK_SRC 37
#define CAM_CC_CSI2PHYTIMER_CLK 38
#define CAM_CC_CSI2PHYTIMER_CLK_SRC 39
#define CAM_CC_CSI3PHYTIMER_CLK 40
#define CAM_CC_CSI3PHYTIMER_CLK_SRC 41
#define CAM_CC_CSI4PHYTIMER_CLK 42
#define CAM_CC_CSI4PHYTIMER_CLK_SRC 43
#define CAM_CC_CSI5PHYTIMER_CLK 44
#define CAM_CC_CSI5PHYTIMER_CLK_SRC 45
#define CAM_CC_CSI6PHYTIMER_CLK 46
#define CAM_CC_CSI6PHYTIMER_CLK_SRC 47
#define CAM_CC_CSI7PHYTIMER_CLK 48
#define CAM_CC_CSI7PHYTIMER_CLK_SRC 49
#define CAM_CC_CSID_CLK 50
#define CAM_CC_CSID_CLK_SRC 51
#define CAM_CC_CSID_CSIPHY_RX_CLK 52
#define CAM_CC_CSIPHY0_CLK 53
#define CAM_CC_CSIPHY1_CLK 54
#define CAM_CC_CSIPHY2_CLK 55
#define CAM_CC_CSIPHY3_CLK 56
#define CAM_CC_CSIPHY4_CLK 57
#define CAM_CC_CSIPHY5_CLK 58
#define CAM_CC_CSIPHY6_CLK 59
#define CAM_CC_CSIPHY7_CLK 60
#define CAM_CC_DRV_AHB_CLK 61
#define CAM_CC_DRV_XO_CLK 62
#define CAM_CC_FAST_AHB_CLK_SRC 63
#define CAM_CC_GDSC_CLK 64
#define CAM_CC_ICP_AHB_CLK 65
#define CAM_CC_ICP_CLK 66
#define CAM_CC_ICP_CLK_SRC 67
#define CAM_CC_IFE_0_CLK 68
#define CAM_CC_IFE_0_CLK_SRC 69
#define CAM_CC_IFE_0_FAST_AHB_CLK 70
#define CAM_CC_IFE_0_SHIFT_CLK 71
#define CAM_CC_IFE_1_CLK 72
#define CAM_CC_IFE_1_CLK_SRC 73
#define CAM_CC_IFE_1_FAST_AHB_CLK 74
#define CAM_CC_IFE_1_SHIFT_CLK 75
#define CAM_CC_IFE_2_CLK 76
#define CAM_CC_IFE_2_CLK_SRC 77
#define CAM_CC_IFE_2_FAST_AHB_CLK 78
#define CAM_CC_IFE_2_SHIFT_CLK 79
#define CAM_CC_IFE_LITE_AHB_CLK 80
#define CAM_CC_IFE_LITE_CLK 81
#define CAM_CC_IFE_LITE_CLK_SRC 82
#define CAM_CC_IFE_LITE_CPHY_RX_CLK 83
#define CAM_CC_IFE_LITE_CSID_CLK 84
#define CAM_CC_IFE_LITE_CSID_CLK_SRC 85
#define CAM_CC_IPE_NPS_AHB_CLK 86
#define CAM_CC_IPE_NPS_CLK 87
#define CAM_CC_IPE_NPS_CLK_SRC 88
#define CAM_CC_IPE_NPS_FAST_AHB_CLK 89
#define CAM_CC_IPE_PPS_CLK 90
#define CAM_CC_IPE_PPS_FAST_AHB_CLK 91
#define CAM_CC_IPE_SHIFT_CLK 92
#define CAM_CC_JPEG_1_CLK 93
#define CAM_CC_JPEG_CLK 94
#define CAM_CC_JPEG_CLK_SRC 95
#define CAM_CC_MCLK0_CLK 96
#define CAM_CC_MCLK0_CLK_SRC 97
#define CAM_CC_MCLK1_CLK 98
#define CAM_CC_MCLK1_CLK_SRC 99
#define CAM_CC_MCLK2_CLK 100
#define CAM_CC_MCLK2_CLK_SRC 101
#define CAM_CC_MCLK3_CLK 102
#define CAM_CC_MCLK3_CLK_SRC 103
#define CAM_CC_MCLK4_CLK 104
#define CAM_CC_MCLK4_CLK_SRC 105
#define CAM_CC_MCLK5_CLK 106
#define CAM_CC_MCLK5_CLK_SRC 107
#define CAM_CC_MCLK6_CLK 108
#define CAM_CC_MCLK6_CLK_SRC 109
#define CAM_CC_MCLK7_CLK 110
#define CAM_CC_MCLK7_CLK_SRC 111
#define CAM_CC_PLL0 112
#define CAM_CC_PLL0_OUT_EVEN 113
#define CAM_CC_PLL0_OUT_ODD 114
#define CAM_CC_PLL1 115
#define CAM_CC_PLL1_OUT_EVEN 116
#define CAM_CC_PLL2 117
#define CAM_CC_PLL3 118
#define CAM_CC_PLL3_OUT_EVEN 119
#define CAM_CC_PLL4 120
#define CAM_CC_PLL4_OUT_EVEN 121
#define CAM_CC_PLL5 122
#define CAM_CC_PLL5_OUT_EVEN 123
#define CAM_CC_PLL6 124
#define CAM_CC_PLL6_OUT_EVEN 125
#define CAM_CC_PLL7 126
#define CAM_CC_PLL7_OUT_EVEN 127
#define CAM_CC_PLL8 128
#define CAM_CC_PLL8_OUT_EVEN 129
#define CAM_CC_PLL9 130
#define CAM_CC_PLL9_OUT_EVEN 131
#define CAM_CC_PLL9_OUT_ODD 132
#define CAM_CC_PLL10 133
#define CAM_CC_PLL10_OUT_EVEN 134
#define CAM_CC_QDSS_DEBUG_CLK 135
#define CAM_CC_QDSS_DEBUG_CLK_SRC 136
#define CAM_CC_QDSS_DEBUG_XO_CLK 137
#define CAM_CC_SBI_CLK 138
#define CAM_CC_SBI_FAST_AHB_CLK 139
#define CAM_CC_SBI_SHIFT_CLK 140
#define CAM_CC_SFE_0_CLK 141
#define CAM_CC_SFE_0_CLK_SRC 142
#define CAM_CC_SFE_0_FAST_AHB_CLK 143
#define CAM_CC_SFE_0_SHIFT_CLK 144
#define CAM_CC_SFE_1_CLK 145
#define CAM_CC_SFE_1_CLK_SRC 146
#define CAM_CC_SFE_1_FAST_AHB_CLK 147
#define CAM_CC_SFE_1_SHIFT_CLK 148
#define CAM_CC_SFE_2_CLK 149
#define CAM_CC_SFE_2_CLK_SRC 150
#define CAM_CC_SFE_2_FAST_AHB_CLK 151
#define CAM_CC_SFE_2_SHIFT_CLK 152
#define CAM_CC_SLEEP_CLK 153
#define CAM_CC_SLEEP_CLK_SRC 154
#define CAM_CC_SLOW_AHB_CLK_SRC 155
#define CAM_CC_TITAN_TOP_SHIFT_CLK 156
#define CAM_CC_XO_CLK_SRC 157
/* CAM_CC power domains */
#define CAM_CC_TITAN_TOP_GDSC 0
#define CAM_CC_BPS_GDSC 1
#define CAM_CC_IFE_0_GDSC 2
#define CAM_CC_IFE_1_GDSC 3
#define CAM_CC_IFE_2_GDSC 4
#define CAM_CC_IPE_0_GDSC 5
#define CAM_CC_SBI_GDSC 6
#define CAM_CC_SFE_0_GDSC 7
#define CAM_CC_SFE_1_GDSC 8
#define CAM_CC_SFE_2_GDSC 9
/* CAM_CC resets */
#define CAM_CC_BPS_BCR 0
#define CAM_CC_DRV_BCR 1
#define CAM_CC_ICP_BCR 2
#define CAM_CC_IFE_0_BCR 3
#define CAM_CC_IFE_1_BCR 4
#define CAM_CC_IFE_2_BCR 5
#define CAM_CC_IPE_0_BCR 6
#define CAM_CC_QDSS_DEBUG_BCR 7
#define CAM_CC_SBI_BCR 8
#define CAM_CC_SFE_0_BCR 9
#define CAM_CC_SFE_1_BCR 10
#define CAM_CC_SFE_2_BCR 11
#endif
include/dt-bindings/clock/qcom,sm8650-videocc.h 0 → 100644
View file @ e2ebc659
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8650_H
#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8650_H
#include "qcom,sm8450-videocc.h"
/* SM8650 introduces below new clocks and resets compared to SM8450 */
/* VIDEO_CC clocks */
#define VIDEO_CC_MVS0_SHIFT_CLK 12
#define VIDEO_CC_MVS0C_SHIFT_CLK 13
#define VIDEO_CC_MVS1_SHIFT_CLK 14
#define VIDEO_CC_MVS1C_SHIFT_CLK 15
#define VIDEO_CC_XO_CLK_SRC 16
/* VIDEO_CC resets */
#define VIDEO_CC_XO_CLK_ARES 7
#endif
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