Commit e6508c7e authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman

Merge tag 'phy-for-5.4' of...

Merge tag 'phy-for-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into char-misc-next

Kishon writes:

phy: for 5.4

  *) Add a new PHY driver for Lantiq VRX200/ARX300 PCIe PHY
  *) Add missing of_node_put() to a bunch of drivers using
     for_each_available_child_of_node()
  *) Add RXAUI/PCIe/SATA/USB3 support in Marvell's Armada
     CP110 COMPHY
  *) Other misc fixes and cleanup
Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>

* tag 'phy-for-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy: (30 commits)
  phy: marvell: phy-mvebu-cp110-comphy: rename instances of DLT
  phy: marvell: phy-mvebu-cp110-comphy: implement RXAUI support
  dt-bindings: pci: add PHY properties to Armada 7K/8K controller bindings
  dt-bindings: phy: Add Marvell COMPHY clocks
  phy: mvebu-cp110-comphy: Update comment about powering off all lanes at boot
  phy: mvebu-cp110-comphy: Add PCIe support
  phy: mvebu-cp110-comphy: Cosmetic change in a helper
  phy: mvebu-cp110-comphy: Add SATA support
  phy: mvebu-cp110-comphy: Add USB3 host/device support
  phy: mvebu-cp110-comphy: Allow non-Ethernet modes to be configured
  phy: mvebu-cp110-comphy: Rename the macro handling only Ethernet modes
  phy: mvebu-cp110-comphy: Add RXAUI support
  phy: mvebu-cp110-comphy: List already supported Ethernet modes
  phy: mvebu-cp110-comphy: Add SMC call support
  phy: mvebu-cp110-comphy: Explicitly initialize the lane submode
  phy: mvebu-cp110-comphy: Add clocks support
  phy-rockchip-inno-hdmi: Fix RK3328_TERM_RESISTOR_CALIB_SPEED_7_0's third value
  phy: qcom-qmp: Correct ready status, again
  phy: qualcomm: phy-qcom-qmp: Add of_node_put() before return
  phy: renesas: rcar-gen3-usb2: Disable clearing VBUS in over-current
  ...
parents 4a79ce74 5af67635
...@@ -17,6 +17,14 @@ Required properties: ...@@ -17,6 +17,14 @@ Required properties:
name must be "core" for the first clock and "reg" for the second name must be "core" for the first clock and "reg" for the second
one one
Optional properties:
- phys: phandle(s) to PHY node(s) following the generic PHY bindings.
Either 1, 2 or 4 PHYs might be needed depending on the number of
PCIe lanes.
- phy-names: names of the PHYs corresponding to the number of lanes.
Must be "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy" for
2 PHYs.
Example: Example:
pcie@f2600000 { pcie@f2600000 {
......
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/lantiq,vrx200-pcie-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Lantiq VRX200 and ARX300 PCIe PHY Device Tree Bindings
maintainers:
- Martin Blumenstingl <martin.blumenstingl@googlemail.com>
properties:
"#phy-cells":
const: 1
description: selects the PHY mode as defined in <dt-bindings/phy/phy-lantiq-vrx200-pcie.h>
compatible:
enum:
- lantiq,vrx200-pcie-phy
- lantiq,arx300-pcie-phy
reg:
maxItems: 1
clocks:
items:
- description: PHY module clock
- description: PDI register clock
clock-names:
items:
- const: phy
- const: pdi
resets:
items:
- description: exclusive PHY reset line
- description: shared reset line between the PCIe PHY and PCIe controller
resets-names:
items:
- const: phy
- const: pcie
lantiq,rcu:
$ref: /schemas/types.yaml#/definitions/phandle
description: phandle to the RCU syscon
lantiq,rcu-endian-offset:
$ref: /schemas/types.yaml#/definitions/uint32
description: the offset of the endian registers for this PHY instance in the RCU syscon
lantiq,rcu-big-endian-mask:
$ref: /schemas/types.yaml#/definitions/uint32
description: the mask to set the PDI (PHY) registers for this PHY instance to big endian
big-endian:
description: Configures the PDI (PHY) registers in big-endian mode
type: boolean
little-endian:
description: Configures the PDI (PHY) registers in big-endian mode
type: boolean
required:
- "#phy-cells"
- compatible
- reg
- clocks
- clock-names
- resets
- reset-names
- lantiq,rcu
- lantiq,rcu-endian-offset
- lantiq,rcu-big-endian-mask
additionalProperties: false
examples:
- |
pcie0_phy: phy@106800 {
compatible = "lantiq,vrx200-pcie-phy";
reg = <0x106800 0x100>;
lantiq,rcu = <&rcu0>;
lantiq,rcu-endian-offset = <0x4c>;
lantiq,rcu-big-endian-mask = <0x80>; /* bit 7 */
big-endian;
clocks = <&pmu 32>, <&pmu 36>;
clock-names = "phy", "pdi";
resets = <&reset0 12 24>, <&reset0 22 22>;
reset-names = "phy", "pcie";
#phy-cells = <1>;
};
...
...@@ -25,6 +25,13 @@ Required properties: ...@@ -25,6 +25,13 @@ Required properties:
- #address-cells: should be 1. - #address-cells: should be 1.
- #size-cells: should be 0. - #size-cells: should be 0.
Optional properlties:
- clocks: pointers to the reference clocks for this device (CP110 only),
consequently: MG clock, MG Core clock, AXI clock.
- clock-names: names of used clocks for CP110 only, must be :
"mg_clk", "mg_core_clk" and "axi_clk".
A sub-node is required for each comphy lane provided by the comphy. A sub-node is required for each comphy lane provided by the comphy.
Required properties (child nodes): Required properties (child nodes):
...@@ -39,6 +46,9 @@ Examples: ...@@ -39,6 +46,9 @@ Examples:
compatible = "marvell,comphy-cp110"; compatible = "marvell,comphy-cp110";
reg = <0x120000 0x6000>; reg = <0x120000 0x6000>;
marvell,system-controller = <&cpm_syscon0>; marvell,system-controller = <&cpm_syscon0>;
clocks = <&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 6>,
<&CP110_LABEL(clk) 1 18>;
clock-names = "mg_clk", "mg_core_clk", "axi_clk";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
......
...@@ -10,7 +10,6 @@ obj-$(CONFIG_PHY_XGENE) += phy-xgene.o ...@@ -10,7 +10,6 @@ obj-$(CONFIG_PHY_XGENE) += phy-xgene.o
obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o
obj-$(CONFIG_ARCH_SUNXI) += allwinner/ obj-$(CONFIG_ARCH_SUNXI) += allwinner/
obj-$(CONFIG_ARCH_MESON) += amlogic/ obj-$(CONFIG_ARCH_MESON) += amlogic/
obj-$(CONFIG_LANTIQ) += lantiq/
obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/ obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
obj-$(CONFIG_ARCH_RENESAS) += renesas/ obj-$(CONFIG_ARCH_RENESAS) += renesas/
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
...@@ -19,6 +18,7 @@ obj-y += broadcom/ \ ...@@ -19,6 +18,7 @@ obj-y += broadcom/ \
cadence/ \ cadence/ \
freescale/ \ freescale/ \
hisilicon/ \ hisilicon/ \
lantiq/ \
marvell/ \ marvell/ \
motorola/ \ motorola/ \
mscc/ \ mscc/ \
......
...@@ -2,6 +2,17 @@ ...@@ -2,6 +2,17 @@
# #
# Phy drivers for Lantiq / Intel platforms # Phy drivers for Lantiq / Intel platforms
# #
config PHY_LANTIQ_VRX200_PCIE
tristate "Lantiq VRX200/ARX300 PCIe PHY"
depends on SOC_TYPE_XWAY || COMPILE_TEST
depends on OF && HAS_IOMEM
select GENERIC_PHY
select REGMAP_MMIO
help
Support for the PCIe PHY(s) on the Lantiq / Intel VRX200 and ARX300
family SoCs.
If unsure, say N.
config PHY_LANTIQ_RCU_USB2 config PHY_LANTIQ_RCU_USB2
tristate "Lantiq XWAY SoC RCU based USB PHY" tristate "Lantiq XWAY SoC RCU based USB PHY"
depends on OF && (SOC_TYPE_XWAY || COMPILE_TEST) depends on OF && (SOC_TYPE_XWAY || COMPILE_TEST)
......
# SPDX-License-Identifier: GPL-2.0-only # SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_PHY_LANTIQ_RCU_USB2) += phy-lantiq-rcu-usb2.o obj-$(CONFIG_PHY_LANTIQ_RCU_USB2) += phy-lantiq-rcu-usb2.o
obj-$(CONFIG_PHY_LANTIQ_VRX200_PCIE) += phy-lantiq-vrx200-pcie.o
This diff is collapsed.
...@@ -57,6 +57,7 @@ config PHY_MVEBU_CP110_COMPHY ...@@ -57,6 +57,7 @@ config PHY_MVEBU_CP110_COMPHY
tristate "Marvell CP110 comphy driver" tristate "Marvell CP110 comphy driver"
depends on ARCH_MVEBU || COMPILE_TEST depends on ARCH_MVEBU || COMPILE_TEST
depends on OF depends on OF
depends on HAVE_ARM_SMCCC
select GENERIC_PHY select GENERIC_PHY
help help
This driver allows to control the comphy, an hardware block providing This driver allows to control the comphy, an hardware block providing
......
...@@ -200,8 +200,10 @@ static int a38x_comphy_probe(struct platform_device *pdev) ...@@ -200,8 +200,10 @@ static int a38x_comphy_probe(struct platform_device *pdev)
} }
phy = devm_phy_create(&pdev->dev, child, &a38x_comphy_ops); phy = devm_phy_create(&pdev->dev, child, &a38x_comphy_ops);
if (IS_ERR(phy)) if (IS_ERR(phy)) {
of_node_put(child);
return PTR_ERR(phy); return PTR_ERR(phy);
}
priv->lane[val].base = base + 0x28 * val; priv->lane[val].base = base + 0x28 * val;
priv->lane[val].priv = priv; priv->lane[val].priv = priv;
......
...@@ -26,6 +26,7 @@ ...@@ -26,6 +26,7 @@
#define COMPHY_SIP_POWER_ON 0x82000001 #define COMPHY_SIP_POWER_ON 0x82000001
#define COMPHY_SIP_POWER_OFF 0x82000002 #define COMPHY_SIP_POWER_OFF 0x82000002
#define COMPHY_SIP_PLL_LOCK 0x82000003 #define COMPHY_SIP_PLL_LOCK 0x82000003
#define COMPHY_FW_NOT_SUPPORTED (-1)
#define COMPHY_FW_MODE_SATA 0x1 #define COMPHY_FW_MODE_SATA 0x1
#define COMPHY_FW_MODE_SGMII 0x2 #define COMPHY_FW_MODE_SGMII 0x2
...@@ -169,6 +170,7 @@ static int mvebu_a3700_comphy_power_on(struct phy *phy) ...@@ -169,6 +170,7 @@ static int mvebu_a3700_comphy_power_on(struct phy *phy)
struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy); struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy);
u32 fw_param; u32 fw_param;
int fw_mode; int fw_mode;
int ret;
fw_mode = mvebu_a3700_comphy_get_fw_mode(lane->id, lane->port, fw_mode = mvebu_a3700_comphy_get_fw_mode(lane->id, lane->port,
lane->mode, lane->submode); lane->mode, lane->submode);
...@@ -217,7 +219,12 @@ static int mvebu_a3700_comphy_power_on(struct phy *phy) ...@@ -217,7 +219,12 @@ static int mvebu_a3700_comphy_power_on(struct phy *phy)
return -ENOTSUPP; return -ENOTSUPP;
} }
return mvebu_a3700_comphy_smc(COMPHY_SIP_POWER_ON, lane->id, fw_param); ret = mvebu_a3700_comphy_smc(COMPHY_SIP_POWER_ON, lane->id, fw_param);
if (ret == COMPHY_FW_NOT_SUPPORTED)
dev_err(lane->dev,
"unsupported SMC call, try updating your firmware\n");
return ret;
} }
static int mvebu_a3700_comphy_power_off(struct phy *phy) static int mvebu_a3700_comphy_power_off(struct phy *phy)
...@@ -277,13 +284,17 @@ static int mvebu_a3700_comphy_probe(struct platform_device *pdev) ...@@ -277,13 +284,17 @@ static int mvebu_a3700_comphy_probe(struct platform_device *pdev)
} }
lane = devm_kzalloc(&pdev->dev, sizeof(*lane), GFP_KERNEL); lane = devm_kzalloc(&pdev->dev, sizeof(*lane), GFP_KERNEL);
if (!lane) if (!lane) {
of_node_put(child);
return -ENOMEM; return -ENOMEM;
}
phy = devm_phy_create(&pdev->dev, child, phy = devm_phy_create(&pdev->dev, child,
&mvebu_a3700_comphy_ops); &mvebu_a3700_comphy_ops);
if (IS_ERR(phy)) if (IS_ERR(phy)) {
of_node_put(child);
return PTR_ERR(phy); return PTR_ERR(phy);
}
lane->dev = &pdev->dev; lane->dev = &pdev->dev;
lane->mode = PHY_MODE_INVALID; lane->mode = PHY_MODE_INVALID;
......
...@@ -394,6 +394,16 @@ int phy_reset(struct phy *phy) ...@@ -394,6 +394,16 @@ int phy_reset(struct phy *phy)
} }
EXPORT_SYMBOL_GPL(phy_reset); EXPORT_SYMBOL_GPL(phy_reset);
/**
* phy_calibrate() - Tunes the phy hw parameters for current configuration
* @phy: the phy returned by phy_get()
*
* Used to calibrate phy hardware, typically by adjusting some parameters in
* runtime, which are otherwise lost after host controller reset and cannot
* be applied in phy_init() or phy_power_on().
*
* Returns: 0 if successful, an negative error code otherwise
*/
int phy_calibrate(struct phy *phy) int phy_calibrate(struct phy *phy)
{ {
int ret; int ret;
......
...@@ -35,7 +35,7 @@ ...@@ -35,7 +35,7 @@
#define PLL_READY_GATE_EN BIT(3) #define PLL_READY_GATE_EN BIT(3)
/* QPHY_PCS_STATUS bit */ /* QPHY_PCS_STATUS bit */
#define PHYSTATUS BIT(6) #define PHYSTATUS BIT(6)
/* QPHY_COM_PCS_READY_STATUS bit */ /* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */
#define PCS_READY BIT(0) #define PCS_READY BIT(0)
/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */ /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
...@@ -115,6 +115,7 @@ enum qphy_reg_layout { ...@@ -115,6 +115,7 @@ enum qphy_reg_layout {
QPHY_SW_RESET, QPHY_SW_RESET,
QPHY_START_CTRL, QPHY_START_CTRL,
QPHY_PCS_READY_STATUS, QPHY_PCS_READY_STATUS,
QPHY_PCS_STATUS,
QPHY_PCS_AUTONOMOUS_MODE_CTRL, QPHY_PCS_AUTONOMOUS_MODE_CTRL,
QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
QPHY_PCS_LFPS_RXTERM_IRQ_STATUS, QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
...@@ -133,7 +134,7 @@ static const unsigned int pciephy_regs_layout[] = { ...@@ -133,7 +134,7 @@ static const unsigned int pciephy_regs_layout[] = {
[QPHY_FLL_MAN_CODE] = 0xd4, [QPHY_FLL_MAN_CODE] = 0xd4,
[QPHY_SW_RESET] = 0x00, [QPHY_SW_RESET] = 0x00,
[QPHY_START_CTRL] = 0x08, [QPHY_START_CTRL] = 0x08,
[QPHY_PCS_READY_STATUS] = 0x174, [QPHY_PCS_STATUS] = 0x174,
}; };
static const unsigned int usb3phy_regs_layout[] = { static const unsigned int usb3phy_regs_layout[] = {
...@@ -144,7 +145,7 @@ static const unsigned int usb3phy_regs_layout[] = { ...@@ -144,7 +145,7 @@ static const unsigned int usb3phy_regs_layout[] = {
[QPHY_FLL_MAN_CODE] = 0xd0, [QPHY_FLL_MAN_CODE] = 0xd0,
[QPHY_SW_RESET] = 0x00, [QPHY_SW_RESET] = 0x00,
[QPHY_START_CTRL] = 0x08, [QPHY_START_CTRL] = 0x08,
[QPHY_PCS_READY_STATUS] = 0x17c, [QPHY_PCS_STATUS] = 0x17c,
[QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4, [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8, [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8,
[QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178, [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
...@@ -153,7 +154,7 @@ static const unsigned int usb3phy_regs_layout[] = { ...@@ -153,7 +154,7 @@ static const unsigned int usb3phy_regs_layout[] = {
static const unsigned int qmp_v3_usb3phy_regs_layout[] = { static const unsigned int qmp_v3_usb3phy_regs_layout[] = {
[QPHY_SW_RESET] = 0x00, [QPHY_SW_RESET] = 0x00,
[QPHY_START_CTRL] = 0x08, [QPHY_START_CTRL] = 0x08,
[QPHY_PCS_READY_STATUS] = 0x174, [QPHY_PCS_STATUS] = 0x174,
[QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8, [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc, [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc,
[QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170, [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
...@@ -911,7 +912,6 @@ struct qmp_phy_cfg { ...@@ -911,7 +912,6 @@ struct qmp_phy_cfg {
unsigned int start_ctrl; unsigned int start_ctrl;
unsigned int pwrdn_ctrl; unsigned int pwrdn_ctrl;
unsigned int mask_pcs_ready;
unsigned int mask_com_pcs_ready; unsigned int mask_com_pcs_ready;
/* true, if PHY has a separate PHY_COM control block */ /* true, if PHY has a separate PHY_COM control block */
...@@ -1074,7 +1074,6 @@ static const struct qmp_phy_cfg msm8996_pciephy_cfg = { ...@@ -1074,7 +1074,6 @@ static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
.start_ctrl = PCS_START | PLL_READY_GATE_EN, .start_ctrl = PCS_START | PLL_READY_GATE_EN,
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
.mask_pcs_ready = PHYSTATUS,
.mask_com_pcs_ready = PCS_READY, .mask_com_pcs_ready = PCS_READY,
.has_phy_com_ctrl = true, .has_phy_com_ctrl = true,
...@@ -1106,7 +1105,6 @@ static const struct qmp_phy_cfg msm8996_usb3phy_cfg = { ...@@ -1106,7 +1105,6 @@ static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
.start_ctrl = SERDES_START | PCS_START, .start_ctrl = SERDES_START | PCS_START,
.pwrdn_ctrl = SW_PWRDN, .pwrdn_ctrl = SW_PWRDN,
.mask_pcs_ready = PHYSTATUS,
}; };
/* list of resets */ /* list of resets */
...@@ -1136,7 +1134,6 @@ static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { ...@@ -1136,7 +1134,6 @@ static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
.start_ctrl = SERDES_START | PCS_START, .start_ctrl = SERDES_START | PCS_START,
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
.mask_pcs_ready = PHYSTATUS,
.has_phy_com_ctrl = false, .has_phy_com_ctrl = false,
.has_lane_rst = false, .has_lane_rst = false,
...@@ -1167,7 +1164,6 @@ static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = { ...@@ -1167,7 +1164,6 @@ static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
.start_ctrl = SERDES_START | PCS_START, .start_ctrl = SERDES_START | PCS_START,
.pwrdn_ctrl = SW_PWRDN, .pwrdn_ctrl = SW_PWRDN,
.mask_pcs_ready = PHYSTATUS,
.has_pwrdn_delay = true, .has_pwrdn_delay = true,
.pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
...@@ -1199,7 +1195,6 @@ static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = { ...@@ -1199,7 +1195,6 @@ static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
.start_ctrl = SERDES_START | PCS_START, .start_ctrl = SERDES_START | PCS_START,
.pwrdn_ctrl = SW_PWRDN, .pwrdn_ctrl = SW_PWRDN,
.mask_pcs_ready = PHYSTATUS,
.has_pwrdn_delay = true, .has_pwrdn_delay = true,
.pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
...@@ -1226,7 +1221,6 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = { ...@@ -1226,7 +1221,6 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
.start_ctrl = SERDES_START, .start_ctrl = SERDES_START,
.pwrdn_ctrl = SW_PWRDN, .pwrdn_ctrl = SW_PWRDN,
.mask_pcs_ready = PCS_READY,
.is_dual_lane_phy = true, .is_dual_lane_phy = true,
.no_pcs_sw_reset = true, .no_pcs_sw_reset = true,
...@@ -1254,7 +1248,6 @@ static const struct qmp_phy_cfg msm8998_pciephy_cfg = { ...@@ -1254,7 +1248,6 @@ static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
.start_ctrl = SERDES_START | PCS_START, .start_ctrl = SERDES_START | PCS_START,
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
.mask_pcs_ready = PHYSTATUS,
}; };
static const struct qmp_phy_cfg msm8998_usb3phy_cfg = { static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
...@@ -1279,7 +1272,6 @@ static const struct qmp_phy_cfg msm8998_usb3phy_cfg = { ...@@ -1279,7 +1272,6 @@ static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
.start_ctrl = SERDES_START | PCS_START, .start_ctrl = SERDES_START | PCS_START,
.pwrdn_ctrl = SW_PWRDN, .pwrdn_ctrl = SW_PWRDN,
.mask_pcs_ready = PHYSTATUS,
.is_dual_lane_phy = true, .is_dual_lane_phy = true,
}; };
...@@ -1457,7 +1449,7 @@ static int qcom_qmp_phy_enable(struct phy *phy) ...@@ -1457,7 +1449,7 @@ static int qcom_qmp_phy_enable(struct phy *phy)
void __iomem *pcs = qphy->pcs; void __iomem *pcs = qphy->pcs;
void __iomem *dp_com = qmp->dp_com; void __iomem *dp_com = qmp->dp_com;
void __iomem *status; void __iomem *status;
unsigned int mask, val; unsigned int mask, val, ready;
int ret; int ret;
dev_vdbg(qmp->dev, "Initializing QMP phy\n"); dev_vdbg(qmp->dev, "Initializing QMP phy\n");
...@@ -1545,10 +1537,17 @@ static int qcom_qmp_phy_enable(struct phy *phy) ...@@ -1545,10 +1537,17 @@ static int qcom_qmp_phy_enable(struct phy *phy)
/* start SerDes and Phy-Coding-Sublayer */ /* start SerDes and Phy-Coding-Sublayer */
qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
if (cfg->type == PHY_TYPE_UFS) {
status = pcs + cfg->regs[QPHY_PCS_READY_STATUS]; status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
mask = cfg->mask_pcs_ready; mask = PCS_READY;
ready = PCS_READY;
} else {
status = pcs + cfg->regs[QPHY_PCS_STATUS];
mask = PHYSTATUS;
ready = 0;
}
ret = readl_poll_timeout(status, val, val & mask, 10, ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
PHY_INIT_COMPLETE_TIMEOUT); PHY_INIT_COMPLETE_TIMEOUT);
if (ret) { if (ret) {
dev_err(qmp->dev, "phy initialization timed-out\n"); dev_err(qmp->dev, "phy initialization timed-out\n");
...@@ -2093,8 +2092,7 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) ...@@ -2093,8 +2092,7 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
if (ret) { if (ret) {
dev_err(dev, "failed to create lane%d phy, %d\n", dev_err(dev, "failed to create lane%d phy, %d\n",
id, ret); id, ret);
pm_runtime_disable(dev); goto err_node_put;
return ret;
} }
/* /*
...@@ -2105,8 +2103,7 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) ...@@ -2105,8 +2103,7 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
if (ret) { if (ret) {
dev_err(qmp->dev, dev_err(qmp->dev,
"failed to register pipe clock source\n"); "failed to register pipe clock source\n");
pm_runtime_disable(dev); goto err_node_put;
return ret;
} }
id++; id++;
} }
...@@ -2118,6 +2115,11 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) ...@@ -2118,6 +2115,11 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
pm_runtime_disable(dev); pm_runtime_disable(dev);
return PTR_ERR_OR_ZERO(phy_provider); return PTR_ERR_OR_ZERO(phy_provider);
err_node_put:
pm_runtime_disable(dev);
of_node_put(child);
return ret;
} }
static struct platform_driver qcom_qmp_phy_driver = { static struct platform_driver qcom_qmp_phy_driver = {
......
...@@ -61,6 +61,7 @@ ...@@ -61,6 +61,7 @@
USB2_OBINT_IDDIGCHG) USB2_OBINT_IDDIGCHG)
/* VBCTRL */ /* VBCTRL */
#define USB2_VBCTRL_OCCLREN BIT(16)
#define USB2_VBCTRL_DRVVBUSSEL BIT(8) #define USB2_VBCTRL_DRVVBUSSEL BIT(8)
/* LINECTRL1 */ /* LINECTRL1 */
...@@ -374,6 +375,7 @@ static void rcar_gen3_init_otg(struct rcar_gen3_chan *ch) ...@@ -374,6 +375,7 @@ static void rcar_gen3_init_otg(struct rcar_gen3_chan *ch)
writel(val, usb2_base + USB2_LINECTRL1); writel(val, usb2_base + USB2_LINECTRL1);
val = readl(usb2_base + USB2_VBCTRL); val = readl(usb2_base + USB2_VBCTRL);
val &= ~USB2_VBCTRL_OCCLREN;
writel(val | USB2_VBCTRL_DRVVBUSSEL, usb2_base + USB2_VBCTRL); writel(val | USB2_VBCTRL_DRVVBUSSEL, usb2_base + USB2_VBCTRL);
val = readl(usb2_base + USB2_ADPCTRL); val = readl(usb2_base + USB2_ADPCTRL);
writel(val | USB2_ADPCTRL_IDPULLUP, usb2_base + USB2_ADPCTRL); writel(val | USB2_ADPCTRL_IDPULLUP, usb2_base + USB2_ADPCTRL);
......
...@@ -198,7 +198,7 @@ ...@@ -198,7 +198,7 @@
#define RK3328_BYPASS_TERM_RESISTOR_CALIB BIT(7) #define RK3328_BYPASS_TERM_RESISTOR_CALIB BIT(7)
#define RK3328_TERM_RESISTOR_CALIB_SPEED_14_8(x) UPDATE((x) >> 8, 6, 0) #define RK3328_TERM_RESISTOR_CALIB_SPEED_14_8(x) UPDATE((x) >> 8, 6, 0)
/* REG:0xc6 */ /* REG:0xc6 */
#define RK3328_TERM_RESISTOR_CALIB_SPEED_7_0(x) UPDATE(x, 7, 9) #define RK3328_TERM_RESISTOR_CALIB_SPEED_7_0(x) UPDATE(x, 7, 0)
/* REG:0xc7 */ /* REG:0xc7 */
#define RK3328_TERM_RESISTOR_50 UPDATE(0, 2, 1) #define RK3328_TERM_RESISTOR_50 UPDATE(0, 2, 1)
#define RK3328_TERM_RESISTOR_62_5 UPDATE(1, 2, 1) #define RK3328_TERM_RESISTOR_62_5 UPDATE(1, 2, 1)
......
...@@ -109,6 +109,7 @@ static struct platform_driver exynos_dp_video_phy_driver = { ...@@ -109,6 +109,7 @@ static struct platform_driver exynos_dp_video_phy_driver = {
.driver = { .driver = {
.name = "exynos-dp-video-phy", .name = "exynos-dp-video-phy",
.of_match_table = exynos_dp_video_phy_of_match, .of_match_table = exynos_dp_video_phy_of_match,
.suppress_bind_attrs = true,
} }
}; };
module_platform_driver(exynos_dp_video_phy_driver); module_platform_driver(exynos_dp_video_phy_driver);
......
...@@ -359,6 +359,7 @@ static struct platform_driver exynos_mipi_video_phy_driver = { ...@@ -359,6 +359,7 @@ static struct platform_driver exynos_mipi_video_phy_driver = {
.driver = { .driver = {
.of_match_table = exynos_mipi_video_phy_of_match, .of_match_table = exynos_mipi_video_phy_of_match,
.name = "exynos-mipi-video-phy", .name = "exynos-mipi-video-phy",
.suppress_bind_attrs = true,
} }
}; };
module_platform_driver(exynos_mipi_video_phy_driver); module_platform_driver(exynos_mipi_video_phy_driver);
......
...@@ -272,6 +272,7 @@ static struct platform_driver exynos_pcie_phy_driver = { ...@@ -272,6 +272,7 @@ static struct platform_driver exynos_pcie_phy_driver = {
.driver = { .driver = {
.of_match_table = exynos_pcie_phy_match, .of_match_table = exynos_pcie_phy_match,
.name = "exynos_pcie_phy", .name = "exynos_pcie_phy",
.suppress_bind_attrs = true,
} }
}; };
......
...@@ -953,6 +953,7 @@ static struct platform_driver exynos5_usb3drd_phy = { ...@@ -953,6 +953,7 @@ static struct platform_driver exynos5_usb3drd_phy = {
.driver = { .driver = {
.of_match_table = exynos5_usbdrd_phy_of_match, .of_match_table = exynos5_usbdrd_phy_of_match,
.name = "exynos5_usb3drd_phy", .name = "exynos5_usb3drd_phy",
.suppress_bind_attrs = true,
} }
}; };
......
...@@ -237,6 +237,7 @@ static struct platform_driver exynos_sata_phy_driver = { ...@@ -237,6 +237,7 @@ static struct platform_driver exynos_sata_phy_driver = {
.driver = { .driver = {
.of_match_table = exynos_sata_phy_of_match, .of_match_table = exynos_sata_phy_of_match,
.name = "samsung,sata-phy", .name = "samsung,sata-phy",
.suppress_bind_attrs = true,
} }
}; };
module_platform_driver(exynos_sata_phy_driver); module_platform_driver(exynos_sata_phy_driver);
......
...@@ -250,6 +250,7 @@ static struct platform_driver samsung_usb2_phy_driver = { ...@@ -250,6 +250,7 @@ static struct platform_driver samsung_usb2_phy_driver = {
.driver = { .driver = {
.of_match_table = samsung_usb2_phy_of_match, .of_match_table = samsung_usb2_phy_of_match,
.name = "samsung-usb2-phy", .name = "samsung-usb2-phy",
.suppress_bind_attrs = true,
} }
}; };
......
...@@ -405,6 +405,7 @@ static int serdes_am654_clk_register(struct serdes_am654 *am654_phy, ...@@ -405,6 +405,7 @@ static int serdes_am654_clk_register(struct serdes_am654 *am654_phy,
const __be32 *addr; const __be32 *addr;
unsigned int reg; unsigned int reg;
struct clk *clk; struct clk *clk;
int ret = 0;
mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
if (!mux) if (!mux)
...@@ -413,34 +414,40 @@ static int serdes_am654_clk_register(struct serdes_am654 *am654_phy, ...@@ -413,34 +414,40 @@ static int serdes_am654_clk_register(struct serdes_am654 *am654_phy,
init = &mux->clk_data; init = &mux->clk_data;
regmap_node = of_parse_phandle(node, "ti,serdes-clk", 0); regmap_node = of_parse_phandle(node, "ti,serdes-clk", 0);
of_node_put(regmap_node);
if (!regmap_node) { if (!regmap_node) {
dev_err(dev, "Fail to get serdes-clk node\n"); dev_err(dev, "Fail to get serdes-clk node\n");
return -ENODEV; ret = -ENODEV;
goto out_put_node;
} }
regmap = syscon_node_to_regmap(regmap_node->parent); regmap = syscon_node_to_regmap(regmap_node->parent);
if (IS_ERR(regmap)) { if (IS_ERR(regmap)) {
dev_err(dev, "Fail to get Syscon regmap\n"); dev_err(dev, "Fail to get Syscon regmap\n");
return PTR_ERR(regmap); ret = PTR_ERR(regmap);
goto out_put_node;
} }
num_parents = of_clk_get_parent_count(node); num_parents = of_clk_get_parent_count(node);
if (num_parents < 2) { if (num_parents < 2) {
dev_err(dev, "SERDES clock must have parents\n"); dev_err(dev, "SERDES clock must have parents\n");
return -EINVAL; ret = -EINVAL;
goto out_put_node;
} }
parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents), parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents),
GFP_KERNEL); GFP_KERNEL);
if (!parent_names) if (!parent_names) {
return -ENOMEM; ret = -ENOMEM;
goto out_put_node;
}
of_clk_parent_fill(node, parent_names, num_parents); of_clk_parent_fill(node, parent_names, num_parents);
addr = of_get_address(regmap_node, 0, NULL, NULL); addr = of_get_address(regmap_node, 0, NULL, NULL);
if (!addr) if (!addr) {
return -EINVAL; ret = -EINVAL;
goto out_put_node;
}
reg = be32_to_cpu(*addr); reg = be32_to_cpu(*addr);
...@@ -456,12 +463,16 @@ static int serdes_am654_clk_register(struct serdes_am654 *am654_phy, ...@@ -456,12 +463,16 @@ static int serdes_am654_clk_register(struct serdes_am654 *am654_phy,
mux->hw.init = init; mux->hw.init = init;
clk = devm_clk_register(dev, &mux->hw); clk = devm_clk_register(dev, &mux->hw);
if (IS_ERR(clk)) if (IS_ERR(clk)) {
return PTR_ERR(clk); ret = PTR_ERR(clk);
goto out_put_node;
}
am654_phy->clks[clock_num] = clk; am654_phy->clks[clock_num] = clk;
return 0; out_put_node:
of_node_put(regmap_node);
return ret;
} }
static const struct of_device_id serdes_am654_id_table[] = { static const struct of_device_id serdes_am654_id_table[] = {
......
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2019 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
*/
#define LANTIQ_PCIE_PHY_MODE_25MHZ 0
#define LANTIQ_PCIE_PHY_MODE_25MHZ_SSC 1
#define LANTIQ_PCIE_PHY_MODE_36MHZ 2
#define LANTIQ_PCIE_PHY_MODE_36MHZ_SSC 3
#define LANTIQ_PCIE_PHY_MODE_100MHZ 4
#define LANTIQ_PCIE_PHY_MODE_100MHZ_SSC 5
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