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Commit ebc4a2df authored by Adrian Bunk's avatar Adrian Bunk Committed by Linus Torvalds
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[PATCH] kill IPHASE5526 

iph5526 does not compiles since 2.5 and was therefore marked as broken.  This
patch removes it.
Signed-off-by: default avatarAdrian Bunk <bunk@stusta.de>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent d006c935
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drivers/net/Kconfig
View file @ ebc4a2df
...@@ -2528,15 +2528,6 @@ config NET_FC ...@@ -2528,15 +2528,6 @@ config NET_FC
adaptor below. You also should have said Y to "SCSI support" and adaptor below. You also should have said Y to "SCSI support" and
"SCSI generic support". "SCSI generic support".
config IPHASE5526
tristate "Interphase 5526 Tachyon chipset based adapter support"
depends on NET_FC && SCSI && PCI && BROKEN
help
Say Y here if you have a Fibre Channel adaptor of this kind.
To compile this driver as a module, choose M here: the module
will be called iph5526.
config SHAPER config SHAPER
tristate "Traffic Shaper (EXPERIMENTAL)" tristate "Traffic Shaper (EXPERIMENTAL)"
depends on NETDEVICES && EXPERIMENTAL depends on NETDEVICES && EXPERIMENTAL
......
drivers/net/Makefile
View file @ ebc4a2df
...@@ -183,7 +183,6 @@ obj-$(CONFIG_SMC91X) += smc91x.o ...@@ -183,7 +183,6 @@ obj-$(CONFIG_SMC91X) += smc91x.o
obj-$(CONFIG_FEC_8XX) += fec_8xx/ obj-$(CONFIG_FEC_8XX) += fec_8xx/
obj-$(CONFIG_ARM) += arm/ obj-$(CONFIG_ARM) += arm/
obj-$(CONFIG_NET_FC) += fc/
obj-$(CONFIG_DEV_APPLETALK) += appletalk/ obj-$(CONFIG_DEV_APPLETALK) += appletalk/
obj-$(CONFIG_TR) += tokenring/ obj-$(CONFIG_TR) += tokenring/
obj-$(CONFIG_WAN) += wan/ obj-$(CONFIG_WAN) += wan/
......
drivers/net/fc/Makefile deleted 100644 → 0
View file @ d006c935
#
# Makefile for linux/drivers/net/fc
#
# 9 Aug 2000, Christoph Hellwig <hch@infradead.org>
# Rewritten to use lists instead of if-statements.
#
obj-$(CONFIG_IPHASE5526) += iph5526.o
drivers/net/fc/iph5526.c deleted 100644 → 0
View file @ d006c935
This source diff could not be displayed because it is too large. You can view the blob instead.
drivers/net/fc/iph5526_ip.h deleted 100644 → 0
View file @ d006c935
#ifndef IPH5526_IP_H
#define IPH5526_IP_H
#define LLC_SNAP_LEN 0x8
/* Offsets into the ARP frame */
#define ARP_OPCODE_0 (0x6 + LLC_SNAP_LEN)
#define ARP_OPCODE_1 (0x7 + LLC_SNAP_LEN)
int iph5526_probe(struct net_device *dev);
static int fcdev_init(struct net_device *dev);
static int iph5526_open(struct net_device *dev);
static int iph5526_close(struct net_device *dev);
static int iph5526_send_packet(struct sk_buff *skb, struct net_device *dev);
static struct net_device_stats * iph5526_get_stats(struct net_device *dev);
static int iph5526_change_mtu(struct net_device *dev, int mtu);
static void rx_net_packet(struct fc_info *fi, u_char *buff_addr, int payload_size);
static void rx_net_mfs_packet(struct fc_info *fi, struct sk_buff *skb);
static int tx_ip_packet(struct sk_buff *skb, unsigned long len, struct fc_info *fi);
static int tx_arp_packet(char *data, unsigned long len, struct fc_info *fi);
#endif
drivers/net/fc/iph5526_novram.c deleted 100644 → 0
View file @ d006c935
/**********************************************************************
* Reading the NVRAM on the Interphase 5526 PCI Fibre Channel Card.
* All contents in this file : courtesy Interphase Corporation.
* Special thanks to Kevin Quick, kquick@iphase.com.
**********************************************************************/
#define FF_MAGIC 0x4646
#define DB_MAGIC 0x4442
#define DL_MAGIC 0x444d
#define CMD_LEN 9
/***********
*
* Switches and defines for header files.
*
* The following defines are used to turn on and off
* various options in the header files. Primarily useful
* for debugging.
*
***********/
static const unsigned short novram_default[4] = {
FF_MAGIC,
DB_MAGIC,
DL_MAGIC,
0 };
/*
* a list of the commands that can be sent to the NOVRAM
*/
#define NR_EXTEND 0x100
#define NR_WRITE 0x140
#define NR_READ 0x180
#define NR_ERASE 0x1c0
#define EWDS 0x00
#define WRAL 0x10
#define ERAL 0x20
#define EWEN 0x30
/*
* Defines for the pins on the NOVRAM
*/
#define BIT(x) (1 << (x))
#define NVDI_B 31
#define NVDI BIT(NVDI_B)
#define NVDO BIT(9)
#define NVCE BIT(30)
#define NVSK BIT(29)
#define NV_MANUAL BIT(28)
/***********
*
* Include files.
*
***********/
#define KeStallExecutionProcessor(x) {volatile int d, p;\
for (d=0; d<x; d++) for (p=0; p<10; p++);\
}
/***********************
*
* This define ands the value and the current config register and puts
* the result in the config register
*
***********************/
#define CFG_AND(val) { volatile int t; \
t = readl(fi->n_r.ptr_novram_hw_control_reg); \
t &= (val); \
writel(t, fi->n_r.ptr_novram_hw_control_reg); \
}
/***********************
*
* This define ors the value and the current config register and puts
* the result in the config register
*
***********************/
#define CFG_OR(val) { volatile int t; \
t = readl(fi->n_r.ptr_novram_hw_control_reg); \
t |= (val); \
writel(t, fi->n_r.ptr_novram_hw_control_reg); \
}
/***********************
*
* Send a command to the NOVRAM, the command is in cmd.
*
* clear CE and SK. Then assert CE.
* Clock each of the command bits out in the correct order with SK
* exit with CE still asserted
*
***********************/
#define NVRAM_CMD(cmd) { int i; \
int c = cmd; \
CFG_AND(~(NVCE|NVSK)); \
CFG_OR(NVCE); \
for (i=0; i<CMD_LEN; i++) { \
NVRAM_CLKOUT((c & (1 << (CMD_LEN - 1))) ? 1 : 0);\
c <<= 1; } }
/***********************
*
* clear the CE, this must be used after each command is complete
*
***********************/
#define NVRAM_CLR_CE CFG_AND(~NVCE)
/***********************
*
* clock the data bit in bitval out to the NOVRAM. The bitval must be
* a 1 or 0, or the clockout operation is undefined
*
***********************/
#define NVRAM_CLKOUT(bitval) {\
CFG_AND(~NVDI); \
CFG_OR((bitval) << NVDI_B); \
KeStallExecutionProcessor(5);\
CFG_OR(NVSK); \
KeStallExecutionProcessor(5);\
CFG_AND( ~NVSK); \
}
/***********************
*
* clock the data bit in and return a 1 or 0, depending on the value
* that was received from the NOVRAM
*
***********************/
#define NVRAM_CLKIN(val) {\
CFG_OR(NVSK); \
KeStallExecutionProcessor(5);\
CFG_AND(~NVSK); \
KeStallExecutionProcessor(5);\
val = (readl(fi->n_r.ptr_novram_hw_status_reg) & NVDO) ? 1 : 0; \
}
/***********
*
* Function Prototypes
*
***********/
static int iph5526_nr_get(struct fc_info *fi, int addr);
static void iph5526_nr_do_init(struct fc_info *fi);
static void iph5526_nr_checksum(struct fc_info *fi);
/*******************************************************************
*
* Local routine: iph5526_nr_do_init
* Purpose: initialize novram server
* Description:
*
* iph5526_nr_do_init reads the novram into the temporary holding place.
* A checksum is done on the area and the Magic Cookies are checked.
* If any of them are bad, the NOVRAM is initialized with the
* default values and a warning message is displayed.
*
*******************************************************************/
static void iph5526_nr_do_init(struct fc_info *fi)
{
int i;
unsigned short chksum = 0;
int bad = 0;
for (i=0; i<IPH5526_NOVRAM_SIZE; i++) {
fi->n_r.data[i] = iph5526_nr_get(fi, i);
chksum += fi->n_r.data[i];
}
if (chksum)
bad = 1;
if (fi->n_r.data[IPH5526_NOVRAM_SIZE - 4] != FF_MAGIC)
bad = 1;
if (fi->n_r.data[IPH5526_NOVRAM_SIZE - 3] != DB_MAGIC)
bad = 1;
if (fi->n_r.data[IPH5526_NOVRAM_SIZE - 2] != DL_MAGIC)
bad = 1;
if (bad) {
for (i=0; i<IPH5526_NOVRAM_SIZE; i++) {
if (i < (IPH5526_NOVRAM_SIZE - 4)) {
fi->n_r.data[i] = 0xffff;
} else {
fi->n_r.data[i] = novram_default[i - (IPH5526_NOVRAM_SIZE - 4)];
}
}
iph5526_nr_checksum(fi);
}
}
/*******************************************************************
*
* Local routine: iph5526_nr_get
* Purpose: read a single word of NOVRAM
* Description:
*
* read the 16 bits that make up a word addr of the novram.
* The 16 bits of data that are read are returned as the return value
*
*******************************************************************/
static int iph5526_nr_get(struct fc_info *fi, int addr)
{
int i;
int t;
int val = 0;
CFG_OR(NV_MANUAL);
/*
* read the first bit that was clocked with the falling edge of the
* the last command data clock
*/
NVRAM_CMD(NR_READ + addr);
/*
* Now read the rest of the bits, the next bit read is D1, then D2,
* and so on
*/
val = 0;
for (i=0; i<16; i++) {
NVRAM_CLKIN(t);
val <<= 1;
val |= t;
}
NVRAM_CLR_CE;
CFG_OR(NVDI);
CFG_AND(~NV_MANUAL);
return(val);
}
/*******************************************************************
*
* Local routine: iph5526_nr_checksum
* Purpose: calculate novram checksum on fi->n_r.data
* Description:
*
* calculate a checksum for the novram on the image that is
* currently in fi->n_r.data
*
*******************************************************************/
static void iph5526_nr_checksum(struct fc_info *fi)
{
int i;
unsigned short chksum = 0;
for (i=0; i<(IPH5526_NOVRAM_SIZE - 1); i++)
chksum += fi->n_r.data[i];
fi->n_r.data[i] = -chksum;
}
drivers/net/fc/iph5526_scsi.h deleted 100644 → 0
View file @ d006c935
#ifndef IPH5526_SCSI_H
#define IPH5526_SCSI_H
#define IPH5526_CAN_QUEUE 32
#define IPH5526_SCSI_FC { \
.name = "Interphase 5526 Fibre Channel SCSI Adapter", \
.detect = iph5526_detect, \
.release = iph5526_release, \
.info = iph5526_info, \
.queuecommand = iph5526_queuecommand, \
.bios_param = iph5526_biosparam, \
.can_queue = IPH5526_CAN_QUEUE, \
.this_id = -1, \
.sg_tablesize = 255, \
.cmd_per_lun = 8, \
.use_clustering = DISABLE_CLUSTERING, \
.eh_abort_handler = iph5526_abort, \
.eh_device_reset_handler = NULL, \
.eh_bus_reset_handler = NULL, \
.eh_host_reset_handler = NULL, \
}
int iph5526_detect(Scsi_Host_Template *tmpt);
int iph5526_queuecommand(Scsi_Cmnd *Cmnd, void (*done) (Scsi_Cmnd *));
int iph5526_release(struct Scsi_Host *host);
int iph5526_abort(Scsi_Cmnd *Cmnd);
const char *iph5526_info(struct Scsi_Host *host);
int iph5526_biosparam(struct Scsi_Disk * disk, struct block_device *n, int ip[]);
#endif
drivers/net/fc/tach.h deleted 100644 → 0
View file @ d006c935
/**********************************************************************
* Defines for the Tachyon Fibre Channel Controller and the Interphase
* (i)chip TPI.
*********************************************************************/
#ifndef _TACH_H
#define _TACH_H
#define MY_PAGE_SIZE 4096
#define REPLICATE 0xFF
#define MAX_NODES 127
#define BROADCAST 0xFFFFFF
#define BROADCAST_ADDR 0xFFFFFFFFFFFF
#define LOGIN_COMPLETED 2
#define LOGIN_ATTEMPTED 1
#define LOGIN_NOT_ATTEMPTED 0
#define TRUE 1
#define FALSE 0
#define TACHYON_LIMIT 0x01EF
#define TACHYON_OFFSET 0x200
/* Offsets to the (i) chip */
#define ICHIP_HW_CONTROL_REG_OFF (0x080 - TACHYON_OFFSET)
#define ICHIP_HW_STATUS_REG_OFF (0x084 - TACHYON_OFFSET)
#define ICHIP_HW_ADDR_MASK_REG_OFF (0x090 - TACHYON_OFFSET)
/* (i)chip Hardware Control Register defines */
#define ICHIP_HCR_RESET 0x01
#define ICHIP_HCR_DERESET 0x0
#define ICHIP_HCR_ENABLE_INTA 0x0000003E
#define ICHIP_HCR_ENABLE_INTB 0x003E0000
#define ICHIP_HCR_IWDATA_FIFO 0x800000
/* (i)chip Hardware Status Register defines */
#define ICHIP_HSR_INT_LATCH 0x02
/* (i)chip Hardware Address Mask Register defines */
#define ICHIP_HAMR_BYTE_SWAP_ADDR_TR 0x08
#define ICHIP_HAMR_BYTE_SWAP_NO_ADDR_TR 0x04
/* NOVRAM defines */
#define IPH5526_NOVRAM_SIZE 64
/* Offsets for the registers that correspond to the
* Qs on the Tachyon (As defined in the Tachyon Manual).
*/
/* Outbound Command Queue (OCQ).
*/
#define OCQ_BASE_REGISTER_OFFSET 0x000
#define OCQ_LENGTH_REGISTER_OFFSET 0x004
#define OCQ_PRODUCER_REGISTER_OFFSET 0x008
#define OCQ_CONSUMER_REGISTER_OFFSET 0x00C
/* Inbound Message Queue (IMQ).
*/
#define IMQ_BASE_REGISTER_OFFSET 0x080
#define IMQ_LENGTH_REGISTER_OFFSET 0x084
#define IMQ_CONSUMER_REGISTER_OFFSET 0x088
#define IMQ_PRODUCER_REGISTER_OFFSET 0x08C
/* Multiframe Sequence Buffer Queue (MFSBQ)
*/
#define MFSBQ_BASE_REGISTER_OFFSET 0x0C0
#define MFSBQ_LENGTH_REGISTER_OFFSET 0x0C4
#define MFSBQ_PRODUCER_REGISTER_OFFSET 0x0C8
#define MFSBQ_CONSUMER_REGISTER_OFFSET 0x0CC
#define MFS_LENGTH_REGISTER_OFFSET 0x0D0
/* Single Frame Sequence Buffer Queue (SFSBQ)
*/
#define SFSBQ_BASE_REGISTER_OFFSET 0x100
#define SFSBQ_LENGTH_REGISTER_OFFSET 0x104
#define SFSBQ_PRODUCER_REGISTER_OFFSET 0x108
#define SFSBQ_CONSUMER_REGISTER_OFFSET 0x10C
#define SFS_LENGTH_REGISTER_OFFSET 0x110
/* SCSI Exchange State Table (SEST)
*/
#define SEST_BASE_REGISTER_OFFSET 0x140
#define SEST_LENGTH_REGISTER_OFFSET 0x144
#define SCSI_LENGTH_REGISTER_OFFSET 0x148
/* Length of the various Qs
*/
#define NO_OF_ENTRIES 8
#define OCQ_LENGTH (MY_PAGE_SIZE/32)
#define IMQ_LENGTH (MY_PAGE_SIZE/32)
#define MFSBQ_LENGTH 8
#define SFSBQ_LENGTH 8
#define SEST_LENGTH MY_PAGE_SIZE
/* Size of the various buffers.
*/
#define TACH_FRAME_SIZE 2048
#define MFS_BUFFER_SIZE TACH_FRAME_SIZE
#define SFS_BUFFER_SIZE (TACH_FRAME_SIZE + TACHYON_HEADER_LEN)
#define SEST_BUFFER_SIZE 512
#define TACH_HEADER_SIZE 64
#define NO_OF_TACH_HEADERS ((MY_PAGE_SIZE)/TACH_HEADER_SIZE)
#define NO_OF_FCP_CMNDS (MY_PAGE_SIZE/32)
#define SDB_SIZE 2048
#define NO_OF_SDB_ENTRIES ((32*MY_PAGE_SIZE)/SDB_SIZE)
/* Offsets to the other Tachyon registers.
* (As defined in the Tachyon manual)
*/
#define TACHYON_CONFIG_REGISTER_OFFSET 0x184
#define TACHYON_CONTROL_REGISTER_OFFSET 0x188
#define TACHYON_STATUS_REGISTER_OFFSET 0x18C
#define TACHYON_FLUSH_SEST_REGISTER_OFFSET 0x190
/* Defines for the Tachyon Configuration register.
*/
#define SCSI_ENABLE 0x40000000
#define WRITE_STREAM_SIZE 0x800 /* size = 16 */
#define READ_STREAM_SIZE 0x300 /* size = 64 */
#define PARITY_EVEN 0x2
#define OOO_REASSEMBLY_DISABLE 0x40
/* Defines for the Tachyon Control register.
*/
#define SOFTWARE_RESET 0x80000000
#define OCQ_RESET 0x4
#define ERROR_RELEASE 0x2
/* Defines for the Tachyon Status register.
*/
#define RECEIVE_FIFO_EMPTY 0x10
#define OSM_FROZEN 0x1
#define OCQ_RESET_STATUS 0x20
#define SCSI_FREEZE_STATUS 0x40
/* Offsets to the Frame Manager registers.
*/
#define FMGR_CONFIG_REGISTER_OFFSET 0x1C0
#define FMGR_CONTROL_REGISTER_OFFSET 0x1C4
#define FMGR_STATUS_REGISTER_OFFSET 0x1C8
#define FMGR_TIMER_REGISTER_OFFSET 0x1CC
#define FMGR_WWN_HI_REGISTER_OFFSET 0x1E0
#define FMGR_WWN_LO_REGISTER_OFFSET 0x1E4
#define FMGR_RCVD_ALPA_REGISTER_OFFSET 0x1E8
/* Defines for the Frame Manager Configuration register.
*/
#define BB_CREDIT 0x10000
#define NPORT 0x8000
#define LOOP_INIT_FABRIC_ADDRESS 0x400
#define LOOP_INIT_PREVIOUS_ADDRESS 0x200
#define LOOP_INIT_SOFT_ADDRESS 0x80
/* Defines for the Frame Manager Control register.
*/
#define HOST_CONTROL 0x02
#define EXIT_HOST_CONTROL 0x03
#define OFFLINE 0x05
#define INITIALIZE 0x06
#define CLEAR_LF 0x07
/* Defines for the Frame Manager Status register.
*/
#define LOOP_UP 0x80000000
#define TRANSMIT_PARITY_ERROR 0x40000000
#define NON_PARTICIPATING 0x20000000
#define OUT_OF_SYNC 0x02000000
#define LOSS_OF_SIGNAL 0x01000000
#define NOS_OLS_RECEIVED 0x00080000
#define LOOP_STATE_TIMEOUT 0x00040000
#define LIPF_RECEIVED 0x00020000
#define BAD_ALPA 0x00010000
#define LINK_FAILURE 0x00001000
#define ELASTIC_STORE_ERROR 0x00000400
#define LINK_UP 0x00000200
#define LINK_DOWN 0x00000100
#define ARBITRATING 0x00000010
#define ARB_WON 0x00000020
#define OPEN 0x00000030
#define OPENED 0x00000040
#define TX_CLS 0x00000050
#define RX_CLS 0x00000060
#define TRANSFER 0x00000070
#define INITIALIZING 0x00000080
#define LOOP_FAIL 0x000000D0
#define OLD_PORT 0x000000F0
#define PORT_STATE_ACTIVE 0x0000000F
#define PORT_STATE_OFFLINE 0x00000000
#define PORT_STATE_LF1 0x00000009
#define PORT_STATE_LF2 0x0000000A
/* Completion Message Types
* (defined in P.177 of the Tachyon manual)
*/
#define OUTBOUND_COMPLETION 0x000
#define OUTBOUND_COMPLETION_I 0x100
#define OUT_HI_PRI_COMPLETION 0x001
#define OUT_HI_PRI_COMPLETION_I 0x101
#define INBOUND_MFS_COMPLETION 0x102
#define INBOUND_OOO_COMPLETION 0x003
#define INBOUND_SFS_COMPLETION 0x104
#define INBOUND_C1_TIMEOUT 0x105
#define INBOUND_UNKNOWN_FRAME_I 0x106
#define INBOUND_BUSIED_FRAME 0x006
#define SFS_BUF_WARN 0x107
#define MFS_BUF_WARN 0x108
#define IMQ_BUF_WARN 0x109
#define FRAME_MGR_INTERRUPT 0x10A
#define READ_STATUS 0x10B
#define INBOUND_SCSI_DATA_COMPLETION 0x10C
#define INBOUND_SCSI_COMMAND 0x10D
#define BAD_SCSI_FRAME 0x10E
#define INB_SCSI_STATUS_COMPLETION 0x10F
/* One of the things that we care about when we receive an
* Outbound Completion Message (OCM).
*/
#define OCM_TIMEOUT_OR_BAD_ALPA 0x0800
/* Defines for the Tachyon Header structure.
*/
#define SOFI3 0x70
#define SOFN3 0xB0
#define EOFN 0x5
/* R_CTL */
#define FC4_DEVICE_DATA 0
#define EXTENDED_LINK_DATA 0x20000000
#define FC4_LINK_DATA 0x30000000
#define BASIC_LINK_DATA 0x80000000
#define LINK_CONTROL 0xC0000000
#define SOLICITED_DATA 0x1000000
#define UNSOLICITED_CONTROL 0x2000000
#define SOLICITED_CONTROL 0x3000000
#define UNSOLICITED_DATA 0x4000000
#define DATA_DESCRIPTOR 0x5000000
#define UNSOLICITED_COMMAND 0x6000000
#define RCTL_ELS_UCTL 0x22000000
#define RCTL_ELS_SCTL 0x23000000
#define RCTL_BASIC_ABTS 0x81000000
#define RCTL_BASIC_ACC 0x84000000
#define RCTL_BASIC_RJT 0x85000000
/* TYPE */
#define TYPE_BLS 0x00000000
#define TYPE_ELS 0x01000000
#define TYPE_FC_SERVICES 0x20000000
#define TYPE_LLC_SNAP 0x05000000
#define TYPE_FCP 0x08000000
/* F_CTL */
#define EXCHANGE_RESPONDER 0x800000
#define SEQUENCE_RESPONDER 0x400000
#define FIRST_SEQUENCE 0x200000
#define LAST_SEQUENCE 0x100000
#define SEQUENCE_INITIATIVE 0x10000
#define RELATIVE_OFF_PRESENT 0x8
#define END_SEQUENCE 0x80000
#define TACHYON_HEADER_LEN 32
#define NW_HEADER_LEN 16
/* Defines for the Outbound Descriptor Block (ODB).
*/
#define ODB_CLASS_3 0xC000
#define ODB_NO_COMP 0x400
#define ODB_NO_INT 0x200
#define ODB_EE_CREDIT 0xF
/* Defines for the Extended Descriptor Block (EDB).
*/
#define EDB_LEN ((32*MY_PAGE_SIZE)/8)
#define EDB_END 0x8000
#define EDB_FREE 0
#define EDB_BUSY 1
/* Command Codes */
#define ELS_LS_RJT 0x01000000
#define ELS_ACC 0x02000000
#define ELS_PLOGI 0x03000000
#define ELS_FLOGI 0x04000000
#define ELS_LOGO 0x05000000
#define ELS_TPRLO 0x24000000
#define ELS_ADISC 0x52000000
#define ELS_PDISC 0x50000000
#define ELS_PRLI 0x20000000
#define ELS_PRLO 0x21000000
#define ELS_SCR 0x62000000
#define ELS_RSCN 0x61000000
#define ELS_FARP_REQ 0x54000000
#define ELS_ABTX 0x06000000
#define ELS_ADVC 0x0D000000
#define ELS_ECHO 0x10000000
#define ELS_ESTC 0x0C000000
#define ELS_ESTS 0x0B000000
#define ELS_RCS 0x07000000
#define ELS_RES 0x08000000
#define ELS_RLS 0x0F000000
#define ELS_RRQ 0x12000000
#define ELS_RSS 0x09000000
#define ELS_RTV 0x0E000000
#define ELS_RSI 0x0A000000
#define ELS_TEST 0x11000000
#define ELS_RNC 0x53000000
#define ELS_RVCS 0x41000000
#define ELS_TPLS 0x23000000
#define ELS_GAID 0x30000000
#define ELS_FACT 0x31000000
#define ELS_FAN 0x60000000
#define ELS_FDACT 0x32000000
#define ELS_NACT 0x33000000
#define ELS_NDACT 0x34000000
#define ELS_QoSR 0x40000000
#define ELS_FDISC 0x51000000
#define ELS_NS_PLOGI 0x03FFFFFC
/* LS_RJT reason codes.
*/
#define INV_LS_CMND_CODE 0x0001
#define LOGICAL_ERR 0x0003
#define LOGICAL_BUSY 0x0005
#define PROTOCOL_ERR 0x0007
#define UNABLE_TO_PERFORM 0x0009
#define CMND_NOT_SUPP 0x000B
/* LS_RJT explanation codes.
*/
#define NO_EXPLN 0x0000
#define RECV_FIELD_SIZE 0x0700
#define CONC_SEQ 0x0900
#define REQ_NOT_SUPPORTED 0x2C00
#define INV_PAYLOAD_LEN 0x2D00
/* Payload Length defines.
*/
#define PLOGI_LEN 116
#define CONCURRENT_SEQUENCES 0x01
#define RO_INFO_CATEGORY 0xFE
#define E_D_TOV 0x07D0 /* 2 Secs */
#define AL_TIME 0x0010 /* ~15 msec */
#define TOV_VALUES (AL_TIME << 16) | E_D_TOV
#define RT_TOV 0x64 /* 100 msec */
#define PTP_TOV_VALUES (RT_TOV << 16) | E_D_TOV
#define SERVICE_VALID 0x8000
#define SEQUENCE_DELIVERY 0x0800
#define CLASS3_CONCURRENT_SEQUENCE 0x01
#define CLASS3_OPEN_SEQUENCE 0x01
/* These are retrieved from the NOVRAM.
*/
#define WORLD_WIDE_NAME_LOW fi->g.my_port_name_low
#define WORLD_WIDE_NAME_HIGH fi->g.my_port_name_high
#define N_PORT_NAME_HIGH fi->g.my_port_name_high
#define N_PORT_NAME_LOW fi->g.my_port_name_low
#define NODE_NAME_HIGH fi->g.my_node_name_high
#define NODE_NAME_LOW fi->g.my_node_name_low
#define PORT_NAME_LEN 8
#define NODE_NAME_LEN 8
#define PH_VERSION 0x0909
#define LOOP_BB_CREDIT 0x00
#define PT2PT_BB_CREDIT 0x01
#define FLOGI_C_F 0x0800 /* Alternate BB_Credit Mgmnt */
#define PLOGI_C_F 0x8800 /* Continuously Increasing + Alternate BB_Credit Management */
/* Fabric defines */
#define DIRECTORY_SERVER 0xFFFFFC
#define FABRIC_CONTROLLER 0xFFFFFD
#define F_PORT 0xFFFFFE
#define FLOGI_DID 0xFFFE
#define NS_PLOGI_DID 0xFFFC
/* Fibre Channel Services defines */
#define FCS_RFC_4 0x02170000
#define FCS_GP_ID4 0x01A10000
#define FCS_ACC 0x8002
#define FCS_REJECT 0x8001
/* CT Header defines */
#define FC_CT_REV 0x01000000
#define DIRECTORY_SERVER_APP 0xFC
#define NAME_SERVICE 0x02
/* Port Type defines */
#define PORT_TYPE_IP 0x05000000
#define PORT_TYPE_NX_PORTS 0x7F000000
/* SCR defines */
#define FABRIC_DETECTED_REG 0x00000001
#define N_PORT_DETECTED_REG 0x00000002
#define FULL_REGISTRATION 0x00000003
#define CLEAR_REGISTRATION 0x000000FF
/* Command structure has only one byte to address targets
*/
#define MAX_SCSI_TARGETS 0xFF
#define FC_SCSI_READ 0x80
#define FC_SCSI_WRITE 0x81
#define FC_ELS 0x01
#define FC_BLS 0x00
#define FC_IP 0x05
#define FC_BROADCAST 0xFF
/* SEST defines.
*/
#define SEST_V 0x80000000 /* V = 1 */
#define INB_SEST_VED 0xA0000000 /* V = 1, D = 1 */
#define SEST_INV 0x7FFFFFFF
#define OUTB_SEST_VED 0x80000000 /* V = 1 */
#define INV_SEQ_LEN 0xFFFFFFFF
#define OUTB_SEST_LINK 0xFFFF
/* PRLI defines.
*/
#define PAGE_LEN 0x100000 /* 3rd byte - 0x10 */
#define PRLI_LEN 0x0014 /* 20 bytes */
#define FCP_TYPE_CODE 0x0800 /* FCP-SCSI */
#define IMAGE_PAIR 0x2000 /* establish image pair */
#define INITIATOR_FUNC 0x00000020
#define TARGET_FUNC 0x00000010
#define READ_XFER_RDY_DISABLED 0x00000002
#define NODE_PROCESS_LOGGED_IN 0x3
#define NODE_NOT_PRESENT 0x2
#define NODE_LOGGED_IN 0x1
#define NODE_LOGGED_OUT 0x0
/* Defines to determine what should be returned when a SCSI frame
* times out.
*/
#define FC_SCSI_BAD_TARGET 0xFFFE0000
/* RSCN Address formats */
#define PORT_ADDRESS_FORMAT 0x00
#define AREA_ADDRESS_FORMAT 0x01
#define DOMAIN_ADDRESS_FORMAT 0x02
/* Defines used to determine whether a frame transmission should
* be indicated by an interrupt or not.
*/
#define NO_COMP_AND_INT 0
#define INT_AND_COMP_REQ 1
#define NO_INT_COMP_REQ 2
/* Other junk...
*/
#define SDB_FREE 0
#define SDB_BUSY 1
#define MAX_PENDING_FRAMES 15
#define RX_ID_FIRST_SEQUENCE 0xFFFF
#define OX_ID_FIRST_SEQUENCE 0xFFFF
#define NOT_SCSI_XID 0x8000
#define MAX_SCSI_XID 0x0FFF /* X_IDs are from 0-4095 */
#define SCSI_READ_BIT 0x4000
#define MAX_SCSI_OXID 0x4FFF
#define OXID_AVAILABLE 0
#define OXID_INUSE 1
#define MAX_SEQ_ID 0xFF
#define INITIATOR 2
#define TARGET 1
#define DELETE_ENTRY 1
#define ADD_ENTRY 2
#endif /* _TACH_H */
drivers/net/fc/tach_structs.h deleted 100644 → 0
View file @ d006c935
/**********************************************************************
* iph5526.c: Structures for the Interphase 5526 PCI Fibre Channel
* IP/SCSI driver.
* Copyright (C) 1999 Vineet M Abraham <vmabraham@hotmail.com>
**********************************************************************/
#ifndef _TACH_STRUCT_H
#define _TACH_STRUCT_H
typedef struct {
u_short cmnd_code;
u_short payload_length;
u_short type_code;
u_short est_image_pair;
u_int originator_pa;
u_int responder_pa;
u_int service_params;
} PRLI;
typedef struct {
u_int flags_and_byte_offset;
u_int byte_count;
u_short no_of_recvd_frames;
u_short no_of_expected_frames;
u_int last_fctl;
u_int sdb_address;
u_int scratch_pad;
u_int expected_ro;
u_short buffer_index;
u_short buffer_offset;
} INB_SEST_ENTRY;
typedef struct {
u_int flags_and_did;
u_short max_frame_len;
u_short cntl;
u_int total_seq_length;
u_short link;
u_short rx_id;
u_int transaction_id;
u_int header_address;
u_char seq_id;
u_char reserved;
u_short header_length;
u_int edb_address;
} OUTB_SEST_ENTRY;
typedef struct {
u_short d_naa;
u_short dest_high;
u_int dest_low;
u_short s_naa;
u_short source_high;
u_int source_low;
} NW_HEADER;
typedef struct {
u_int resv;
u_char sof_and_eof;
u_char dest_alpa;
u_short lcr_and_time_stamp;
u_int r_ctl_and_d_id;
u_int vc_id_and_s_id;
u_int type_and_f_cntl;
u_char seq_id;
u_char df_cntl;
u_short seq_cnt;
u_short ox_id;
u_short rx_id;
u_int ro;
NW_HEADER nw_header;
} TACHYON_HEADER;
typedef struct {
u_short service_options;
u_short initiator_ctl;
u_short recipient_ctl;
u_short recv_data_field_size;
u_short concurrent_sequences;
u_short n_port_end_to_end_credit;
u_short open_seq_per_exchange;
u_short resv;
}CLASS_OF_SERVICE;
typedef struct {
u_int logo_cmnd;
u_char reserved;
u_char n_port_id_2;
u_char n_port_id_1;
u_char n_port_id_0;
u_int port_name_up;
u_int port_name_low;
} LOGO;
typedef struct {
u_int ls_cmnd_code;
u_int hard_address;
u_int port_name_high;
u_int port_name_low;
u_int node_name_high;
u_int node_name_low;
u_int n_port_id;
} ADISC;
typedef struct {
u_int cmnd_code;
u_int reason_code;
} LS_RJT;
typedef struct {
u_int cmnd_code;
} ACC;
typedef struct {
u_int seq_d_id;
u_int tot_len;
u_short cntl;
u_short rx_id;
u_short cs_enable;
u_short cs_seed;
u_int trans_id;
u_int hdr_addr;
u_short frame_len;
u_short hdr_len;
u_int edb_addr;
}ODB;
typedef struct {
u_int cmnd_code;
u_int reg_function; /* in the last byte */
} SCR;
typedef struct {
u_int rev_in_id;
u_char fs_type;
u_char fs_subtype;
u_char options;
u_char resv1;
u_short cmnd_resp_code;
u_short max_res_size;
u_char resv2;
u_char reason_code;
u_char expln_code;
u_char vendor_unique;
} CT_HDR;
typedef struct {
CT_HDR ct_hdr;
u_int s_id;
u_char bit_map[32]; /* 32 byte bit map */
} RFC_4;
typedef struct {
u_int ls_cmnd_code;
u_short fc_ph_version;
u_short buff_to_buff_credit;
u_short common_features;
u_short recv_data_field_size;
u_short n_port_total_conc_seq;
u_short rel_off_by_info_cat;
u_int ED_TOV;
u_int n_port_name_high;
u_int n_port_name_low;
u_int node_name_high;
u_int node_name_low;
CLASS_OF_SERVICE c_of_s[3];
u_int resv[4];
u_int vendor_version_level[4];
}LOGIN;
typedef struct {
CT_HDR ct_hdr;
u_int port_type; /* in the first byte */
} GP_ID4;
typedef struct {
u_int buf_addr;
u_short ehf;
u_short buf_len;
}EDB;
/* (i)chip Registers */
struct i_chip_regs {
u_int ptr_ichip_hw_control_reg;
u_int ptr_ichip_hw_status_reg;
u_int ptr_ichip_hw_addr_mask_reg;
};
struct iph5526_novram {
u_int ptr_novram_hw_control_reg;
u_int ptr_novram_hw_status_reg;
u_short data[IPH5526_NOVRAM_SIZE];
};
/* Tachyon Registers */
struct tachyon_regs {
u_int ptr_ocq_base_reg;
u_int ptr_ocq_len_reg;
u_int ptr_ocq_prod_indx_reg;
u_int ptr_ocq_cons_indx_reg;
u_int ptr_imq_base_reg;
u_int ptr_imq_len_reg;
u_int ptr_imq_cons_indx_reg;
u_int ptr_imq_prod_indx_reg;
u_int ptr_mfsbq_base_reg;
u_int ptr_mfsbq_len_reg;
u_int ptr_mfsbq_prod_reg;
u_int ptr_mfsbq_cons_reg;
u_int ptr_mfsbuff_len_reg;
u_int ptr_sfsbq_base_reg;
u_int ptr_sfsbq_len_reg;
u_int ptr_sfsbq_prod_reg;
u_int ptr_sfsbq_cons_reg;
u_int ptr_sfsbuff_len_reg;
u_int ptr_sest_base_reg;
u_int ptr_sest_len_reg;
u_int ptr_scsibuff_len_reg;
u_int ptr_tach_config_reg;
u_int ptr_tach_control_reg;
u_int ptr_tach_status_reg;
u_int ptr_tach_flush_oxid_reg;
u_int ptr_fm_config_reg;
u_int ptr_fm_control_reg;
u_int ptr_fm_status_reg;
u_int ptr_fm_tov_reg;
u_int ptr_fm_wwn_hi_reg;
u_int ptr_fm_wwn_low_reg;
u_int ptr_fm_rx_al_pa_reg;
};
struct globals {
u_long tachyon_base;
u_int *mem_base;
u_short ox_id; /* OX_ID used for IP and ELS frames */
u_short scsi_oxid; /* OX_ID for SEST entry */
u_char seq_id;
u_int my_id;
u_int my_ddaa; /* my domain and area in a fabric */
volatile u_char loop_up;
volatile u_char ptp_up; /* we have a point-to-point link */
volatile u_char link_up;
volatile u_char n_port_try;
volatile u_char nport_timer_set;
volatile u_char lport_timer_set;
/* Hmmm... We don't want to Initialize while closing */
u_char dont_init;
u_int my_node_name_high;
u_int my_node_name_low;
u_int my_port_name_high;
u_int my_port_name_low;
u_char fabric_present;
u_char explore_fabric;
u_char name_server;
u_int my_mtu;
u_int *els_buffer[MAX_PENDING_FRAMES]; /* temp space for ELS frames */
char *arp_buffer; /* temp space for ARP frames */
u_int mfs_buffer_count; /* keep track of MFS buffers used*/
u_char scsi_registered;
/* variables for port discovery */
volatile u_char port_discovery;
volatile u_char perform_adisc;
u_short alpa_list_index;
u_short type_of_frame; /* Could be IP/SCSI Read/SCSI Write*/
u_char no_of_targets; /* used to assign target_ids */
u_long sem; /* to synchronize between IP and SCSI */
u_char e_i;
/* the frames */
TACHYON_HEADER tach_header;
LOGIN login;
PRLI prli;
LOGO logo;
ADISC adisc;
LS_RJT ls_rjt;
ODB odb;
INB_SEST_ENTRY inb_sest_entry;
OUTB_SEST_ENTRY outb_sest_entry;
ACC acc;
SCR scr;
EDB edb;
RFC_4 rfc_4;
GP_ID4 gp_id4;
};
struct queue_variables {
/* Indices maintained in host memory.
*/
u_int *host_ocq_cons_indx, *host_hpcq_cons_indx, *host_imq_prod_indx;
u_int *ptr_host_ocq_cons_indx, *ptr_host_hpcq_cons_indx, *ptr_host_imq_prod_indx;
/* Variables for Outbound Command Queue (OCQ).
*/
u_int *ptr_ocq_base;
u_int ocq_len, ocq_end;
u_int ocq_prod_indx;
u_int *ptr_odb[OCQ_LENGTH];
/* Variables for Inbound Message Queue (IMQ).
*/
u_int *ptr_imq_base;
u_int imq_len, imq_end;
u_int imq_cons_indx;
u_int imq_prod_indx;
u_int *ptr_imqe[IMQ_LENGTH];
u_int *ptr_mfsbq_base;
u_int mfsbq_len, mfsbq_end;
u_int mfsbq_prod_indx;
u_int mfsbq_cons_indx;
u_int mfsbuff_len, mfsbuff_end;
u_int *ptr_sfsbq_base;
u_int sfsbq_len, sfsbq_end;
u_int sfsbq_prod_indx;
u_int sfsbq_cons_indx;
u_int sfsbuff_len, sfsbuff_end;
u_int *ptr_sfs_buffers[SFSBQ_LENGTH * NO_OF_ENTRIES];
/* Tables for SCSI Transactions */
u_int *ptr_sest_base;
u_int *ptr_sest[SEST_LENGTH];
u_char free_scsi_oxid[SEST_LENGTH];
u_int *ptr_sdb_base;
u_int *ptr_sdb_slot[NO_OF_SDB_ENTRIES];
u_char sdb_slot_status[NO_OF_SDB_ENTRIES];
u_int sdb_indx;
u_int *ptr_fcp_cmnd_base;
u_int *ptr_fcp_cmnd[NO_OF_FCP_CMNDS];
u_int fcp_cmnd_indx;
/* Table for data to be transmitted.
*/
u_int *ptr_edb_base;
u_int *ptr_edb[EDB_LEN];
u_int edb_buffer_indx;
volatile u_char free_edb_list[EDB_LEN];
/* Table of Tachyon Headers.
*/
u_int *ptr_tachyon_header[NO_OF_TACH_HEADERS];
u_int *ptr_tachyon_header_base;
u_int tachyon_header_indx;
};
/* Used to match incoming ACCs to ELS requests sent out */
struct ox_id_els_map {
u_short ox_id;
u_int els;
struct ox_id_els_map *next;
};
/* Carries info about individual nodes... stores the info got at login
* time. Also maintains mapping between MAC->FC addresses
*/
struct fc_node_info {
/* Itz the WWN (8 bytes), the last 6 bytes is the MAC address */
u_char hw_addr[PORT_NAME_LEN];
u_char node_name[NODE_NAME_LEN];
u_int d_id; /*real FC address, 3 bytes */
int mtu;
/* login = 1 if login attempted
* login = 2 if login completed
*/
int login;
u_char scsi; /* = 1 if device is a SCSI Target */
u_char target_id;
CLASS_OF_SERVICE c_of_s[3];
struct fc_node_info *next;
};
struct fc_info {
char name[8];
u_long base_addr;
int irq;
struct net_device_stats fc_stats;
struct fc_node_info *node_info_list;
int num_nodes;
struct ox_id_els_map *ox_id_list;
struct i_chip_regs i_r;
struct tachyon_regs t_r;
struct queue_variables q;
struct globals g;
struct iph5526_novram n_r;
u_short clone_id;
struct timer_list nport_timer;
struct timer_list lport_timer;
struct timer_list explore_timer;
struct timer_list display_cache_timer;
struct net_device *dev;
struct Scsi_Host *host;
spinlock_t fc_lock;
};
struct iph5526_hostdata {
struct fc_info *fi;
fcp_cmd cmnd;
Scsi_Cmnd *cmnd_handler[SEST_LENGTH];
u_int tag_ages[MAX_SCSI_TARGETS];
};
/* List of valid AL_PAs */
u_char alpa_list[127] = {
0x00, 0x01, 0x02, 0x04, 0x08, 0x0F, 0x10, 0x17,
0x18, 0x1B, 0x1D, 0x1E, 0x1F, 0x23, 0x25, 0x26,
0x27, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x31,
0x32, 0x33, 0x34, 0x35, 0x36, 0x39, 0x3A, 0x3C,
0x43, 0x45, 0x46, 0x47, 0x49, 0x4A, 0x4B, 0x4C,
0x4D, 0x4E, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56,
0x59, 0x5A, 0x5C, 0x63, 0x65, 0x66, 0x67, 0x69,
0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x71, 0x72, 0x73,
0x74, 0x75, 0x76, 0x79, 0x7A, 0x7C, 0x80, 0x81,
0x82, 0x84, 0x88, 0x8F, 0x90, 0x97, 0x98, 0x9B,
0x9D, 0x9E, 0x9F, 0xA3, 0xA5, 0xA6, 0xA7, 0xA9,
0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xB1, 0xB2, 0xB3,
0xB4, 0xB5, 0xB6, 0xB9, 0xBA, 0xBC, 0xC3, 0xC5,
0xC6, 0xC7, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE,
0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD9, 0xDA,
0xDC, 0xE0, 0xE1, 0xE2, 0xE4, 0xE8, 0xEF
};
#endif /* _TACH_STRUCT_H */
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