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Commit fbc836cd authored by Sung Joon Kim's avatar Sung Joon Kim Committed by Alex Deucher
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drm/amd/display: Remove read/write to external register 

[why&how]
We need to remove the reference to these registers to
prevent any usage in the future.
Reviewed-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: default avatarTom Chung <chiahsuan.chung@amd.com>
Signed-off-by: default avatarSung Joon Kim <sungkim@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 1ba65e74
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Showing with 0 additions and 88 deletions
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
View file @ fbc836cd
...@@ -842,35 +842,6 @@ static void dcn35_set_low_power_state(struct clk_mgr *clk_mgr_base) ...@@ -842,35 +842,6 @@ static void dcn35_set_low_power_state(struct clk_mgr *clk_mgr_base)
} }
} }
static void dcn35_set_ips_idle_state(struct clk_mgr *clk_mgr_base, bool allow_idle)
{
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
struct dc *dc = clk_mgr_base->ctx->dc;
uint32_t val = dcn35_smu_read_ips_scratch(clk_mgr);
if (dc->config.disable_ips == DMUB_IPS_ENABLE ||
dc->config.disable_ips == DMUB_IPS_DISABLE_DYNAMIC) {
val = val & ~DMUB_IPS1_ALLOW_MASK;
val = val & ~DMUB_IPS2_ALLOW_MASK;
} else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS1) {
val |= DMUB_IPS1_ALLOW_MASK;
val |= DMUB_IPS2_ALLOW_MASK;
} else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS2) {
val = val & ~DMUB_IPS1_ALLOW_MASK;
val |= DMUB_IPS2_ALLOW_MASK;
} else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS2_Z10) {
val = val & ~DMUB_IPS1_ALLOW_MASK;
val = val & ~DMUB_IPS2_ALLOW_MASK;
}
if (!allow_idle) {
val |= DMUB_IPS1_ALLOW_MASK;
val |= DMUB_IPS2_ALLOW_MASK;
}
dcn35_smu_write_ips_scratch(clk_mgr, val);
}
static void dcn35_exit_low_power_state(struct clk_mgr *clk_mgr_base) static void dcn35_exit_low_power_state(struct clk_mgr *clk_mgr_base)
{ {
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
...@@ -890,13 +861,6 @@ static bool dcn35_is_ips_supported(struct clk_mgr *clk_mgr_base) ...@@ -890,13 +861,6 @@ static bool dcn35_is_ips_supported(struct clk_mgr *clk_mgr_base)
return ips_supported; return ips_supported;
} }
static uint32_t dcn35_get_ips_idle_state(struct clk_mgr *clk_mgr_base)
{
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
return dcn35_smu_read_ips_scratch(clk_mgr);
}
static void dcn35_init_clocks_fpga(struct clk_mgr *clk_mgr) static void dcn35_init_clocks_fpga(struct clk_mgr *clk_mgr)
{ {
init_clk_states(clk_mgr); init_clk_states(clk_mgr);
...@@ -984,8 +948,6 @@ static struct clk_mgr_funcs dcn35_funcs = { ...@@ -984,8 +948,6 @@ static struct clk_mgr_funcs dcn35_funcs = {
.set_low_power_state = dcn35_set_low_power_state, .set_low_power_state = dcn35_set_low_power_state,
.exit_low_power_state = dcn35_exit_low_power_state, .exit_low_power_state = dcn35_exit_low_power_state,
.is_ips_supported = dcn35_is_ips_supported, .is_ips_supported = dcn35_is_ips_supported,
.set_idle_state = dcn35_set_ips_idle_state,
.get_idle_state = dcn35_get_ips_idle_state
}; };
struct clk_mgr_funcs dcn35_fpga_funcs = { struct clk_mgr_funcs dcn35_fpga_funcs = {
......
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
View file @ fbc836cd
...@@ -487,24 +487,3 @@ int dcn35_smu_get_ips_supported(struct clk_mgr_internal *clk_mgr) ...@@ -487,24 +487,3 @@ int dcn35_smu_get_ips_supported(struct clk_mgr_internal *clk_mgr)
//smu_print("%s: VBIOSSMC_MSG_QueryIPS2Support return = %x\n", __func__, retv); //smu_print("%s: VBIOSSMC_MSG_QueryIPS2Support return = %x\n", __func__, retv);
return retv; return retv;
} }
void dcn35_smu_write_ips_scratch(struct clk_mgr_internal *clk_mgr, uint32_t param)
{
if (!clk_mgr->smu_present)
return;
REG_WRITE(MP1_SMN_C2PMSG_71, param);
//smu_print("%s: write_ips_scratch = %x\n", __func__, param);
}
uint32_t dcn35_smu_read_ips_scratch(struct clk_mgr_internal *clk_mgr)
{
uint32_t retv;
if (!clk_mgr->smu_present)
return 0;
retv = REG_READ(MP1_SMN_C2PMSG_71);
//smu_print("%s: dcn35_smu_read_ips_scratch = %x\n", __func__, retv);
return retv;
}
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h
View file @ fbc836cd
...@@ -198,6 +198,4 @@ int dcn35_smu_exit_low_power_state(struct clk_mgr_internal *clk_mgr); ...@@ -198,6 +198,4 @@ int dcn35_smu_exit_low_power_state(struct clk_mgr_internal *clk_mgr);
int dcn35_smu_get_ips_supported(struct clk_mgr_internal *clk_mgr); int dcn35_smu_get_ips_supported(struct clk_mgr_internal *clk_mgr);
int dcn35_smu_get_dtbclk(struct clk_mgr_internal *clk_mgr); int dcn35_smu_get_dtbclk(struct clk_mgr_internal *clk_mgr);
int dcn35_smu_get_dprefclk(struct clk_mgr_internal *clk_mgr); int dcn35_smu_get_dprefclk(struct clk_mgr_internal *clk_mgr);
void dcn35_smu_write_ips_scratch(struct clk_mgr_internal *clk_mgr, uint32_t param);
uint32_t dcn35_smu_read_ips_scratch(struct clk_mgr_internal *clk_mgr);
#endif /* DAL_DC_35_SMU_H_ */ #endif /* DAL_DC_35_SMU_H_ */
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
View file @ fbc836cd
...@@ -1336,22 +1336,6 @@ void dcn35_optimize_bandwidth( ...@@ -1336,22 +1336,6 @@ void dcn35_optimize_bandwidth(
} }
} }
void dcn35_set_idle_state(const struct dc *dc, bool allow_idle)
{
// TODO: Find a more suitable communcation
if (dc->clk_mgr->funcs->set_idle_state)
dc->clk_mgr->funcs->set_idle_state(dc->clk_mgr, allow_idle);
}
uint32_t dcn35_get_idle_state(const struct dc *dc)
{
// TODO: Find a more suitable communcation
if (dc->clk_mgr->funcs->get_idle_state)
return dc->clk_mgr->funcs->get_idle_state(dc->clk_mgr);
return 0;
}
void dcn35_set_drr(struct pipe_ctx **pipe_ctx, void dcn35_set_drr(struct pipe_ctx **pipe_ctx,
int num_pipes, struct dc_crtc_timing_adjust adjust) int num_pipes, struct dc_crtc_timing_adjust adjust)
{ {
......
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h
View file @ fbc836cd
...@@ -84,9 +84,6 @@ void dcn35_dsc_pg_control( ...@@ -84,9 +84,6 @@ void dcn35_dsc_pg_control(
unsigned int dsc_inst, unsigned int dsc_inst,
bool power_on); bool power_on);
void dcn35_set_idle_state(const struct dc *dc, bool allow_idle);
uint32_t dcn35_get_idle_state(const struct dc *dc);
void dcn35_set_drr(struct pipe_ctx **pipe_ctx, void dcn35_set_drr(struct pipe_ctx **pipe_ctx,
int num_pipes, struct dc_crtc_timing_adjust adjust); int num_pipes, struct dc_crtc_timing_adjust adjust);
......
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c
View file @ fbc836cd
...@@ -121,8 +121,6 @@ static const struct hw_sequencer_funcs dcn35_funcs = { ...@@ -121,8 +121,6 @@ static const struct hw_sequencer_funcs dcn35_funcs = {
.hw_block_power_up = dcn35_hw_block_power_up, .hw_block_power_up = dcn35_hw_block_power_up,
.hw_block_power_down = dcn35_hw_block_power_down, .hw_block_power_down = dcn35_hw_block_power_down,
.root_clock_control = dcn35_root_clock_control, .root_clock_control = dcn35_root_clock_control,
.set_idle_state = dcn35_set_idle_state,
.get_idle_state = dcn35_get_idle_state,
.set_long_vtotal = dcn35_set_long_vblank, .set_long_vtotal = dcn35_set_long_vblank,
}; };
......
drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
View file @ fbc836cd
...@@ -120,8 +120,6 @@ static const struct hw_sequencer_funcs dcn351_funcs = { ...@@ -120,8 +120,6 @@ static const struct hw_sequencer_funcs dcn351_funcs = {
.hw_block_power_up = dcn35_hw_block_power_up, .hw_block_power_up = dcn35_hw_block_power_up,
.hw_block_power_down = dcn35_hw_block_power_down, .hw_block_power_down = dcn35_hw_block_power_down,
.root_clock_control = dcn35_root_clock_control, .root_clock_control = dcn35_root_clock_control,
.set_idle_state = dcn35_set_idle_state,
.get_idle_state = dcn35_get_idle_state
}; };
static const struct hwseq_private_funcs dcn351_private_funcs = { static const struct hwseq_private_funcs dcn351_private_funcs = {
......
drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
View file @ fbc836cd
...@@ -424,8 +424,6 @@ struct hw_sequencer_funcs { ...@@ -424,8 +424,6 @@ struct hw_sequencer_funcs {
struct pg_block_update *update_state); struct pg_block_update *update_state);
void (*root_clock_control)(struct dc *dc, void (*root_clock_control)(struct dc *dc,
struct pg_block_update *update_state, bool power_on); struct pg_block_update *update_state, bool power_on);
void (*set_idle_state)(const struct dc *dc, bool allow_idle);
uint32_t (*get_idle_state)(const struct dc *dc);
bool (*is_pipe_topology_transition_seamless)(struct dc *dc, bool (*is_pipe_topology_transition_seamless)(struct dc *dc,
const struct dc_state *cur_ctx, const struct dc_state *cur_ctx,
const struct dc_state *new_ctx); const struct dc_state *new_ctx);
......
drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
View file @ fbc836cd
...@@ -281,8 +281,6 @@ struct clk_mgr_funcs { ...@@ -281,8 +281,6 @@ struct clk_mgr_funcs {
void (*set_low_power_state)(struct clk_mgr *clk_mgr); void (*set_low_power_state)(struct clk_mgr *clk_mgr);
void (*exit_low_power_state)(struct clk_mgr *clk_mgr); void (*exit_low_power_state)(struct clk_mgr *clk_mgr);
bool (*is_ips_supported)(struct clk_mgr *clk_mgr); bool (*is_ips_supported)(struct clk_mgr *clk_mgr);
void (*set_idle_state)(struct clk_mgr *clk_mgr, bool allow_idle);
uint32_t (*get_idle_state)(struct clk_mgr *clk_mgr);
void (*init_clocks)(struct clk_mgr *clk_mgr); void (*init_clocks)(struct clk_mgr *clk_mgr);
......
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