Commit fbf461d1 authored by Priit Laes's avatar Priit Laes Committed by Greg Kroah-Hartman

staging: fbtft: Use standard MIPI DCS command defines for hx8353d

This patch makes use of the standard MIPI Display Command Set to remove
some of the magic constants found in source code.
Signed-off-by: default avatarPriit Laes <plaes@plaes.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent fd59f106
...@@ -19,6 +19,7 @@ ...@@ -19,6 +19,7 @@
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/delay.h> #include <linux/delay.h>
#include <video/mipi_display.h>
#include "fbtft.h" #include "fbtft.h"
...@@ -47,17 +48,17 @@ static int init_display(struct fbtft_par *par) ...@@ -47,17 +48,17 @@ static int init_display(struct fbtft_par *par)
write_reg(par, 0x3A, 0x05); write_reg(par, 0x3A, 0x05);
/* MEM ACCESS */ /* MEM ACCESS */
write_reg(par, 0x36, 0xC0); write_reg(par, MIPI_DCS_SET_ADDRESS_MODE, 0xC0);
/* SLPOUT - Sleep out & booster on */ /* SLPOUT - Sleep out & booster on */
write_reg(par, 0x11); write_reg(par, MIPI_DCS_EXIT_SLEEP_MODE);
mdelay(150); mdelay(150);
/* DISPON - Display On */ /* DISPON - Display On */
write_reg(par, 0x29); write_reg(par, MIPI_DCS_SET_DISPLAY_ON);
/* RGBSET */ /* RGBSET */
write_reg(par, 0x2D, write_reg(par, MIPI_DCS_WRITE_LUT,
0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30,
32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62,
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
...@@ -95,16 +96,20 @@ static int set_var(struct fbtft_par *par) ...@@ -95,16 +96,20 @@ static int set_var(struct fbtft_par *par)
rgb-bgr order color filter panel: 0=rgb, 1=bgr */ rgb-bgr order color filter panel: 0=rgb, 1=bgr */
switch (par->info->var.rotate) { switch (par->info->var.rotate) {
case 0: case 0:
write_reg(par, 0x36, mx | my | (par->bgr << 3)); write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
mx | my | (par->bgr << 3));
break; break;
case 270: case 270:
write_reg(par, 0x36, my | mv | (par->bgr << 3)); write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
my | mv | (par->bgr << 3));
break; break;
case 180: case 180:
write_reg(par, 0x36, par->bgr << 3); write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
par->bgr << 3);
break; break;
case 90: case 90:
write_reg(par, 0x36, mx | mv | (par->bgr << 3)); write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
mx | mv | (par->bgr << 3));
break; break;
} }
......
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