dt-bindings: mmc: sdhci-of-dwcmhsc: Add Sophgo SG2042 support
SG2042 use Synopsys dwcnshc IP for SD/eMMC controllers. SG2042 defines 3 clocks for SD/eMMC controllers. - EMMC_100M/SD_100M for cclk(Card clocks in DWC_mshc), so reuse existing "core". - AXI_EMMC/AXI_SD for aclk/hclk(Bus interface clocks in DWC_mshc) and blck(Core Base Clock in DWC_mshc), these 3 clocks share one source, so reuse existing "bus". - 100K_EMMC/100K_SD for cqetmclk(Timer clocks in DWC_mshc), so reuse existing "timer" which was added for rockchip specified. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/9ca450097e5389a38bcd7d8ddf863766df4cea10.1722847198.git.unicorn_wang@outlook.comSigned-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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