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Commit fe53d144 authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 

Pull ARM SoC driver updates from Arnd Bergmann:
 "A number of new drivers get added this time, along with many
  low-priority bugfixes. The most interesting changes by subsystem are:

  bus drivers:
   - Updates to the Broadcom bus interface driver to support newer SoC
     types
   - The TI OMAP sysc driver now supports updated DT bindings

  memory controllers:
   - A new driver for Tegra186 gets added
   - A new driver for the ti-emif sram, to allow relocating
     suspend/resume handlers there

  SoC specific:
   - A new driver for Qualcomm QMI, the interface to the modem on MSM
     SoCs
   - A new driver for power domains on the actions S700 SoC
   - A driver for the Xilinx Zynq VCU logicoreIP

  reset controllers:
   - A new driver for Amlogic Meson-AGX
   - various bug fixes

  tee subsystem:
   - A new user interface got added to enable asynchronous communication
     with the TEE supplicant.
   - A new method of using user space memory for communication with the
     TEE is added"

* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (84 commits)
  of: platform: fix OF node refcount leak
  soc: fsl: guts: Add a NULL check for devm_kasprintf()
  bus: ti-sysc: Fix smartreflex sysc mask
  psci: add CPU_IDLE dependency
  soc: xilinx: Fix Kconfig alignment
  soc: xilinx: xlnx_vcu: Use bitwise & rather than logical && on clkoutdiv
  soc: xilinx: xlnx_vcu: Depends on HAS_IOMEM for xlnx_vcu
  soc: bcm: brcmstb: Be multi-platform compatible
  soc: brcmstb: biuctrl: exit without warning on non brcmstb platforms
  Revert "soc: brcmstb: Only register SoC device on STB platforms"
  bus: omap: add MODULE_LICENSE tags
  soc: brcmstb: Only register SoC device on STB platforms
  tee: shm: Potential NULL dereference calling tee_shm_register()
  soc: xilinx: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver
  dt-bindings: soc: xilinx: Add DT bindings to xlnx_vcu driver
  soc: xilinx: Create folder structure for soc specific drivers
  of: platform: populate /firmware/ node from of_platform_default_populate_init()
  soc: samsung: Add SPDX license identifiers
  soc: qcom: smp2p: Use common error handling code in qcom_smp2p_probe()
  tee: shm: don't put_page on null shm->pages
  ...
parents adbc128f 796543a6
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Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt
View file @ fe53d144
......@@ -17,21 +17,23 @@ Further, syscon nodes that map platform-specific registers used for general
system control is required:
- compatible: "brcm,bcm<chip_id>-sun-top-ctrl", "syscon"
- compatible: "brcm,bcm<chip_id>-hif-cpubiuctrl", "syscon"
- compatible: "brcm,bcm<chip_id>-cpu-biu-ctrl",
"brcm,brcmstb-cpu-biu-ctrl",
"syscon"
- compatible: "brcm,bcm<chip_id>-hif-continuation", "syscon"
hif-cpubiuctrl node
cpu-biu-ctrl node
-------------------
SoCs with Broadcom Brahma15 ARM-based CPUs have a specific Bus Interface Unit
(BIU) block which controls and interfaces the CPU complex to the different
Memory Controller Ports (MCP), one per memory controller (MEMC). This BIU block
offers a feature called Write Pairing which consists in collapsing two adjacent
cache lines into a single (bursted) write transaction towards the memory
controller (MEMC) to maximize write bandwidth.
SoCs with Broadcom Brahma15 ARM-based and Brahma53 ARM64-based CPUs have a
specific Bus Interface Unit (BIU) block which controls and interfaces the CPU
complex to the different Memory Controller Ports (MCP), one per memory
controller (MEMC). This BIU block offers a feature called Write Pairing which
consists in collapsing two adjacent cache lines into a single (bursted) write
transaction towards the memory controller (MEMC) to maximize write bandwidth.
Required properties:
- compatible: must be "brcm,bcm7445-hif-cpubiuctrl", "syscon"
- compatible: must be "brcm,bcm7445-cpu-biu-ctrl", "brcm,brcmstb-cpu-biu-ctrl", "syscon"
Optional properties:
......@@ -52,7 +54,7 @@ example:
};
hif_cpubiuctrl: syscon@3e2400 {
compatible = "brcm,bcm7445-hif-cpubiuctrl", "syscon";
compatible = "brcm,bcm7445-cpu-biu-ctrl", "brcm,brcmstb-cpu-biu-ctrl", "syscon";
reg = <0x3e2400 0x5b4>;
brcm,write-pairing;
};
......
Documentation/devicetree/bindings/arm/cpus.txt
View file @ fe53d144
......@@ -169,6 +169,7 @@ described below.
"arm,cortex-r5"
"arm,cortex-r7"
"brcm,brahma-b15"
"brcm,brahma-b53"
"brcm,vulcan"
"cavium,thunder"
"cavium,thunder2"
......
Documentation/devicetree/bindings/bus/ti-sysc.txt
View file @ fe53d144
......@@ -19,6 +19,7 @@ Required standard properties:
- compatible shall be one of the following generic types:
"ti,sysc"
"ti,sysc-omap2"
"ti,sysc-omap4"
"ti,sysc-omap4-simple"
......
Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
View file @ fe53d144
......@@ -23,6 +23,13 @@ Required properties:
the value shall be "emif<n>" where <n> is the number of the EMIF
instance with base 1.
Required only for "ti,emif-am3352" and "ti,emif-am4372":
- sram : Phandles for generic sram driver nodes,
first should be type 'protect-exec' for the driver to use to copy
and run PM functions, second should be regular pool to be used for
data region for code. See Documentation/devicetree/bindings/sram/sram.txt
for more details.
Optional properties:
- cs1-used : Have this property if CS1 of this EMIF
instance has a memory part attached to it. If there is a memory
......@@ -44,7 +51,7 @@ Optional properties:
- hw-caps-temp-alert : Have this property if the controller
has capability for generating SDRAM temperature alerts
Example:
-Examples:
emif1: emif@4c000000 {
compatible = "ti,emif-4d";
......@@ -56,3 +63,11 @@ emif1: emif@4c000000 {
hw-caps-ll-interface;
hw-caps-temp-alert;
};
/* From am33xx.dtsi */
emif: emif@4c000000 {
compatible = "ti,emif-am3352";
reg = <0x4C000000 0x1000>;
sram = <&pm_sram_code
&pm_sram_data>;
};
Documentation/devicetree/bindings/power/fsl,imx-gpc.txt
View file @ fe53d144
......@@ -9,6 +9,7 @@ Required properties:
- fsl,imx6q-gpc
- fsl,imx6qp-gpc
- fsl,imx6sl-gpc
- fsl,imx6sx-gpc
- reg: should be register base and length as documented in the
datasheet
- interrupts: Should contain one interrupt specifier for the GPC interrupt
......@@ -29,6 +30,8 @@ Required properties:
PU_DOMAIN 1
The following additional DOMAIN_INDEX value is valid for i.MX6SL:
DISPLAY_DOMAIN 2
The following additional DOMAIN_INDEX value is valid for i.MX6SX:
PCI_DOMAIN 3
- #power-domain-cells: Should be 0
......
Documentation/devicetree/bindings/reset/amlogic,meson-reset.txt
View file @ fe53d144
......@@ -5,7 +5,8 @@ Please also refer to reset.txt in this directory for common reset
controller binding usage.
Required properties:
- compatible: Should be "amlogic,meson8b-reset" or "amlogic,meson-gxbb-reset"
- compatible: Should be "amlogic,meson8b-reset", "amlogic,meson-gxbb-reset" or
"amlogic,meson-axg-reset".
- reg: should contain the register address base
- #reset-cells: 1, see below
......
Documentation/devicetree/bindings/soc/qcom/qcom,smp2p.txt
View file @ fe53d144
......@@ -17,9 +17,15 @@ processor ID) and a string identifier.
Value type: <prop-encoded-array>
Definition: one entry specifying the smp2p notification interrupt
- qcom,ipc:
- mboxes:
Usage: required
Value type: <prop-encoded-array>
Definition: reference to the associated doorbell in APCS, as described
in mailbox/mailbox.txt
- qcom,ipc:
Usage: required, unless mboxes is specified
Value type: <prop-encoded-array>
Definition: three entries specifying the outgoing ipc bit used for
signaling the remote end of the smp2p edge:
- phandle to a syscon node representing the apcs registers
......
Documentation/devicetree/bindings/soc/xilinx/xlnx,vcu.txt 0 → 100644
View file @ fe53d144
LogicoreIP designed compatible with Xilinx ZYNQ family.
-------------------------------------------------------
General concept
---------------
LogicoreIP design to provide the isolation between processing system
and programmable logic. Also provides the list of register set to configure
the frequency.
Required properties:
- compatible: shall be one of:
"xlnx,vcu"
"xlnx,vcu-logicoreip-1.0"
- reg, reg-names: There are two sets of registers need to provide.
1. vcu slcr
2. Logicore
reg-names should contain name for the each register sequence.
- clocks: phandle for aclk and pll_ref clocksource
- clock-names: The identification string, "aclk", is always required for
the axi clock. "pll_ref" is required for pll.
Example:
xlnx_vcu: vcu@a0040000 {
compatible = "xlnx,vcu-logicoreip-1.0";
reg = <0x0 0xa0040000 0x0 0x1000>,
<0x0 0xa0041000 0x0 0x1000>;
reg-names = "vcu_slcr", "logicore";
clocks = <&si570_1>, <&clkc 71>;
clock-names = "pll_ref", "aclk";
};
arch/arm/boot/dts/dra7.dtsi
View file @ fe53d144
......@@ -1523,7 +1523,7 @@ usb3_phy1: phy@4a084400 {
};
target-module@4a0dd000 {
compatible = "ti,sysc-omap4-sr";
compatible = "ti,sysc-omap4-sr", "ti,sysc";
ti,hwmods = "smartreflex_core";
reg = <0x4a0dd038 0x4>;
reg-names = "sysc";
......@@ -1542,7 +1542,7 @@ target-module@4a0dd000 {
};
target-module@4a0d9000 {
compatible = "ti,sysc-omap4-sr";
compatible = "ti,sysc-omap4-sr", "ti,sysc";
ti,hwmods = "smartreflex_mpu";
reg = <0x4a0d9038 0x4>;
reg-names = "sysc";
......
arch/arm/boot/dts/omap4.dtsi
View file @ fe53d144
......@@ -395,7 +395,7 @@ gpio6: gpio@4805d000 {
};
target-module@48076000 {
compatible = "ti,sysc-omap4";
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "slimbus2";
reg = <0x48076000 0x4>,
<0x48076010 0x4>;
......@@ -475,7 +475,7 @@ uart4: serial@4806e000 {
};
target-module@4a0db000 {
compatible = "ti,sysc-sr";
compatible = "ti,sysc-omap4-sr", "ti,sysc";
ti,hwmods = "smartreflex_iva";
reg = <0x4a0db038 0x4>;
reg-names = "sysc";
......@@ -498,7 +498,7 @@ smartreflex_iva: smartreflex@0 {
};
target-module@4a0dd000 {
compatible = "ti,sysc-sr";
compatible = "ti,sysc-omap4-sr", "ti,sysc";
ti,hwmods = "smartreflex_core";
reg = <0x4a0dd038 0x4>;
reg-names = "sysc";
......@@ -521,7 +521,7 @@ smartreflex_core: smartreflex@0 {
};
target-module@4a0d9000 {
compatible = "ti,sysc-sr";
compatible = "ti,sysc-omap4-sr", "ti,sysc";
ti,hwmods = "smartreflex_mpu";
reg = <0x4a0d9038 0x4>;
reg-names = "sysc";
......@@ -747,7 +747,7 @@ mmu_dsp: mmu@4a066000 {
};
target-module@52000000 {
compatible = "ti,sysc-omap4";
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "iss";
reg = <0x52000000 0x4>,
<0x52000010 0x4>;
......@@ -866,7 +866,7 @@ mcbsp3: mcbsp@40126000 {
};
target-module@40128000 {
compatible = "ti,sysc-mcasp";
compatible = "ti,sysc-mcasp", "ti,sysc";
ti,hwmods = "mcasp";
reg = <0x40128000 0x4>,
<0x40128004 0x4>;
......@@ -891,7 +891,7 @@ target-module@40128000 {
};
target-module@4012c000 {
compatible = "ti,sysc-omap4";
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "slimbus1";
reg = <0x4012c000 0x4>,
<0x4012c010 0x4>;
......@@ -912,7 +912,7 @@ target-module@4012c000 {
};
target-module@401f1000 {
compatible = "ti,sysc-omap4";
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "aess";
reg = <0x401f1000 0x4>,
<0x401f1010 0x4>;
......@@ -1027,7 +1027,7 @@ mbox_dsp: mbox_dsp {
};
target-module@4a10a000 {
compatible = "ti,sysc-omap4";
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "fdif";
reg = <0x4a10a000 0x4>,
<0x4a10a010 0x4>;
......@@ -1266,7 +1266,7 @@ abb_iva: regulator-abb-iva {
};
target-module@56000000 {
compatible = "ti,sysc-omap4";
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "gpu";
reg = <0x5601fc00 0x4>,
<0x5601fc10 0x4>;
......
arch/arm/mach-bcm/brcmstb.c
View file @ fe53d144
......@@ -14,7 +14,6 @@
#include <linux/init.h>
#include <linux/irqchip.h>
#include <linux/of_platform.h>
#include <linux/soc/brcmstb/brcmstb.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
......@@ -38,7 +37,6 @@ u32 brcmstb_uart_config[3] = {
static void __init brcmstb_init_irq(void)
{
irqchip_init();
brcmstb_biuctrl_init();
}
static const char *const brcmstb_match[] __initconst = {
......
arch/arm/mach-omap2/omap_hwmod.c
View file @ fe53d144
......@@ -143,6 +143,8 @@
#include <linux/of_address.h>
#include <linux/bootmem.h>
#include <linux/platform_data/ti-sysc.h>
#include <asm/system_misc.h>
#include "clock.h"
......
arch/arm/mach-omap2/omap_hwmod.h
View file @ fe53d144
......@@ -37,9 +37,15 @@
struct omap_device;
extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type1;
extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2;
extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type3;
extern struct sysc_regbits omap_hwmod_sysc_type1;
extern struct sysc_regbits omap_hwmod_sysc_type2;
extern struct sysc_regbits omap_hwmod_sysc_type3;
extern struct sysc_regbits omap34xx_sr_sysc_fields;
extern struct sysc_regbits omap36xx_sr_sysc_fields;
extern struct sysc_regbits omap3_sham_sysc_fields;
extern struct sysc_regbits omap3xxx_aes_sysc_fields;
extern struct sysc_regbits omap_hwmod_sysc_type_mcasp;
extern struct sysc_regbits omap_hwmod_sysc_type_usb_host_fs;
/*
* OCP SYSCONFIG bit shifts/masks TYPE1. These are for IPs compliant
......@@ -284,26 +290,6 @@ struct omap_hwmod_ocp_if {
#define CLOCKACT_TEST_ICLK 0x2
#define CLOCKACT_TEST_NONE 0x3
/**
* struct omap_hwmod_sysc_fields - hwmod OCP_SYSCONFIG register field offsets.
* @midle_shift: Offset of the midle bit
* @clkact_shift: Offset of the clockactivity bit
* @sidle_shift: Offset of the sidle bit
* @enwkup_shift: Offset of the enawakeup bit
* @srst_shift: Offset of the softreset bit
* @autoidle_shift: Offset of the autoidle bit
* @dmadisable_shift: Offset of the dmadisable bit
*/
struct omap_hwmod_sysc_fields {
u8 midle_shift;
u8 clkact_shift;
u8 sidle_shift;
u8 enwkup_shift;
u8 srst_shift;
u8 autoidle_shift;
u8 dmadisable_shift;
};
/**
* struct omap_hwmod_class_sysconfig - hwmod class OCP_SYS* data
* @rev_offs: IP block revision register offset (from module base addr)
......@@ -335,7 +321,7 @@ struct omap_hwmod_class_sysconfig {
u32 sysc_offs;
u32 syss_offs;
u16 sysc_flags;
struct omap_hwmod_sysc_fields *sysc_fields;
struct sysc_regbits *sysc_fields;
u8 srst_udelay;
u8 idlemodes;
};
......
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
View file @ fe53d144
......@@ -1108,10 +1108,6 @@ static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
};
/* SR common */
static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
.clkact_shift = 20,
};
static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
.sysc_offs = 0x24,
.sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
......@@ -1124,11 +1120,6 @@ static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
.rev = 1,
};
static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
.sidle_shift = 24,
.enwkup_shift = 26,
};
static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
.sysc_offs = 0x38,
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
......@@ -2607,12 +2598,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = {
};
/* l4_core -> SHAM2 (SHA1/MD5) (similar to omap24xx) */
static struct omap_hwmod_sysc_fields omap3_sham_sysc_fields = {
.sidle_shift = 4,
.srst_shift = 1,
.autoidle_shift = 0,
};
static struct omap_hwmod_class_sysconfig omap3_sham_sysc = {
.rev_offs = 0x5c,
.sysc_offs = 0x60,
......@@ -2651,12 +2636,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = {
};
/* l4_core -> AES */
static struct omap_hwmod_sysc_fields omap3xxx_aes_sysc_fields = {
.sidle_shift = 6,
.srst_shift = 1,
.autoidle_shift = 0,
};
static struct omap_hwmod_class_sysconfig omap3_aes_sysc = {
.rev_offs = 0x44,
.sysc_offs = 0x48,
......
arch/arm/mach-omap2/omap_hwmod_44xx_data.c
View file @ fe53d144
......@@ -1658,10 +1658,6 @@ static struct omap_hwmod omap44xx_mailbox_hwmod = {
*/
/* The IP is not compliant to type1 / type2 scheme */
static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
.sidle_shift = 0,
};
static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
.sysc_offs = 0x0004,
.sysc_flags = SYSC_HAS_SIDLEMODE,
......@@ -2403,17 +2399,12 @@ static struct omap_hwmod omap44xx_slimbus2_hwmod = {
*/
/* The IP is not compliant to type1 / type2 scheme */
static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
.sidle_shift = 24,
.enwkup_shift = 26,
};
static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
.sysc_offs = 0x0038,
.sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type_smartreflex,
.sysc_fields = &omap36xx_sr_sysc_fields,
};
static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
......@@ -2844,12 +2835,6 @@ static struct omap_hwmod omap44xx_uart4_hwmod = {
*/
/* The IP is not compliant to type1 / type2 scheme */
static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
.midle_shift = 4,
.sidle_shift = 2,
.srst_shift = 1,
};
static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0210,
......
arch/arm/mach-omap2/omap_hwmod_7xx_data.c
View file @ fe53d144
......@@ -2055,17 +2055,12 @@ static struct omap_hwmod dra7xx_sata_hwmod = {
*/
/* The IP is not compliant to type1 / type2 scheme */
static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
.sidle_shift = 24,
.enwkup_shift = 26,
};
static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
.sysc_offs = 0x0038,
.sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type_smartreflex,
.sysc_fields = &omap36xx_sr_sysc_fields,
};
static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
......
arch/arm/mach-omap2/omap_hwmod_common_data.c
View file @ fe53d144
......@@ -16,6 +16,9 @@
* data and their integration with other OMAP modules and Linux.
*/
#include <linux/types.h>
#include <linux/platform_data/ti-sysc.h>
#include "omap_hwmod.h"
#include "omap_hwmod_common_data.h"
......@@ -27,7 +30,7 @@
* if the device ip is compliant with the original PRCM protocol
* defined for OMAP2420.
*/
struct omap_hwmod_sysc_fields omap_hwmod_sysc_type1 = {
struct sysc_regbits omap_hwmod_sysc_type1 = {
.midle_shift = SYSC_TYPE1_MIDLEMODE_SHIFT,
.clkact_shift = SYSC_TYPE1_CLOCKACTIVITY_SHIFT,
.sidle_shift = SYSC_TYPE1_SIDLEMODE_SHIFT,
......@@ -43,7 +46,7 @@ struct omap_hwmod_sysc_fields omap_hwmod_sysc_type1 = {
* device ip is compliant with the new PRCM protocol defined for new
* OMAP4 IPs.
*/
struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2 = {
struct sysc_regbits omap_hwmod_sysc_type2 = {
.midle_shift = SYSC_TYPE2_MIDLEMODE_SHIFT,
.sidle_shift = SYSC_TYPE2_SIDLEMODE_SHIFT,
.srst_shift = SYSC_TYPE2_SOFTRESET_SHIFT,
......@@ -54,7 +57,7 @@ struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2 = {
* struct omap_hwmod_sysc_type3 - TYPE3 sysconfig scheme.
* Used by some IPs on AM33xx
*/
struct omap_hwmod_sysc_fields omap_hwmod_sysc_type3 = {
struct sysc_regbits omap_hwmod_sysc_type3 = {
.midle_shift = SYSC_TYPE3_MIDLEMODE_SHIFT,
.sidle_shift = SYSC_TYPE3_SIDLEMODE_SHIFT,
};
......@@ -63,3 +66,34 @@ struct omap_dss_dispc_dev_attr omap2_3_dss_dispc_dev_attr = {
.manager_count = 2,
.has_framedonetv_irq = 0
};
struct sysc_regbits omap34xx_sr_sysc_fields = {
.clkact_shift = 20,
};
struct sysc_regbits omap36xx_sr_sysc_fields = {
.sidle_shift = 24,
.enwkup_shift = 26,
};
struct sysc_regbits omap3_sham_sysc_fields = {
.sidle_shift = 4,
.srst_shift = 1,
.autoidle_shift = 0,
};
struct sysc_regbits omap3xxx_aes_sysc_fields = {
.sidle_shift = 6,
.srst_shift = 1,
.autoidle_shift = 0,
};
struct sysc_regbits omap_hwmod_sysc_type_mcasp = {
.sidle_shift = 0,
};
struct sysc_regbits omap_hwmod_sysc_type_usb_host_fs = {
.midle_shift = 4,
.sidle_shift = 2,
.srst_shift = 1,
};
drivers/bus/omap_l3_noc.c
View file @ fe53d144
......@@ -375,3 +375,8 @@ static void __exit omap_l3_exit(void)
platform_driver_unregister(&omap_l3_driver);
}
module_exit(omap_l3_exit);
MODULE_AUTHOR("Santosh Shilimkar");
MODULE_AUTHOR("Sricharan R");
MODULE_DESCRIPTION("OMAP L3 Interconnect error handling driver");
MODULE_LICENSE("GPL v2");
drivers/bus/omap_l3_smx.c
View file @ fe53d144
......@@ -309,3 +309,9 @@ static void __exit omap3_l3_exit(void)
platform_driver_unregister(&omap3_l3_driver);
}
module_exit(omap3_l3_exit);
MODULE_AUTHOR("Felipe Balbi");
MODULE_AUTHOR("Santosh Shilimkar");
MODULE_AUTHOR("Sricharan R");
MODULE_DESCRIPTION("OMAP3XXX L3 Interconnect Driver");
MODULE_LICENSE("GPL");
drivers/bus/ti-sysc.c
View file @ fe53d144
This diff is collapsed.
drivers/firmware/Kconfig
View file @ fe53d144
......@@ -10,7 +10,7 @@ config ARM_PSCI_FW
config ARM_PSCI_CHECKER
bool "ARM PSCI checker"
depends on ARM_PSCI_FW && HOTPLUG_CPU && !TORTURE_TEST
depends on ARM_PSCI_FW && HOTPLUG_CPU && CPU_IDLE && !TORTURE_TEST
help
Run the PSCI checker during startup. This checks that hotplug and
suspend operations work correctly when using PSCI.
......
drivers/firmware/qcom_scm.c
View file @ fe53d144
......@@ -622,30 +622,6 @@ static struct platform_driver qcom_scm_driver = {
static int __init qcom_scm_init(void)
{
struct device_node *np, *fw_np;
int ret;
fw_np = of_find_node_by_name(NULL, "firmware");
if (!fw_np)
return -ENODEV;
np = of_find_matching_node(fw_np, qcom_scm_dt_match);
if (!np) {
of_node_put(fw_np);
return -ENODEV;
}
of_node_put(np);
ret = of_platform_populate(fw_np, qcom_scm_dt_match, NULL, NULL);
of_node_put(fw_np);
if (ret)
return ret;
return platform_driver_register(&qcom_scm_driver);
}
subsys_initcall(qcom_scm_init);
drivers/firmware/raspberrypi.c
View file @ fe53d144
......@@ -174,7 +174,7 @@ rpi_firmware_print_firmware_revision(struct rpi_firmware *fw)
if (ret == 0) {
struct tm tm;
time_to_tm(packet, 0, &tm);
time64_to_tm(packet, 0, &tm);
dev_info(fw->cl.dev,
"Attached to firmware from %04ld-%02d-%02d %02d:%02d\n",
......
drivers/firmware/ti_sci.c
View file @ fe53d144
......@@ -287,13 +287,13 @@ static void ti_sci_rx_callback(struct mbox_client *cl, void *m)
/* Is the message of valid length? */
if (mbox_msg->len > info->desc->max_msg_size) {
dev_err(dev, "Unable to handle %d xfer(max %d)\n",
dev_err(dev, "Unable to handle %zu xfer(max %d)\n",
mbox_msg->len, info->desc->max_msg_size);
ti_sci_dump_header_dbg(dev, hdr);
return;
}
if (mbox_msg->len < xfer->rx_len) {
dev_err(dev, "Recv xfer %d < expected %d length\n",
dev_err(dev, "Recv xfer %zu < expected %d length\n",
mbox_msg->len, xfer->rx_len);
ti_sci_dump_header_dbg(dev, hdr);
return;
......
drivers/iommu/tegra-smmu.c
View file @ fe53d144
......@@ -20,6 +20,12 @@
#include <soc/tegra/ahb.h>
#include <soc/tegra/mc.h>
struct tegra_smmu_group {
struct list_head list;
const struct tegra_smmu_group_soc *soc;
struct iommu_group *group;
};
struct tegra_smmu {
void __iomem *regs;
struct device *dev;
......@@ -27,6 +33,8 @@ struct tegra_smmu {
struct tegra_mc *mc;
const struct tegra_smmu_soc *soc;
struct list_head groups;
unsigned long pfn_mask;
unsigned long tlb_mask;
......@@ -703,19 +711,47 @@ static struct tegra_smmu *tegra_smmu_find(struct device_node *np)
return mc->smmu;
}
static int tegra_smmu_configure(struct tegra_smmu *smmu, struct device *dev,
struct of_phandle_args *args)
{
const struct iommu_ops *ops = smmu->iommu.ops;
int err;
err = iommu_fwspec_init(dev, &dev->of_node->fwnode, ops);
if (err < 0) {
dev_err(dev, "failed to initialize fwspec: %d\n", err);
return err;
}
err = ops->of_xlate(dev, args);
if (err < 0) {
dev_err(dev, "failed to parse SW group ID: %d\n", err);
iommu_fwspec_free(dev);
return err;
}
return 0;
}
static int tegra_smmu_add_device(struct device *dev)
{
struct device_node *np = dev->of_node;
struct tegra_smmu *smmu = NULL;
struct iommu_group *group;
struct of_phandle_args args;
unsigned int index = 0;
int err;
while (of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index,
&args) == 0) {
struct tegra_smmu *smmu;
smmu = tegra_smmu_find(args.np);
if (smmu) {
err = tegra_smmu_configure(smmu, dev, &args);
of_node_put(args.np);
if (err < 0)
return err;
/*
* Only a single IOMMU master interface is currently
* supported by the Linux kernel, so abort after the
......@@ -728,9 +764,13 @@ static int tegra_smmu_add_device(struct device *dev)
break;
}
of_node_put(args.np);
index++;
}
if (!smmu)
return -ENODEV;
group = iommu_group_get_for_dev(dev);
if (IS_ERR(group))
return PTR_ERR(group);
......@@ -751,6 +791,80 @@ static void tegra_smmu_remove_device(struct device *dev)
iommu_group_remove_device(dev);
}
static const struct tegra_smmu_group_soc *
tegra_smmu_find_group(struct tegra_smmu *smmu, unsigned int swgroup)
{
unsigned int i, j;
for (i = 0; i < smmu->soc->num_groups; i++)
for (j = 0; j < smmu->soc->groups[i].num_swgroups; j++)
if (smmu->soc->groups[i].swgroups[j] == swgroup)
return &smmu->soc->groups[i];
return NULL;
}
static struct iommu_group *tegra_smmu_group_get(struct tegra_smmu *smmu,
unsigned int swgroup)
{
const struct tegra_smmu_group_soc *soc;
struct tegra_smmu_group *group;
soc = tegra_smmu_find_group(smmu, swgroup);
if (!soc)
return NULL;
mutex_lock(&smmu->lock);
list_for_each_entry(group, &smmu->groups, list)
if (group->soc == soc) {
mutex_unlock(&smmu->lock);
return group->group;
}
group = devm_kzalloc(smmu->dev, sizeof(*group), GFP_KERNEL);
if (!group) {
mutex_unlock(&smmu->lock);
return NULL;
}
INIT_LIST_HEAD(&group->list);
group->soc = soc;
group->group = iommu_group_alloc();
if (IS_ERR(group->group)) {
devm_kfree(smmu->dev, group);
mutex_unlock(&smmu->lock);
return NULL;
}
list_add_tail(&group->list, &smmu->groups);
mutex_unlock(&smmu->lock);
return group->group;
}
static struct iommu_group *tegra_smmu_device_group(struct device *dev)
{
struct iommu_fwspec *fwspec = dev->iommu_fwspec;
struct tegra_smmu *smmu = dev->archdata.iommu;
struct iommu_group *group;
group = tegra_smmu_group_get(smmu, fwspec->ids[0]);
if (!group)
group = generic_device_group(dev);
return group;
}
static int tegra_smmu_of_xlate(struct device *dev,
struct of_phandle_args *args)
{
u32 id = args->args[0];
return iommu_fwspec_add_ids(dev, &id, 1);
}
static const struct iommu_ops tegra_smmu_ops = {
.capable = tegra_smmu_capable,
.domain_alloc = tegra_smmu_domain_alloc,
......@@ -759,12 +873,12 @@ static const struct iommu_ops tegra_smmu_ops = {
.detach_dev = tegra_smmu_detach_dev,
.add_device = tegra_smmu_add_device,
.remove_device = tegra_smmu_remove_device,
.device_group = generic_device_group,
.device_group = tegra_smmu_device_group,
.map = tegra_smmu_map,
.unmap = tegra_smmu_unmap,
.map_sg = default_iommu_map_sg,
.iova_to_phys = tegra_smmu_iova_to_phys,
.of_xlate = tegra_smmu_of_xlate,
.pgsize_bitmap = SZ_4K,
};
......@@ -913,6 +1027,7 @@ struct tegra_smmu *tegra_smmu_probe(struct device *dev,
if (!smmu->asids)
return ERR_PTR(-ENOMEM);
INIT_LIST_HEAD(&smmu->groups);
mutex_init(&smmu->lock);
smmu->regs = mc->regs;
......@@ -954,6 +1069,7 @@ struct tegra_smmu *tegra_smmu_probe(struct device *dev,
return ERR_PTR(err);
iommu_device_set_ops(&smmu->iommu, &tegra_smmu_ops);
iommu_device_set_fwnode(&smmu->iommu, dev->fwnode);
err = iommu_device_register(&smmu->iommu);
if (err) {
......
drivers/memory/Kconfig
View file @ fe53d144
......@@ -84,6 +84,16 @@ config OMAP_GPMC_DEBUG
bootloader or else the GPMC timings won't be identical with the
bootloader timings.
config TI_EMIF_SRAM
tristate "Texas Instruments EMIF SRAM driver"
depends on (SOC_AM33XX || SOC_AM43XX) && SRAM
help
This driver is for the EMIF module available on Texas Instruments
AM33XX and AM43XX SoCs and is required for PM. Certain parts of
the EMIF PM code must run from on-chip SRAM late in the suspend
sequence so this driver provides several relocatable PM functions
for the SoC PM code to use.
config MVEBU_DEVBUS
bool "Marvell EBU Device Bus Controller"
default y
......
drivers/memory/Makefile
View file @ fe53d144
......@@ -23,3 +23,11 @@ obj-$(CONFIG_DA8XX_DDRCTL) += da8xx-ddrctl.o
obj-$(CONFIG_SAMSUNG_MC) += samsung/
obj-$(CONFIG_TEGRA_MC) += tegra/
obj-$(CONFIG_TI_EMIF_SRAM) += ti-emif-sram.o
ti-emif-sram-objs := ti-emif-pm.o ti-emif-sram-pm.o
AFLAGS_ti-emif-sram-pm.o :=-Wa,-march=armv7-a
include drivers/memory/Makefile.asm-offsets
drivers/memory/ti-emif-sram-pm.o: include/generated/ti-emif-asm-offsets.h
drivers/memory/Makefile.asm-offsets 0 → 100644
View file @ fe53d144
drivers/memory/emif-asm-offsets.s: drivers/memory/emif-asm-offsets.c
$(call if_changed_dep,cc_s_c)
include/generated/ti-emif-asm-offsets.h: drivers/memory/emif-asm-offsets.s FORCE
$(call filechk,offsets,__TI_EMIF_ASM_OFFSETS_H__)
drivers/memory/emif-asm-offsets.c 0 → 100644
View file @ fe53d144
/*
* TI AM33XX EMIF PM Assembly Offsets
*
* Copyright (C) 2016-2017 Texas Instruments Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/ti-emif-sram.h>
int main(void)
{
DEFINE(EMIF_SDCFG_VAL_OFFSET,
offsetof(struct emif_regs_amx3, emif_sdcfg_val));
DEFINE(EMIF_TIMING1_VAL_OFFSET,
offsetof(struct emif_regs_amx3, emif_timing1_val));
DEFINE(EMIF_TIMING2_VAL_OFFSET,
offsetof(struct emif_regs_amx3, emif_timing2_val));
DEFINE(EMIF_TIMING3_VAL_OFFSET,
offsetof(struct emif_regs_amx3, emif_timing3_val));
DEFINE(EMIF_REF_CTRL_VAL_OFFSET,
offsetof(struct emif_regs_amx3, emif_ref_ctrl_val));
DEFINE(EMIF_ZQCFG_VAL_OFFSET,
offsetof(struct emif_regs_amx3, emif_zqcfg_val));
DEFINE(EMIF_PMCR_VAL_OFFSET,
offsetof(struct emif_regs_amx3, emif_pmcr_val));
DEFINE(EMIF_PMCR_SHDW_VAL_OFFSET,
offsetof(struct emif_regs_amx3, emif_pmcr_shdw_val));
DEFINE(EMIF_RD_WR_LEVEL_RAMP_CTRL_OFFSET,
offsetof(struct emif_regs_amx3, emif_rd_wr_level_ramp_ctrl));
DEFINE(EMIF_RD_WR_EXEC_THRESH_OFFSET,
offsetof(struct emif_regs_amx3, emif_rd_wr_exec_thresh));
DEFINE(EMIF_COS_CONFIG_OFFSET,
offsetof(struct emif_regs_amx3, emif_cos_config));
DEFINE(EMIF_PRIORITY_TO_COS_MAPPING_OFFSET,
offsetof(struct emif_regs_amx3, emif_priority_to_cos_mapping));
DEFINE(EMIF_CONNECT_ID_SERV_1_MAP_OFFSET,
offsetof(struct emif_regs_amx3, emif_connect_id_serv_1_map));
DEFINE(EMIF_CONNECT_ID_SERV_2_MAP_OFFSET,
offsetof(struct emif_regs_amx3, emif_connect_id_serv_2_map));
DEFINE(EMIF_OCP_CONFIG_VAL_OFFSET,
offsetof(struct emif_regs_amx3, emif_ocp_config_val));
DEFINE(EMIF_LPDDR2_NVM_TIM_OFFSET,
offsetof(struct emif_regs_amx3, emif_lpddr2_nvm_tim));
DEFINE(EMIF_LPDDR2_NVM_TIM_SHDW_OFFSET,
offsetof(struct emif_regs_amx3, emif_lpddr2_nvm_tim_shdw));
DEFINE(EMIF_DLL_CALIB_CTRL_VAL_OFFSET,
offsetof(struct emif_regs_amx3, emif_dll_calib_ctrl_val));
DEFINE(EMIF_DLL_CALIB_CTRL_VAL_SHDW_OFFSET,
offsetof(struct emif_regs_amx3, emif_dll_calib_ctrl_val_shdw));
DEFINE(EMIF_DDR_PHY_CTLR_1_OFFSET,
offsetof(struct emif_regs_amx3, emif_ddr_phy_ctlr_1));
DEFINE(EMIF_EXT_PHY_CTRL_VALS_OFFSET,
offsetof(struct emif_regs_amx3, emif_ext_phy_ctrl_vals));
DEFINE(EMIF_REGS_AMX3_SIZE, sizeof(struct emif_regs_amx3));
BLANK();
DEFINE(EMIF_PM_BASE_ADDR_VIRT_OFFSET,
offsetof(struct ti_emif_pm_data, ti_emif_base_addr_virt));
DEFINE(EMIF_PM_BASE_ADDR_PHYS_OFFSET,
offsetof(struct ti_emif_pm_data, ti_emif_base_addr_phys));
DEFINE(EMIF_PM_CONFIG_OFFSET,
offsetof(struct ti_emif_pm_data, ti_emif_sram_config));
DEFINE(EMIF_PM_REGS_VIRT_OFFSET,
offsetof(struct ti_emif_pm_data, regs_virt));
DEFINE(EMIF_PM_REGS_PHYS_OFFSET,
offsetof(struct ti_emif_pm_data, regs_phys));
DEFINE(EMIF_PM_DATA_SIZE, sizeof(struct ti_emif_pm_data));
BLANK();
DEFINE(EMIF_PM_SAVE_CONTEXT_OFFSET,
offsetof(struct ti_emif_pm_functions, save_context));
DEFINE(EMIF_PM_RESTORE_CONTEXT_OFFSET,
offsetof(struct ti_emif_pm_functions, restore_context));
DEFINE(EMIF_PM_ENTER_SR_OFFSET,
offsetof(struct ti_emif_pm_functions, enter_sr));
DEFINE(EMIF_PM_EXIT_SR_OFFSET,
offsetof(struct ti_emif_pm_functions, exit_sr));
DEFINE(EMIF_PM_ABORT_SR_OFFSET,
offsetof(struct ti_emif_pm_functions, abort_sr));
DEFINE(EMIF_PM_FUNCTIONS_SIZE, sizeof(struct ti_emif_pm_functions));
return 0;
}
drivers/memory/emif.h
View file @ fe53d144
......@@ -555,6 +555,9 @@
#define READ_LATENCY_SHDW_SHIFT 0
#define READ_LATENCY_SHDW_MASK (0x1f << 0)
#define EMIF_SRAM_AM33_REG_LAYOUT 0x00000000
#define EMIF_SRAM_AM43_REG_LAYOUT 0x00000001
#ifndef __ASSEMBLY__
/*
* Structure containing shadow of important registers in EMIF
......@@ -585,5 +588,19 @@ struct emif_regs {
u32 ext_phy_ctrl_3_shdw;
u32 ext_phy_ctrl_4_shdw;
};
struct ti_emif_pm_functions;
extern unsigned int ti_emif_sram;
extern unsigned int ti_emif_sram_sz;
extern struct ti_emif_pm_data ti_emif_pm_sram_data;
extern struct emif_regs_amx3 ti_emif_regs_amx3;
void ti_emif_save_context(void);
void ti_emif_restore_context(void);
void ti_emif_enter_sr(void);
void ti_emif_exit_sr(void);
void ti_emif_abort_sr(void);
#endif /* __ASSEMBLY__ */
#endif /* __EMIF_H */
drivers/memory/tegra/Makefile
View file @ fe53d144
......@@ -10,3 +10,4 @@ tegra-mc-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210.o
obj-$(CONFIG_TEGRA_MC) += tegra-mc.o
obj-$(CONFIG_TEGRA124_EMC) += tegra124-emc.o
obj-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186.o
drivers/memory/tegra/tegra114.c
View file @ fe53d144
......@@ -912,11 +912,26 @@ static const struct tegra_smmu_swgroup tegra114_swgroups[] = {
{ .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
};
static const unsigned int tegra114_group_display[] = {
TEGRA_SWGROUP_DC,
TEGRA_SWGROUP_DCB,
};
static const struct tegra_smmu_group_soc tegra114_groups[] = {
{
.name = "display",
.swgroups = tegra114_group_display,
.num_swgroups = ARRAY_SIZE(tegra114_group_display),
},
};
static const struct tegra_smmu_soc tegra114_smmu_soc = {
.clients = tegra114_mc_clients,
.num_clients = ARRAY_SIZE(tegra114_mc_clients),
.swgroups = tegra114_swgroups,
.num_swgroups = ARRAY_SIZE(tegra114_swgroups),
.groups = tegra114_groups,
.num_groups = ARRAY_SIZE(tegra114_groups),
.supports_round_robin_arbitration = false,
.supports_request_limit = false,
.num_tlb_lines = 32,
......
drivers/memory/tegra/tegra124.c
View file @ fe53d144
......@@ -999,12 +999,27 @@ static const struct tegra_smmu_swgroup tegra124_swgroups[] = {
{ .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
};
static const unsigned int tegra124_group_display[] = {
TEGRA_SWGROUP_DC,
TEGRA_SWGROUP_DCB,
};
static const struct tegra_smmu_group_soc tegra124_groups[] = {
{
.name = "display",
.swgroups = tegra124_group_display,
.num_swgroups = ARRAY_SIZE(tegra124_group_display),
},
};
#ifdef CONFIG_ARCH_TEGRA_124_SOC
static const struct tegra_smmu_soc tegra124_smmu_soc = {
.clients = tegra124_mc_clients,
.num_clients = ARRAY_SIZE(tegra124_mc_clients),
.swgroups = tegra124_swgroups,
.num_swgroups = ARRAY_SIZE(tegra124_swgroups),
.groups = tegra124_groups,
.num_groups = ARRAY_SIZE(tegra124_groups),
.supports_round_robin_arbitration = true,
.supports_request_limit = true,
.num_tlb_lines = 32,
......@@ -1029,6 +1044,8 @@ static const struct tegra_smmu_soc tegra132_smmu_soc = {
.num_clients = ARRAY_SIZE(tegra124_mc_clients),
.swgroups = tegra124_swgroups,
.num_swgroups = ARRAY_SIZE(tegra124_swgroups),
.groups = tegra124_groups,
.num_groups = ARRAY_SIZE(tegra124_groups),
.supports_round_robin_arbitration = true,
.supports_request_limit = true,
.num_tlb_lines = 32,
......
drivers/memory/tegra/tegra186.c 0 → 100644
View file @ fe53d144
This diff is collapsed.
drivers/memory/tegra/tegra210.c
View file @ fe53d144
......@@ -1059,11 +1059,26 @@ static const struct tegra_smmu_swgroup tegra210_swgroups[] = {
{ .name = "tsecb", .swgroup = TEGRA_SWGROUP_TSECB, .reg = 0xad4 },
};
static const unsigned int tegra210_group_display[] = {
TEGRA_SWGROUP_DC,
TEGRA_SWGROUP_DCB,
};
static const struct tegra_smmu_group_soc tegra210_groups[] = {
{
.name = "display",
.swgroups = tegra210_group_display,
.num_swgroups = ARRAY_SIZE(tegra210_group_display),
},
};
static const struct tegra_smmu_soc tegra210_smmu_soc = {
.clients = tegra210_mc_clients,
.num_clients = ARRAY_SIZE(tegra210_mc_clients),
.swgroups = tegra210_swgroups,
.num_swgroups = ARRAY_SIZE(tegra210_swgroups),
.groups = tegra210_groups,
.num_groups = ARRAY_SIZE(tegra210_groups),
.supports_round_robin_arbitration = true,
.supports_request_limit = true,
.num_tlb_lines = 32,
......
drivers/memory/tegra/tegra30.c
View file @ fe53d144
......@@ -934,11 +934,26 @@ static const struct tegra_smmu_swgroup tegra30_swgroups[] = {
{ .name = "isp", .swgroup = TEGRA_SWGROUP_ISP, .reg = 0x258 },
};
static const unsigned int tegra30_group_display[] = {
TEGRA_SWGROUP_DC,
TEGRA_SWGROUP_DCB,
};
static const struct tegra_smmu_group_soc tegra30_groups[] = {
{
.name = "display",
.swgroups = tegra30_group_display,
.num_swgroups = ARRAY_SIZE(tegra30_group_display),
},
};
static const struct tegra_smmu_soc tegra30_smmu_soc = {
.clients = tegra30_mc_clients,
.num_clients = ARRAY_SIZE(tegra30_mc_clients),
.swgroups = tegra30_swgroups,
.num_swgroups = ARRAY_SIZE(tegra30_swgroups),
.groups = tegra30_groups,
.num_groups = ARRAY_SIZE(tegra30_groups),
.supports_round_robin_arbitration = false,
.supports_request_limit = false,
.num_tlb_lines = 16,
......
drivers/memory/ti-emif-pm.c 0 → 100644
View file @ fe53d144
/*
* TI AM33XX SRAM EMIF Driver
*
* Copyright (C) 2016-2017 Texas Instruments Inc.
* Dave Gerlach
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/err.h>
#include <linux/genalloc.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/sram.h>
#include <linux/ti-emif-sram.h>
#include "emif.h"
#define TI_EMIF_SRAM_SYMBOL_OFFSET(sym) ((unsigned long)(sym) - \
(unsigned long)&ti_emif_sram)
#define EMIF_POWER_MGMT_WAIT_SELF_REFRESH_8192_CYCLES 0x00a0
struct ti_emif_data {
phys_addr_t ti_emif_sram_phys;
phys_addr_t ti_emif_sram_data_phys;
unsigned long ti_emif_sram_virt;
unsigned long ti_emif_sram_data_virt;
struct gen_pool *sram_pool_code;
struct gen_pool *sram_pool_data;
struct ti_emif_pm_data pm_data;
struct ti_emif_pm_functions pm_functions;
};
static struct ti_emif_data *emif_instance;
static u32 sram_suspend_address(struct ti_emif_data *emif_data,
unsigned long addr)
{
return (emif_data->ti_emif_sram_virt +
TI_EMIF_SRAM_SYMBOL_OFFSET(addr));
}
static phys_addr_t sram_resume_address(struct ti_emif_data *emif_data,
unsigned long addr)
{
return ((unsigned long)emif_data->ti_emif_sram_phys +
TI_EMIF_SRAM_SYMBOL_OFFSET(addr));
}
static void ti_emif_free_sram(struct ti_emif_data *emif_data)
{
gen_pool_free(emif_data->sram_pool_code, emif_data->ti_emif_sram_virt,
ti_emif_sram_sz);
gen_pool_free(emif_data->sram_pool_data,
emif_data->ti_emif_sram_data_virt,
sizeof(struct emif_regs_amx3));
}
static int ti_emif_alloc_sram(struct device *dev,
struct ti_emif_data *emif_data)
{
struct device_node *np = dev->of_node;
int ret;
emif_data->sram_pool_code = of_gen_pool_get(np, "sram", 0);
if (!emif_data->sram_pool_code) {
dev_err(dev, "Unable to get sram pool for ocmcram code\n");
return -ENODEV;
}
emif_data->ti_emif_sram_virt =
gen_pool_alloc(emif_data->sram_pool_code,
ti_emif_sram_sz);
if (!emif_data->ti_emif_sram_virt) {
dev_err(dev, "Unable to allocate code memory from ocmcram\n");
return -ENOMEM;
}
/* Save physical address to calculate resume offset during pm init */
emif_data->ti_emif_sram_phys =
gen_pool_virt_to_phys(emif_data->sram_pool_code,
emif_data->ti_emif_sram_virt);
/* Get sram pool for data section and allocate space */
emif_data->sram_pool_data = of_gen_pool_get(np, "sram", 1);
if (!emif_data->sram_pool_data) {
dev_err(dev, "Unable to get sram pool for ocmcram data\n");
ret = -ENODEV;
goto err_free_sram_code;
}
emif_data->ti_emif_sram_data_virt =
gen_pool_alloc(emif_data->sram_pool_data,
sizeof(struct emif_regs_amx3));
if (!emif_data->ti_emif_sram_data_virt) {
dev_err(dev, "Unable to allocate data memory from ocmcram\n");
ret = -ENOMEM;
goto err_free_sram_code;
}
/* Save physical address to calculate resume offset during pm init */
emif_data->ti_emif_sram_data_phys =
gen_pool_virt_to_phys(emif_data->sram_pool_data,
emif_data->ti_emif_sram_data_virt);
/*
* These functions are called during suspend path while MMU is
* still on so add virtual base to offset for absolute address
*/
emif_data->pm_functions.save_context =
sram_suspend_address(emif_data,
(unsigned long)ti_emif_save_context);
emif_data->pm_functions.enter_sr =
sram_suspend_address(emif_data,
(unsigned long)ti_emif_enter_sr);
emif_data->pm_functions.abort_sr =
sram_suspend_address(emif_data,
(unsigned long)ti_emif_abort_sr);
/*
* These are called during resume path when MMU is not enabled
* so physical address is used instead
*/
emif_data->pm_functions.restore_context =
sram_resume_address(emif_data,
(unsigned long)ti_emif_restore_context);
emif_data->pm_functions.exit_sr =
sram_resume_address(emif_data,
(unsigned long)ti_emif_exit_sr);
emif_data->pm_data.regs_virt =
(struct emif_regs_amx3 *)emif_data->ti_emif_sram_data_virt;
emif_data->pm_data.regs_phys = emif_data->ti_emif_sram_data_phys;
return 0;
err_free_sram_code:
gen_pool_free(emif_data->sram_pool_code, emif_data->ti_emif_sram_virt,
ti_emif_sram_sz);
return ret;
}
static int ti_emif_push_sram(struct device *dev, struct ti_emif_data *emif_data)
{
void *copy_addr;
u32 data_addr;
copy_addr = sram_exec_copy(emif_data->sram_pool_code,
(void *)emif_data->ti_emif_sram_virt,
&ti_emif_sram, ti_emif_sram_sz);
if (!copy_addr) {
dev_err(dev, "Cannot copy emif code to sram\n");
return -ENODEV;
}
data_addr = sram_suspend_address(emif_data,
(unsigned long)&ti_emif_pm_sram_data);
copy_addr = sram_exec_copy(emif_data->sram_pool_code,
(void *)data_addr,
&emif_data->pm_data,
sizeof(emif_data->pm_data));
if (!copy_addr) {
dev_err(dev, "Cannot copy emif data to code sram\n");
return -ENODEV;
}
return 0;
}
/*
* Due to Usage Note 3.1.2 "DDR3: JEDEC Compliance for Maximum
* Self-Refresh Command Limit" found in AM335x Silicon Errata
* (Document SPRZ360F Revised November 2013) we must configure
* the self refresh delay timer to 0xA (8192 cycles) to avoid
* generating too many refresh command from the EMIF.
*/
static void ti_emif_configure_sr_delay(struct ti_emif_data *emif_data)
{
writel(EMIF_POWER_MGMT_WAIT_SELF_REFRESH_8192_CYCLES,
(emif_data->pm_data.ti_emif_base_addr_virt +
EMIF_POWER_MANAGEMENT_CONTROL));
writel(EMIF_POWER_MGMT_WAIT_SELF_REFRESH_8192_CYCLES,
(emif_data->pm_data.ti_emif_base_addr_virt +
EMIF_POWER_MANAGEMENT_CTRL_SHDW));
}
/**
* ti_emif_copy_pm_function_table - copy mapping of pm funcs in sram
* @sram_pool: pointer to struct gen_pool where dst resides
* @dst: void * to address that table should be copied
*
* Returns 0 if success other error code if table is not available
*/
int ti_emif_copy_pm_function_table(struct gen_pool *sram_pool, void *dst)
{
void *copy_addr;
if (!emif_instance)
return -ENODEV;
copy_addr = sram_exec_copy(sram_pool, dst,
&emif_instance->pm_functions,
sizeof(emif_instance->pm_functions));
if (!copy_addr)
return -ENODEV;
return 0;
}
EXPORT_SYMBOL_GPL(ti_emif_copy_pm_function_table);
/**
* ti_emif_get_mem_type - return type for memory type in use
*
* Returns memory type value read from EMIF or error code if fails
*/
int ti_emif_get_mem_type(void)
{
unsigned long temp;
if (!emif_instance)
return -ENODEV;
temp = readl(emif_instance->pm_data.ti_emif_base_addr_virt +
EMIF_SDRAM_CONFIG);
temp = (temp & SDRAM_TYPE_MASK) >> SDRAM_TYPE_SHIFT;
return temp;
}
EXPORT_SYMBOL_GPL(ti_emif_get_mem_type);
static const struct of_device_id ti_emif_of_match[] = {
{ .compatible = "ti,emif-am3352", .data =
(void *)EMIF_SRAM_AM33_REG_LAYOUT, },
{ .compatible = "ti,emif-am4372", .data =
(void *)EMIF_SRAM_AM43_REG_LAYOUT, },
{},
};
MODULE_DEVICE_TABLE(of, ti_emif_of_match);
static int ti_emif_probe(struct platform_device *pdev)
{
int ret;
struct resource *res;
struct device *dev = &pdev->dev;
const struct of_device_id *match;
struct ti_emif_data *emif_data;
emif_data = devm_kzalloc(dev, sizeof(*emif_data), GFP_KERNEL);
if (!emif_data)
return -ENOMEM;
match = of_match_device(ti_emif_of_match, &pdev->dev);
if (!match)
return -ENODEV;
emif_data->pm_data.ti_emif_sram_config = (unsigned long)match->data;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
emif_data->pm_data.ti_emif_base_addr_virt = devm_ioremap_resource(dev,
res);
if (IS_ERR(emif_data->pm_data.ti_emif_base_addr_virt)) {
dev_err(dev, "could not ioremap emif mem\n");
ret = PTR_ERR(emif_data->pm_data.ti_emif_base_addr_virt);
return ret;
}
emif_data->pm_data.ti_emif_base_addr_phys = res->start;
ti_emif_configure_sr_delay(emif_data);
ret = ti_emif_alloc_sram(dev, emif_data);
if (ret)
return ret;
ret = ti_emif_push_sram(dev, emif_data);
if (ret)
goto fail_free_sram;
emif_instance = emif_data;
return 0;
fail_free_sram:
ti_emif_free_sram(emif_data);
return ret;
}
static int ti_emif_remove(struct platform_device *pdev)
{
struct ti_emif_data *emif_data = emif_instance;
emif_instance = NULL;
ti_emif_free_sram(emif_data);
return 0;
}
static struct platform_driver ti_emif_driver = {
.probe = ti_emif_probe,
.remove = ti_emif_remove,
.driver = {
.name = KBUILD_MODNAME,
.of_match_table = of_match_ptr(ti_emif_of_match),
},
};
module_platform_driver(ti_emif_driver);
MODULE_AUTHOR("Dave Gerlach <d-gerlach@ti.com>");
MODULE_DESCRIPTION("Texas Instruments SRAM EMIF driver");
MODULE_LICENSE("GPL v2");
drivers/memory/ti-emif-sram-pm.S 0 → 100644
View file @ fe53d144
This diff is collapsed.
drivers/of/platform.c
View file @ fe53d144
......@@ -513,6 +513,12 @@ static int __init of_platform_default_populate_init(void)
for_each_matching_node(node, reserved_mem_matches)
of_platform_device_create(node, NULL, NULL);
node = of_find_node_by_path("/firmware");
if (node) {
of_platform_populate(node, NULL, NULL, NULL);
of_node_put(node);
}
/* Populate everything else. */
of_platform_default_populate(NULL, NULL, NULL);
......
drivers/pcmcia/at91_cf.c
View file @ fe53d144
......@@ -236,10 +236,8 @@ static int at91_cf_dt_init(struct platform_device *pdev)
pdev->dev.platform_data = board;
mc = syscon_regmap_lookup_by_compatible("atmel,at91rm9200-sdramc");
if (IS_ERR(mc))
return PTR_ERR(mc);
return 0;
return PTR_ERR_OR_ZERO(mc);
}
#else
static int at91_cf_dt_init(struct platform_device *pdev)
......
drivers/reset/core.c
View file @ fe53d144
......@@ -566,17 +566,18 @@ EXPORT_SYMBOL_GPL(__devm_reset_control_get);
* device_reset - find reset controller associated with the device
* and perform reset
* @dev: device to be reset by the controller
* @optional: whether it is optional to reset the device
*
* Convenience wrapper for reset_control_get() and reset_control_reset().
* Convenience wrapper for __reset_control_get() and reset_control_reset().
* This is useful for the common case of devices with single, dedicated reset
* lines.
*/
int device_reset(struct device *dev)
int __device_reset(struct device *dev, bool optional)
{
struct reset_control *rstc;
int ret;
rstc = reset_control_get(dev, NULL);
rstc = __reset_control_get(dev, NULL, 0, 0, optional);
if (IS_ERR(rstc))
return PTR_ERR(rstc);
......@@ -586,7 +587,7 @@ int device_reset(struct device *dev)
return ret;
}
EXPORT_SYMBOL_GPL(device_reset);
EXPORT_SYMBOL_GPL(__device_reset);
/**
* APIs to manage an array of reset controls.
......
drivers/reset/reset-meson.c
View file @ fe53d144
......@@ -139,6 +139,8 @@ static const struct of_device_id meson_reset_dt_ids[] = {
.data = &meson_reset_meson8_ops, },
{ .compatible = "amlogic,meson-gxbb-reset",
.data = &meson_reset_gx_ops, },
{ .compatible = "amlogic,meson-axg-reset",
.data = &meson_reset_gx_ops, },
{ /* sentinel */ },
};
......
drivers/soc/Kconfig
View file @ fe53d144
......@@ -16,6 +16,7 @@ source "drivers/soc/tegra/Kconfig"
source "drivers/soc/ti/Kconfig"
source "drivers/soc/ux500/Kconfig"
source "drivers/soc/versatile/Kconfig"
source "drivers/soc/xilinx/Kconfig"
source "drivers/soc/zte/Kconfig"
endmenu
drivers/soc/Makefile
View file @ fe53d144
......@@ -23,4 +23,5 @@ obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-$(CONFIG_SOC_TI) += ti/
obj-$(CONFIG_ARCH_U8500) += ux500/
obj-$(CONFIG_PLAT_VERSATILE) += versatile/
obj-y += xilinx/
obj-$(CONFIG_ARCH_ZX) += zte/
drivers/soc/actions/owl-sps.c
View file @ fe53d144
......@@ -17,6 +17,7 @@
#include <linux/pm_domain.h>
#include <linux/soc/actions/owl-sps.h>
#include <dt-bindings/power/owl-s500-powergate.h>
#include <dt-bindings/power/owl-s700-powergate.h>
struct owl_sps_domain_info {
const char *name;
......@@ -203,8 +204,49 @@ static const struct owl_sps_info s500_sps_info = {
.domains = s500_sps_domains,
};
static const struct owl_sps_domain_info s700_sps_domains[] = {
[S700_PD_VDE] = {
.name = "VDE",
.pwr_bit = 0,
},
[S700_PD_VCE_SI] = {
.name = "VCE_SI",
.pwr_bit = 1,
},
[S700_PD_USB2_1] = {
.name = "USB2_1",
.pwr_bit = 2,
},
[S700_PD_HDE] = {
.name = "HDE",
.pwr_bit = 7,
},
[S700_PD_DMA] = {
.name = "DMA",
.pwr_bit = 8,
},
[S700_PD_DS] = {
.name = "DS",
.pwr_bit = 9,
},
[S700_PD_USB3] = {
.name = "USB3",
.pwr_bit = 10,
},
[S700_PD_USB2_0] = {
.name = "USB2_0",
.pwr_bit = 11,
},
};
static const struct owl_sps_info s700_sps_info = {
.num_domains = ARRAY_SIZE(s700_sps_domains),
.domains = s700_sps_domains,
};
static const struct of_device_id owl_sps_of_matches[] = {
{ .compatible = "actions,s500-sps", .data = &s500_sps_info },
{ .compatible = "actions,s700-sps", .data = &s700_sps_info },
{ }
};
......
drivers/soc/bcm/brcmstb/biuctrl.c
View file @ fe53d144
......@@ -21,11 +21,70 @@
#include <linux/syscore_ops.h>
#include <linux/soc/brcmstb/brcmstb.h>
#define CPU_CREDIT_REG_OFFSET 0x184
#define CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK 0x70000000
#define CPU_CREDIT_REG_MCPx_READ_CRED_MASK 0xf
#define CPU_CREDIT_REG_MCPx_WRITE_CRED_MASK 0xf
#define CPU_CREDIT_REG_MCPx_READ_CRED_SHIFT(x) ((x) * 8)
#define CPU_CREDIT_REG_MCPx_WRITE_CRED_SHIFT(x) (((x) * 8) + 4)
#define CPU_MCP_FLOW_REG_MCPx_RDBUFF_CRED_SHIFT(x) ((x) * 8)
#define CPU_MCP_FLOW_REG_MCPx_RDBUFF_CRED_MASK 0xff
#define CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_THRESHOLD_MASK 0xf
#define CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_MASK 0xf
#define CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_SHIFT 4
#define CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_ENABLE BIT(8)
static void __iomem *cpubiuctrl_base;
static bool mcp_wr_pairing_en;
static const int *cpubiuctrl_regs;
static inline u32 cbc_readl(int reg)
{
int offset = cpubiuctrl_regs[reg];
if (offset == -1)
return (u32)-1;
return readl_relaxed(cpubiuctrl_base + offset);
}
static inline void cbc_writel(u32 val, int reg)
{
int offset = cpubiuctrl_regs[reg];
if (offset == -1)
return;
writel_relaxed(val, cpubiuctrl_base + offset);
}
enum cpubiuctrl_regs {
CPU_CREDIT_REG = 0,
CPU_MCP_FLOW_REG,
CPU_WRITEBACK_CTRL_REG
};
static const int b15_cpubiuctrl_regs[] = {
[CPU_CREDIT_REG] = 0x184,
[CPU_MCP_FLOW_REG] = -1,
[CPU_WRITEBACK_CTRL_REG] = -1,
};
/* Odd cases, e.g: 7260 */
static const int b53_cpubiuctrl_no_wb_regs[] = {
[CPU_CREDIT_REG] = 0x0b0,
[CPU_MCP_FLOW_REG] = 0x0b4,
[CPU_WRITEBACK_CTRL_REG] = -1,
};
static const int b53_cpubiuctrl_regs[] = {
[CPU_CREDIT_REG] = 0x0b0,
[CPU_MCP_FLOW_REG] = 0x0b4,
[CPU_WRITEBACK_CTRL_REG] = 0x22c,
};
#define NUM_CPU_BIUCTRL_REGS 3
static int __init mcp_write_pairing_set(void)
{
......@@ -34,15 +93,15 @@ static int __init mcp_write_pairing_set(void)
if (!cpubiuctrl_base)
return -1;
creds = readl_relaxed(cpubiuctrl_base + CPU_CREDIT_REG_OFFSET);
creds = cbc_readl(CPU_CREDIT_REG);
if (mcp_wr_pairing_en) {
pr_info("MCP: Enabling write pairing\n");
writel_relaxed(creds | CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK,
cpubiuctrl_base + CPU_CREDIT_REG_OFFSET);
cbc_writel(creds | CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK,
CPU_CREDIT_REG);
} else if (creds & CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK) {
pr_info("MCP: Disabling write pairing\n");
writel_relaxed(creds & ~CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK,
cpubiuctrl_base + CPU_CREDIT_REG_OFFSET);
cbc_writel(creds & ~CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK,
CPU_CREDIT_REG);
} else {
pr_info("MCP: Write pairing already disabled\n");
}
......@@ -50,16 +109,63 @@ static int __init mcp_write_pairing_set(void)
return 0;
}
static int __init setup_hifcpubiuctrl_regs(void)
static const u32 b53_mach_compat[] = {
0x7268,
0x7271,
0x7278,
};
static void __init mcp_b53_set(void)
{
struct device_node *np;
int ret = 0;
unsigned int i;
u32 reg;
np = of_find_compatible_node(NULL, NULL, "brcm,brcmstb-cpu-biu-ctrl");
if (!np) {
pr_err("missing BIU control node\n");
return -ENODEV;
reg = brcmstb_get_family_id();
for (i = 0; i < ARRAY_SIZE(b53_mach_compat); i++) {
if (BRCM_ID(reg) == b53_mach_compat[i])
break;
}
if (i == ARRAY_SIZE(b53_mach_compat))
return;
/* Set all 3 MCP interfaces to 8 credits */
reg = cbc_readl(CPU_CREDIT_REG);
for (i = 0; i < 3; i++) {
reg &= ~(CPU_CREDIT_REG_MCPx_WRITE_CRED_MASK <<
CPU_CREDIT_REG_MCPx_WRITE_CRED_SHIFT(i));
reg &= ~(CPU_CREDIT_REG_MCPx_READ_CRED_MASK <<
CPU_CREDIT_REG_MCPx_READ_CRED_SHIFT(i));
reg |= 8 << CPU_CREDIT_REG_MCPx_WRITE_CRED_SHIFT(i);
reg |= 8 << CPU_CREDIT_REG_MCPx_READ_CRED_SHIFT(i);
}
cbc_writel(reg, CPU_CREDIT_REG);
/* Max out the number of in-flight Jwords reads on the MCP interface */
reg = cbc_readl(CPU_MCP_FLOW_REG);
for (i = 0; i < 3; i++)
reg |= CPU_MCP_FLOW_REG_MCPx_RDBUFF_CRED_MASK <<
CPU_MCP_FLOW_REG_MCPx_RDBUFF_CRED_SHIFT(i);
cbc_writel(reg, CPU_MCP_FLOW_REG);
/* Enable writeback throttling, set timeout to 128 cycles, 256 cycles
* threshold
*/
reg = cbc_readl(CPU_WRITEBACK_CTRL_REG);
reg |= CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_ENABLE;
reg &= ~CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_THRESHOLD_MASK;
reg &= ~(CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_MASK <<
CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_SHIFT);
reg |= 8;
reg |= 7 << CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_SHIFT;
cbc_writel(reg, CPU_WRITEBACK_CTRL_REG);
}
static int __init setup_hifcpubiuctrl_regs(struct device_node *np)
{
struct device_node *cpu_dn;
int ret = 0;
cpubiuctrl_base = of_iomap(np, 0);
if (!cpubiuctrl_base) {
......@@ -69,27 +175,56 @@ static int __init setup_hifcpubiuctrl_regs(void)
}
mcp_wr_pairing_en = of_property_read_bool(np, "brcm,write-pairing");
cpu_dn = of_get_cpu_node(0, NULL);
if (!cpu_dn) {
pr_err("failed to obtain CPU device node\n");
ret = -ENODEV;
goto out;
}
if (of_device_is_compatible(cpu_dn, "brcm,brahma-b15"))
cpubiuctrl_regs = b15_cpubiuctrl_regs;
else if (of_device_is_compatible(cpu_dn, "brcm,brahma-b53"))
cpubiuctrl_regs = b53_cpubiuctrl_regs;
else {
pr_err("unsupported CPU\n");
ret = -EINVAL;
}
of_node_put(cpu_dn);
if (BRCM_ID(brcmstb_get_family_id()) == 0x7260)
cpubiuctrl_regs = b53_cpubiuctrl_no_wb_regs;
out:
of_node_put(np);
return ret;
}
#ifdef CONFIG_PM_SLEEP
static u32 cpu_credit_reg_dump; /* for save/restore */
static u32 cpubiuctrl_reg_save[NUM_CPU_BIUCTRL_REGS];
static int brcmstb_cpu_credit_reg_suspend(void)
{
if (cpubiuctrl_base)
cpu_credit_reg_dump =
readl_relaxed(cpubiuctrl_base + CPU_CREDIT_REG_OFFSET);
unsigned int i;
if (!cpubiuctrl_base)
return 0;
for (i = 0; i < NUM_CPU_BIUCTRL_REGS; i++)
cpubiuctrl_reg_save[i] = cbc_readl(i);
return 0;
}
static void brcmstb_cpu_credit_reg_resume(void)
{
if (cpubiuctrl_base)
writel_relaxed(cpu_credit_reg_dump,
cpubiuctrl_base + CPU_CREDIT_REG_OFFSET);
unsigned int i;
if (!cpubiuctrl_base)
return;
for (i = 0; i < NUM_CPU_BIUCTRL_REGS; i++)
cbc_writel(cpubiuctrl_reg_save[i], i);
}
static struct syscore_ops brcmstb_cpu_credit_syscore_ops = {
......@@ -99,19 +234,30 @@ static struct syscore_ops brcmstb_cpu_credit_syscore_ops = {
#endif
void __init brcmstb_biuctrl_init(void)
static int __init brcmstb_biuctrl_init(void)
{
struct device_node *np;
int ret;
setup_hifcpubiuctrl_regs();
/* We might be running on a multi-platform kernel, don't make this a
* fatal error, just bail out early
*/
np = of_find_compatible_node(NULL, NULL, "brcm,brcmstb-cpu-biu-ctrl");
if (!np)
return 0;
setup_hifcpubiuctrl_regs(np);
ret = mcp_write_pairing_set();
if (ret) {
pr_err("MCP: Unable to disable write pairing!\n");
return;
return ret;
}
mcp_b53_set();
#ifdef CONFIG_PM_SLEEP
register_syscore_ops(&brcmstb_cpu_credit_syscore_ops);
#endif
return 0;
}
early_initcall(brcmstb_biuctrl_init);
drivers/soc/bcm/brcmstb/common.c
View file @ fe53d144
......@@ -66,24 +66,47 @@ static const struct of_device_id sun_top_ctrl_match[] = {
{ }
};
static int __init brcmstb_soc_device_init(void)
static int __init brcmstb_soc_device_early_init(void)
{
struct soc_device_attribute *soc_dev_attr;
struct soc_device *soc_dev;
struct device_node *sun_top_ctrl;
void __iomem *sun_top_ctrl_base;
int ret = 0;
/* We could be on a multi-platform kernel, don't make this fatal but
* bail out early
*/
sun_top_ctrl = of_find_matching_node(NULL, sun_top_ctrl_match);
if (!sun_top_ctrl)
return -ENODEV;
return ret;
sun_top_ctrl_base = of_iomap(sun_top_ctrl, 0);
if (!sun_top_ctrl_base)
return -ENODEV;
if (!sun_top_ctrl_base) {
ret = -ENODEV;
goto out;
}
family_id = readl(sun_top_ctrl_base);
product_id = readl(sun_top_ctrl_base + 0x4);
iounmap(sun_top_ctrl_base);
out:
of_node_put(sun_top_ctrl);
return ret;
}
early_initcall(brcmstb_soc_device_early_init);
static int __init brcmstb_soc_device_init(void)
{
struct soc_device_attribute *soc_dev_attr;
struct device_node *sun_top_ctrl;
struct soc_device *soc_dev;
int ret = 0;
/* We could be on a multi-platform kernel, don't make this fatal but
* bail out early
*/
sun_top_ctrl = of_find_matching_node(NULL, sun_top_ctrl_match);
if (!sun_top_ctrl)
return ret;
soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
if (!soc_dev_attr) {
......@@ -107,14 +130,10 @@ static int __init brcmstb_soc_device_init(void)
kfree(soc_dev_attr->soc_id);
kfree(soc_dev_attr->revision);
kfree(soc_dev_attr);
ret = -ENODEV;
goto out;
ret = -ENOMEM;
}
return 0;
out:
iounmap(sun_top_ctrl_base);
of_node_put(sun_top_ctrl);
return ret;
}
arch_initcall(brcmstb_soc_device_init);
drivers/soc/fsl/guts.c
View file @ fe53d144
......@@ -167,10 +167,16 @@ static int fsl_guts_probe(struct platform_device *pdev)
} else {
soc_dev_attr.family = devm_kasprintf(dev, GFP_KERNEL, "QorIQ");
}
if (!soc_dev_attr.family)
return -ENOMEM;
soc_dev_attr.soc_id = devm_kasprintf(dev, GFP_KERNEL,
"svr:0x%08x", svr);
if (!soc_dev_attr.soc_id)
return -ENOMEM;
soc_dev_attr.revision = devm_kasprintf(dev, GFP_KERNEL, "%d.%d",
(svr >> 4) & 0xf, svr & 0xf);
if (!soc_dev_attr.revision)
return -ENOMEM;
soc_dev = soc_device_register(&soc_dev_attr);
if (IS_ERR(soc_dev))
......@@ -214,6 +220,8 @@ static const struct of_device_id fsl_guts_of_match[] = {
{ .compatible = "fsl,ls1043a-dcfg", },
{ .compatible = "fsl,ls2080a-dcfg", },
{ .compatible = "fsl,ls1088a-dcfg", },
{ .compatible = "fsl,ls1012a-dcfg", },
{ .compatible = "fsl,ls1046a-dcfg", },
{}
};
MODULE_DEVICE_TABLE(of, fsl_guts_of_match);
......
drivers/soc/imx/gpc.c
View file @ fe53d144
......@@ -273,7 +273,15 @@ static struct imx_pm_domain imx_gpc_domains[] = {
},
.reg_offs = 0x240,
.cntr_pdn_bit = 4,
}
}, {
.base = {
.name = "PCI",
.power_off = imx6_pm_domain_power_off,
.power_on = imx6_pm_domain_power_on,
},
.reg_offs = 0x200,
.cntr_pdn_bit = 6,
},
};
struct imx_gpc_dt_data {
......@@ -296,10 +304,16 @@ static const struct imx_gpc_dt_data imx6sl_dt_data = {
.err009619_present = false,
};
static const struct imx_gpc_dt_data imx6sx_dt_data = {
.num_domains = 4,
.err009619_present = false,
};
static const struct of_device_id imx_gpc_dt_ids[] = {
{ .compatible = "fsl,imx6q-gpc", .data = &imx6q_dt_data },
{ .compatible = "fsl,imx6qp-gpc", .data = &imx6qp_dt_data },
{ .compatible = "fsl,imx6sl-gpc", .data = &imx6sl_dt_data },
{ .compatible = "fsl,imx6sx-gpc", .data = &imx6sx_dt_data },
{ }
};
......
drivers/soc/qcom/Kconfig
View file @ fe53d144
......@@ -35,6 +35,15 @@ config QCOM_PM
modes. It interface with various system drivers to put the cores in
low power modes.
config QCOM_QMI_HELPERS
tristate
depends on ARCH_QCOM
help
Helper library for handling QMI encoded messages. QMI encoded
messages are used in communication between the majority of QRTR
clients and this helpers provide the common functionality needed for
doing this from a kernel driver.
config QCOM_RMTFS_MEM
tristate "Qualcomm Remote Filesystem memory driver"
depends on ARCH_QCOM
......@@ -75,6 +84,7 @@ config QCOM_SMEM_STATE
config QCOM_SMP2P
tristate "Qualcomm Shared Memory Point to Point support"
depends on MAILBOX
depends on QCOM_SMEM
select QCOM_SMEM_STATE
help
......
drivers/soc/qcom/Makefile
View file @ fe53d144
......@@ -3,6 +3,8 @@ obj-$(CONFIG_QCOM_GLINK_SSR) += glink_ssr.o
obj-$(CONFIG_QCOM_GSBI) += qcom_gsbi.o
obj-$(CONFIG_QCOM_MDT_LOADER) += mdt_loader.o
obj-$(CONFIG_QCOM_PM) += spm.o
obj-$(CONFIG_QCOM_QMI_HELPERS) += qmi_helpers.o
qmi_helpers-y += qmi_encdec.o qmi_interface.o
obj-$(CONFIG_QCOM_RMTFS_MEM) += rmtfs_mem.o
obj-$(CONFIG_QCOM_SMD_RPM) += smd-rpm.o
obj-$(CONFIG_QCOM_SMEM) += smem.o
......
drivers/soc/qcom/qmi_encdec.c 0 → 100644
View file @ fe53d144
This diff is collapsed.
drivers/soc/qcom/qmi_interface.c 0 → 100644
View file @ fe53d144
This diff is collapsed.
drivers/soc/qcom/rmtfs_mem.c
View file @ fe53d144
......@@ -267,3 +267,7 @@ static void qcom_rmtfs_mem_exit(void)
unregister_chrdev_region(qcom_rmtfs_mem_major, QCOM_RMTFS_MEM_DEV_MAX);
}
module_exit(qcom_rmtfs_mem_exit);
MODULE_AUTHOR("Linaro Ltd");
MODULE_DESCRIPTION("Qualcomm Remote Filesystem memory driver");
MODULE_LICENSE("GPL v2");
drivers/soc/qcom/smp2p.c
View file @ fe53d144
......@@ -18,6 +18,7 @@
#include <linux/of.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/mailbox_client.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/platform_device.h>
......@@ -126,6 +127,8 @@ struct smp2p_entry {
* @ipc_regmap: regmap for the outbound ipc
* @ipc_offset: offset within the regmap
* @ipc_bit: bit in regmap@offset to kick to signal remote processor
* @mbox_client: mailbox client handle
* @mbox_chan: apcs ipc mailbox channel handle
* @inbound: list of inbound entries
* @outbound: list of outbound entries
*/
......@@ -146,6 +149,9 @@ struct qcom_smp2p {
int ipc_offset;
int ipc_bit;
struct mbox_client mbox_client;
struct mbox_chan *mbox_chan;
struct list_head inbound;
struct list_head outbound;
};
......@@ -154,7 +160,13 @@ static void qcom_smp2p_kick(struct qcom_smp2p *smp2p)
{
/* Make sure any updated data is written before the kick */
wmb();
if (smp2p->mbox_chan) {
mbox_send_message(smp2p->mbox_chan, NULL);
mbox_client_txdone(smp2p->mbox_chan, 0);
} else {
regmap_write(smp2p->ipc_regmap, smp2p->ipc_offset, BIT(smp2p->ipc_bit));
}
}
/**
......@@ -453,10 +465,6 @@ static int qcom_smp2p_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, smp2p);
ret = smp2p_parse_ipc(smp2p);
if (ret)
return ret;
key = "qcom,smem";
ret = of_property_read_u32_array(pdev->dev.of_node, key,
smp2p->smem_items, 2);
......@@ -465,17 +473,13 @@ static int qcom_smp2p_probe(struct platform_device *pdev)
key = "qcom,local-pid";
ret = of_property_read_u32(pdev->dev.of_node, key, &smp2p->local_pid);
if (ret < 0) {
dev_err(&pdev->dev, "failed to read %s\n", key);
return -EINVAL;
}
if (ret)
goto report_read_failure;
key = "qcom,remote-pid";
ret = of_property_read_u32(pdev->dev.of_node, key, &smp2p->remote_pid);
if (ret < 0) {
dev_err(&pdev->dev, "failed to read %s\n", key);
return -EINVAL;
}
if (ret)
goto report_read_failure;
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
......@@ -483,9 +487,23 @@ static int qcom_smp2p_probe(struct platform_device *pdev)
return irq;
}
smp2p->mbox_client.dev = &pdev->dev;
smp2p->mbox_client.knows_txdone = true;
smp2p->mbox_chan = mbox_request_channel(&smp2p->mbox_client, 0);
if (IS_ERR(smp2p->mbox_chan)) {
if (PTR_ERR(smp2p->mbox_chan) != -ENODEV)
return PTR_ERR(smp2p->mbox_chan);
smp2p->mbox_chan = NULL;
ret = smp2p_parse_ipc(smp2p);
if (ret)
return ret;
}
ret = qcom_smp2p_alloc_outbound_item(smp2p);
if (ret < 0)
return ret;
goto release_mbox;
for_each_available_child_of_node(pdev->dev.of_node, node) {
entry = devm_kzalloc(&pdev->dev, sizeof(*entry), GFP_KERNEL);
......@@ -540,7 +558,14 @@ static int qcom_smp2p_probe(struct platform_device *pdev)
smp2p->out->valid_entries = 0;
release_mbox:
mbox_free_channel(smp2p->mbox_chan);
return ret;
report_read_failure:
dev_err(&pdev->dev, "failed to read %s\n", key);
return -EINVAL;
}
static int qcom_smp2p_remove(struct platform_device *pdev)
......@@ -554,6 +579,8 @@ static int qcom_smp2p_remove(struct platform_device *pdev)
list_for_each_entry(entry, &smp2p->outbound, node)
qcom_smem_state_unregister(entry->state);
mbox_free_channel(smp2p->mbox_chan);
smp2p->out->valid_entries = 0;
return 0;
......
drivers/soc/qcom/smsm.c
View file @ fe53d144
......@@ -496,8 +496,10 @@ static int qcom_smsm_probe(struct platform_device *pdev)
if (!smsm->hosts)
return -ENOMEM;
local_node = of_find_node_with_property(of_node_get(pdev->dev.of_node),
"#qcom,smem-state-cells");
for_each_child_of_node(pdev->dev.of_node, local_node) {
if (of_find_property(local_node, "#qcom,smem-state-cells", NULL))
break;
}
if (!local_node) {
dev_err(&pdev->dev, "no state entry\n");
return -EINVAL;
......
drivers/soc/samsung/Kconfig
View file @ fe53d144
# SPDX-License-Identifier: GPL-2.0
#
# SAMSUNG SoC drivers
#
......
drivers/soc/samsung/Makefile
View file @ fe53d144
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_EXYNOS_PMU) += exynos-pmu.o
obj-$(CONFIG_EXYNOS_PMU_ARM_DRIVERS) += exynos3250-pmu.o exynos4-pmu.o \
......
drivers/soc/samsung/exynos-pmu.c
View file @ fe53d144
/*
* Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* EXYNOS - CPU PMU(Power Management Unit) support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
// http://www.samsung.com/
//
// EXYNOS - CPU PMU(Power Management Unit) support
#include <linux/of.h>
#include <linux/of_address.h>
......
drivers/soc/samsung/exynos-pmu.h
View file @ fe53d144
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2015 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Header for EXYNOS PMU Driver support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __EXYNOS_PMU_H
......
drivers/soc/samsung/exynos3250-pmu.c
View file @ fe53d144
/*
* Copyright (c) 2011-2015 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* EXYNOS3250 - CPU PMU (Power Management Unit) support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (c) 2011-2015 Samsung Electronics Co., Ltd.
// http://www.samsung.com/
//
// EXYNOS3250 - CPU PMU (Power Management Unit) support
#include <linux/soc/samsung/exynos-regs-pmu.h>
#include <linux/soc/samsung/exynos-pmu.h>
......
drivers/soc/samsung/exynos4-pmu.c
View file @ fe53d144
/*
* Copyright (c) 2011-2015 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* EXYNOS4 - CPU PMU(Power Management Unit) support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (c) 2011-2015 Samsung Electronics Co., Ltd.
// http://www.samsung.com/
//
// EXYNOS4 - CPU PMU(Power Management Unit) support
#include <linux/soc/samsung/exynos-regs-pmu.h>
#include <linux/soc/samsung/exynos-pmu.h>
......
drivers/soc/samsung/exynos5250-pmu.c
View file @ fe53d144
/*
* Copyright (c) 2011-2015 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* EXYNOS5250 - CPU PMU (Power Management Unit) support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (c) 2011-2015 Samsung Electronics Co., Ltd.
// http://www.samsung.com/
//
// EXYNOS5250 - CPU PMU (Power Management Unit) support
#include <linux/soc/samsung/exynos-regs-pmu.h>
#include <linux/soc/samsung/exynos-pmu.h>
......
drivers/soc/samsung/exynos5420-pmu.c
View file @ fe53d144
/*
* Copyright (c) 2011-2015 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* EXYNOS5420 - CPU PMU (Power Management Unit) support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (c) 2011-2015 Samsung Electronics Co., Ltd.
// http://www.samsung.com/
//
// EXYNOS5420 - CPU PMU (Power Management Unit) support
#include <linux/pm.h>
#include <linux/soc/samsung/exynos-regs-pmu.h>
......
drivers/soc/samsung/pm_domains.c
View file @ fe53d144
/*
* Exynos Generic power domain support.
*
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Implementation of Exynos specific power domain control which is used in
* conjunction with runtime-pm. Support for both device-tree and non-device-tree
* based power domain support is included.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
// SPDX-License-Identifier: GPL-2.0
//
// Exynos Generic power domain support.
//
// Copyright (c) 2012 Samsung Electronics Co., Ltd.
// http://www.samsung.com
//
// Implementation of Exynos specific power domain control which is used in
// conjunction with runtime-pm. Support for both device-tree and non-device-tree
// based power domain support is included.
#include <linux/io.h>
#include <linux/err.h>
......
drivers/soc/ti/knav_qmss_queue.c
View file @ fe53d144
......@@ -225,7 +225,7 @@ static struct knav_queue *__knav_queue_open(struct knav_queue_inst *inst,
if (!knav_queue_is_busy(inst)) {
struct knav_range_info *range = inst->range;
inst->name = kstrndup(name, KNAV_NAME_SIZE, GFP_KERNEL);
inst->name = kstrndup(name, KNAV_NAME_SIZE - 1, GFP_KERNEL);
if (range->ops && range->ops->open_queue)
ret = range->ops->open_queue(range, inst, flags);
......@@ -779,7 +779,7 @@ void *knav_pool_create(const char *name,
goto err;
}
pool->name = kstrndup(name, KNAV_NAME_SIZE, GFP_KERNEL);
pool->name = kstrndup(name, KNAV_NAME_SIZE - 1, GFP_KERNEL);
pool->kdev = kdev;
pool->dev = kdev->dev;
......
drivers/soc/xilinx/Kconfig 0 → 100644
View file @ fe53d144
# SPDX-License-Identifier: GPL-2.0
menu "Xilinx SoC drivers"
config XILINX_VCU
tristate "Xilinx VCU logicoreIP Init"
depends on HAS_IOMEM
help
Provides the driver to enable and disable the isolation between the
processing system and programmable logic part by using the logicoreIP
register set. This driver also configures the frequency based on the
clock information from the logicoreIP register set.
If you say yes here you get support for the logicoreIP.
If unsure, say N.
To compile this driver as a module, choose M here: the
module will be called xlnx_vcu.
endmenu
drivers/soc/xilinx/Makefile 0 → 100644
View file @ fe53d144
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_XILINX_VCU) += xlnx_vcu.o
drivers/soc/xilinx/xlnx_vcu.c 0 → 100644
View file @ fe53d144
This diff is collapsed.
drivers/tee/optee/Makefile
View file @ fe53d144
......@@ -4,3 +4,4 @@ optee-objs += core.o
optee-objs += call.o
optee-objs += rpc.o
optee-objs += supp.o
optee-objs += shm_pool.o
drivers/tee/optee/call.c
View file @ fe53d144
......@@ -15,6 +15,7 @@
#include <linux/device.h>
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/tee_drv.h>
#include <linux/types.h>
......@@ -135,6 +136,7 @@ u32 optee_do_call_with_arg(struct tee_context *ctx, phys_addr_t parg)
struct optee *optee = tee_get_drvdata(ctx->teedev);
struct optee_call_waiter w;
struct optee_rpc_param param = { };
struct optee_call_ctx call_ctx = { };
u32 ret;
param.a0 = OPTEE_SMC_CALL_WITH_ARG;
......@@ -159,13 +161,14 @@ u32 optee_do_call_with_arg(struct tee_context *ctx, phys_addr_t parg)
param.a1 = res.a1;
param.a2 = res.a2;
param.a3 = res.a3;
optee_handle_rpc(ctx, &param);
optee_handle_rpc(ctx, &param, &call_ctx);
} else {
ret = res.a0;
break;
}
}
optee_rpc_finalize_call(&call_ctx);
/*
* We're done with our thread in secure world, if there's any
* thread waiters wake up one.
......@@ -442,3 +445,218 @@ void optee_disable_shm_cache(struct optee *optee)
}
optee_cq_wait_final(&optee->call_queue, &w);
}
#define PAGELIST_ENTRIES_PER_PAGE \
((OPTEE_MSG_NONCONTIG_PAGE_SIZE / sizeof(u64)) - 1)
/**
* optee_fill_pages_list() - write list of user pages to given shared
* buffer.
*
* @dst: page-aligned buffer where list of pages will be stored
* @pages: array of pages that represents shared buffer
* @num_pages: number of entries in @pages
* @page_offset: offset of user buffer from page start
*
* @dst should be big enough to hold list of user page addresses and
* links to the next pages of buffer
*/
void optee_fill_pages_list(u64 *dst, struct page **pages, int num_pages,
size_t page_offset)
{
int n = 0;
phys_addr_t optee_page;
/*
* Refer to OPTEE_MSG_ATTR_NONCONTIG description in optee_msg.h
* for details.
*/
struct {
u64 pages_list[PAGELIST_ENTRIES_PER_PAGE];
u64 next_page_data;
} *pages_data;
/*
* Currently OP-TEE uses 4k page size and it does not looks
* like this will change in the future. On other hand, there are
* no know ARM architectures with page size < 4k.
* Thus the next built assert looks redundant. But the following
* code heavily relies on this assumption, so it is better be
* safe than sorry.
*/
BUILD_BUG_ON(PAGE_SIZE < OPTEE_MSG_NONCONTIG_PAGE_SIZE);
pages_data = (void *)dst;
/*
* If linux page is bigger than 4k, and user buffer offset is
* larger than 4k/8k/12k/etc this will skip first 4k pages,
* because they bear no value data for OP-TEE.
*/
optee_page = page_to_phys(*pages) +
round_down(page_offset, OPTEE_MSG_NONCONTIG_PAGE_SIZE);
while (true) {
pages_data->pages_list[n++] = optee_page;
if (n == PAGELIST_ENTRIES_PER_PAGE) {
pages_data->next_page_data =
virt_to_phys(pages_data + 1);
pages_data++;
n = 0;
}
optee_page += OPTEE_MSG_NONCONTIG_PAGE_SIZE;
if (!(optee_page & ~PAGE_MASK)) {
if (!--num_pages)
break;
pages++;
optee_page = page_to_phys(*pages);
}
}
}
/*
* The final entry in each pagelist page is a pointer to the next
* pagelist page.
*/
static size_t get_pages_list_size(size_t num_entries)
{
int pages = DIV_ROUND_UP(num_entries, PAGELIST_ENTRIES_PER_PAGE);
return pages * OPTEE_MSG_NONCONTIG_PAGE_SIZE;
}
u64 *optee_allocate_pages_list(size_t num_entries)
{
return alloc_pages_exact(get_pages_list_size(num_entries), GFP_KERNEL);
}
void optee_free_pages_list(void *list, size_t num_entries)
{
free_pages_exact(list, get_pages_list_size(num_entries));
}
static bool is_normal_memory(pgprot_t p)
{
#if defined(CONFIG_ARM)
return (pgprot_val(p) & L_PTE_MT_MASK) == L_PTE_MT_WRITEALLOC;
#elif defined(CONFIG_ARM64)
return (pgprot_val(p) & PTE_ATTRINDX_MASK) == PTE_ATTRINDX(MT_NORMAL);
#else
#error "Unuspported architecture"
#endif
}
static int __check_mem_type(struct vm_area_struct *vma, unsigned long end)
{
while (vma && is_normal_memory(vma->vm_page_prot)) {
if (vma->vm_end >= end)
return 0;
vma = vma->vm_next;
}
return -EINVAL;
}
static int check_mem_type(unsigned long start, size_t num_pages)
{
struct mm_struct *mm = current->mm;
int rc;
down_read(&mm->mmap_sem);
rc = __check_mem_type(find_vma(mm, start),
start + num_pages * PAGE_SIZE);
up_read(&mm->mmap_sem);
return rc;
}
int optee_shm_register(struct tee_context *ctx, struct tee_shm *shm,
struct page **pages, size_t num_pages,
unsigned long start)
{
struct tee_shm *shm_arg = NULL;
struct optee_msg_arg *msg_arg;
u64 *pages_list;
phys_addr_t msg_parg;
int rc;
if (!num_pages)
return -EINVAL;
rc = check_mem_type(start, num_pages);
if (rc)
return rc;
pages_list = optee_allocate_pages_list(num_pages);
if (!pages_list)
return -ENOMEM;
shm_arg = get_msg_arg(ctx, 1, &msg_arg, &msg_parg);
if (IS_ERR(shm_arg)) {
rc = PTR_ERR(shm_arg);
goto out;
}
optee_fill_pages_list(pages_list, pages, num_pages,
tee_shm_get_page_offset(shm));
msg_arg->cmd = OPTEE_MSG_CMD_REGISTER_SHM;
msg_arg->params->attr = OPTEE_MSG_ATTR_TYPE_TMEM_OUTPUT |
OPTEE_MSG_ATTR_NONCONTIG;
msg_arg->params->u.tmem.shm_ref = (unsigned long)shm;
msg_arg->params->u.tmem.size = tee_shm_get_size(shm);
/*
* In the least bits of msg_arg->params->u.tmem.buf_ptr we
* store buffer offset from 4k page, as described in OP-TEE ABI.
*/
msg_arg->params->u.tmem.buf_ptr = virt_to_phys(pages_list) |
(tee_shm_get_page_offset(shm) & (OPTEE_MSG_NONCONTIG_PAGE_SIZE - 1));
if (optee_do_call_with_arg(ctx, msg_parg) ||
msg_arg->ret != TEEC_SUCCESS)
rc = -EINVAL;
tee_shm_free(shm_arg);
out:
optee_free_pages_list(pages_list, num_pages);
return rc;
}
int optee_shm_unregister(struct tee_context *ctx, struct tee_shm *shm)
{
struct tee_shm *shm_arg;
struct optee_msg_arg *msg_arg;
phys_addr_t msg_parg;
int rc = 0;
shm_arg = get_msg_arg(ctx, 1, &msg_arg, &msg_parg);
if (IS_ERR(shm_arg))
return PTR_ERR(shm_arg);
msg_arg->cmd = OPTEE_MSG_CMD_UNREGISTER_SHM;
msg_arg->params[0].attr = OPTEE_MSG_ATTR_TYPE_RMEM_INPUT;
msg_arg->params[0].u.rmem.shm_ref = (unsigned long)shm;
if (optee_do_call_with_arg(ctx, msg_parg) ||
msg_arg->ret != TEEC_SUCCESS)
rc = -EINVAL;
tee_shm_free(shm_arg);
return rc;
}
int optee_shm_register_supp(struct tee_context *ctx, struct tee_shm *shm,
struct page **pages, size_t num_pages,
unsigned long start)
{
/*
* We don't want to register supplicant memory in OP-TEE.
* Instead information about it will be passed in RPC code.
*/
return check_mem_type(start, num_pages);
}
int optee_shm_unregister_supp(struct tee_context *ctx, struct tee_shm *shm)
{
return 0;
}
drivers/tee/optee/core.c
View file @ fe53d144
This diff is collapsed.
drivers/tee/optee/optee_msg.h
View file @ fe53d144
......@@ -67,11 +67,32 @@
#define OPTEE_MSG_ATTR_META BIT(8)
/*
* The temporary shared memory object is not physically contigous and this
* temp memref is followed by another fragment until the last temp memref
* that doesn't have this bit set.
* Pointer to a list of pages used to register user-defined SHM buffer.
* Used with OPTEE_MSG_ATTR_TYPE_TMEM_*.
* buf_ptr should point to the beginning of the buffer. Buffer will contain
* list of page addresses. OP-TEE core can reconstruct contiguous buffer from
* that page addresses list. Page addresses are stored as 64 bit values.
* Last entry on a page should point to the next page of buffer.
* Every entry in buffer should point to a 4k page beginning (12 least
* significant bits must be equal to zero).
*
* 12 least significant bints of optee_msg_param.u.tmem.buf_ptr should hold page
* offset of the user buffer.
*
* So, entries should be placed like members of this structure:
*
* struct page_data {
* uint64_t pages_array[OPTEE_MSG_NONCONTIG_PAGE_SIZE/sizeof(uint64_t) - 1];
* uint64_t next_page_data;
* };
*
* Structure is designed to exactly fit into the page size
* OPTEE_MSG_NONCONTIG_PAGE_SIZE which is a standard 4KB page.
*
* The size of 4KB is chosen because this is the smallest page size for ARM
* architectures. If REE uses larger pages, it should divide them to 4KB ones.
*/
#define OPTEE_MSG_ATTR_FRAGMENT BIT(9)
#define OPTEE_MSG_ATTR_NONCONTIG BIT(9)
/*
* Memory attributes for caching passed with temp memrefs. The actual value
......@@ -94,6 +115,11 @@
#define OPTEE_MSG_LOGIN_APPLICATION_USER 0x00000005
#define OPTEE_MSG_LOGIN_APPLICATION_GROUP 0x00000006
/*
* Page size used in non-contiguous buffer entries
*/
#define OPTEE_MSG_NONCONTIG_PAGE_SIZE 4096
/**
* struct optee_msg_param_tmem - temporary memory reference parameter
* @buf_ptr: Address of the buffer
......@@ -145,8 +171,8 @@ struct optee_msg_param_value {
*
* @attr & OPTEE_MSG_ATTR_TYPE_MASK indicates if tmem, rmem or value is used in
* the union. OPTEE_MSG_ATTR_TYPE_VALUE_* indicates value,
* OPTEE_MSG_ATTR_TYPE_TMEM_* indicates tmem and
* OPTEE_MSG_ATTR_TYPE_RMEM_* indicates rmem.
* OPTEE_MSG_ATTR_TYPE_TMEM_* indicates @tmem and
* OPTEE_MSG_ATTR_TYPE_RMEM_* indicates @rmem,
* OPTEE_MSG_ATTR_TYPE_NONE indicates that none of the members are used.
*/
struct optee_msg_param {
......
drivers/tee/optee/optee_private.h
View file @ fe53d144
......@@ -53,36 +53,24 @@ struct optee_wait_queue {
* @ctx the context of current connected supplicant.
* if !NULL the supplicant device is available for use,
* else busy
* @ctx_mutex: held while accessing @ctx
* @func: supplicant function id to call
* @ret: call return value
* @num_params: number of elements in @param
* @param: parameters for @func
* @req_posted: if true, a request has been posted to the supplicant
* @supp_next_send: if true, next step is for supplicant to send response
* @thrd_mutex: held by the thread doing a request to supplicant
* @supp_mutex: held by supplicant while operating on this struct
* @data_to_supp: supplicant is waiting on this for next request
* @data_from_supp: requesting thread is waiting on this to get the result
* @mutex: held while accessing content of this struct
* @req_id: current request id if supplicant is doing synchronous
* communication, else -1
* @reqs: queued request not yet retrieved by supplicant
* @idr: IDR holding all requests currently being processed
* by supplicant
* @reqs_c: completion used by supplicant when waiting for a
* request to be queued.
*/
struct optee_supp {
/* Serializes access to this struct */
struct mutex mutex;
struct tee_context *ctx;
/* Serializes access of ctx */
struct mutex ctx_mutex;
u32 func;
u32 ret;
size_t num_params;
struct tee_param *param;
bool req_posted;
bool supp_next_send;
/* Serializes access to this struct for requesting thread */
struct mutex thrd_mutex;
/* Serializes access to this struct for supplicant threads */
struct mutex supp_mutex;
struct completion data_to_supp;
struct completion data_from_supp;
int req_id;
struct list_head reqs;
struct idr idr;
struct completion reqs_c;
};
/**
......@@ -96,6 +84,8 @@ struct optee_supp {
* @supp: supplicant synchronization struct for RPC to supplicant
* @pool: shared memory pool
* @memremaped_shm virtual address of memory in shared memory pool
* @sec_caps: secure world capabilities defined by
* OPTEE_SMC_SEC_CAP_* in optee_smc.h
*/
struct optee {
struct tee_device *supp_teedev;
......@@ -106,6 +96,7 @@ struct optee {
struct optee_supp supp;
struct tee_shm_pool *pool;
void *memremaped_shm;
u32 sec_caps;
};
struct optee_session {
......@@ -130,7 +121,16 @@ struct optee_rpc_param {
u32 a7;
};
void optee_handle_rpc(struct tee_context *ctx, struct optee_rpc_param *param);
/* Holds context that is preserved during one STD call */
struct optee_call_ctx {
/* information about pages list used in last allocation */
void *pages_list;
size_t num_entries;
};
void optee_handle_rpc(struct tee_context *ctx, struct optee_rpc_param *param,
struct optee_call_ctx *call_ctx);
void optee_rpc_finalize_call(struct optee_call_ctx *call_ctx);
void optee_wait_queue_init(struct optee_wait_queue *wq);
void optee_wait_queue_exit(struct optee_wait_queue *wq);
......@@ -142,6 +142,7 @@ int optee_supp_read(struct tee_context *ctx, void __user *buf, size_t len);
int optee_supp_write(struct tee_context *ctx, void __user *buf, size_t len);
void optee_supp_init(struct optee_supp *supp);
void optee_supp_uninit(struct optee_supp *supp);
void optee_supp_release(struct optee_supp *supp);
int optee_supp_recv(struct tee_context *ctx, u32 *func, u32 *num_params,
struct tee_param *param);
......@@ -160,11 +161,26 @@ int optee_cancel_req(struct tee_context *ctx, u32 cancel_id, u32 session);
void optee_enable_shm_cache(struct optee *optee);
void optee_disable_shm_cache(struct optee *optee);
int optee_shm_register(struct tee_context *ctx, struct tee_shm *shm,
struct page **pages, size_t num_pages,
unsigned long start);
int optee_shm_unregister(struct tee_context *ctx, struct tee_shm *shm);
int optee_shm_register_supp(struct tee_context *ctx, struct tee_shm *shm,
struct page **pages, size_t num_pages,
unsigned long start);
int optee_shm_unregister_supp(struct tee_context *ctx, struct tee_shm *shm);
int optee_from_msg_param(struct tee_param *params, size_t num_params,
const struct optee_msg_param *msg_params);
int optee_to_msg_param(struct optee_msg_param *msg_params, size_t num_params,
const struct tee_param *params);
u64 *optee_allocate_pages_list(size_t num_entries);
void optee_free_pages_list(void *array, size_t num_entries);
void optee_fill_pages_list(u64 *dst, struct page **pages, int num_pages,
size_t page_offset);
/*
* Small helpers
*/
......
drivers/tee/optee/optee_smc.h
View file @ fe53d144
......@@ -222,6 +222,13 @@ struct optee_smc_get_shm_config_result {
#define OPTEE_SMC_SEC_CAP_HAVE_RESERVED_SHM BIT(0)
/* Secure world can communicate via previously unregistered shared memory */
#define OPTEE_SMC_SEC_CAP_UNREGISTERED_SHM BIT(1)
/*
* Secure world supports commands "register/unregister shared memory",
* secure world accepts command buffers located in any parts of non-secure RAM
*/
#define OPTEE_SMC_SEC_CAP_DYNAMIC_SHM BIT(2)
#define OPTEE_SMC_FUNCID_EXCHANGE_CAPABILITIES 9
#define OPTEE_SMC_EXCHANGE_CAPABILITIES \
OPTEE_SMC_FAST_CALL_VAL(OPTEE_SMC_FUNCID_EXCHANGE_CAPABILITIES)
......
drivers/tee/optee/rpc.c
View file @ fe53d144
This diff is collapsed.
drivers/tee/optee/shm_pool.c 0 → 100644
View file @ fe53d144
This diff is collapsed.
drivers/tee/optee/shm_pool.h 0 → 100644
View file @ fe53d144
/*
* Copyright (c) 2015, Linaro Limited
* Copyright (c) 2016, EPAM Systems
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef SHM_POOL_H
#define SHM_POOL_H
#include <linux/tee_drv.h>
struct tee_shm_pool_mgr *optee_shm_pool_alloc_pages(void);
#endif
drivers/tee/optee/supp.c
View file @ fe53d144
This diff is collapsed.
drivers/tee/tee_core.c
View file @ fe53d144
This diff is collapsed.
drivers/tee/tee_private.h
View file @ fe53d144
This diff is collapsed.
drivers/tee/tee_shm.c
View file @ fe53d144
This diff is collapsed.
drivers/tee/tee_shm_pool.c
View file @ fe53d144
This diff is collapsed.
include/dt-bindings/reset/amlogic,meson-axg-reset.h 0 → 100644
View file @ fe53d144
This diff is collapsed.
include/linux/platform_data/ti-sysc.h 0 → 100644
View file @ fe53d144
This diff is collapsed.
include/linux/qcom_scm.h
View file @ fe53d144
......@@ -13,6 +13,9 @@
#ifndef __QCOM_SCM_H
#define __QCOM_SCM_H
#include <linux/types.h>
#include <linux/cpumask.h>
#define QCOM_SCM_VERSION(major, minor) (((major) << 16) | ((minor) & 0xFF))
#define QCOM_SCM_CPU_PWR_DOWN_L2_ON 0x0
#define QCOM_SCM_CPU_PWR_DOWN_L2_OFF 0x1
......
include/linux/reset.h
View file @ fe53d144
This diff is collapsed.
include/linux/soc/brcmstb/brcmstb.h
View file @ fe53d144
This diff is collapsed.
include/linux/soc/qcom/qmi.h 0 → 100644
View file @ fe53d144
This diff is collapsed.
include/linux/tee_drv.h
View file @ fe53d144
This diff is collapsed.
include/linux/ti-emif-sram.h 0 → 100644
View file @ fe53d144
This diff is collapsed.
include/soc/tegra/mc.h
View file @ fe53d144
This diff is collapsed.
include/uapi/linux/tee.h
View file @ fe53d144
This diff is collapsed.
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