- 14 Jun, 2024 14 commits
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Lewis Huang authored
[Why] For some panel, it cannot handle pseudo vblank set by otg resync when leave psr [How] The monitor patch will keep otg_on during enter IPS1. And then we don't need to do otg resync when wake up. Reviewed-by:
Duncan Ma <duncan.ma@amd.com> Acked-by:
Zaeem Mohamed <zaeem.mohamed@amd.com> Signed-off-by:
Lewis Huang <lewis.huang@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Chiawen Huang authored
[How&Why] Once IPS active, all the DCN resources are not be allowed to access. It needs to a function for 3rd party to on/off IPS. Reviewed-by:
Chiawen Huang <chiawen.huang@amd.com> Tested-by:
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Dillon Varone authored
[WHY&HOW] Add 5ms timeout to trigger recovery and force allow P-State in DMUB. Reviewed-by:
Alvin Lee <alvin.lee2@amd.com> Acked-by:
Dillon Varone <dillon.varone@amd.com> Tested-by:
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Dillon Varone authored
[WHY&HOW] UCLK and FCLK are updated together, so an FCLK update can also cause UCLK update to SMU. When this happens, the UCLK provided should be max if switching is unsupported. Reviewed-by:
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Wayne Lin authored
[Why] enc10->base.features.flags.bits.DP_IS_USB_C will be overwritten if we set it before initializing enc10->base.features [How] Determine DP_IS_USB_C after enc10->base.features is initialized. Besides, bp_cap_info.DP_IS_USB_C will never be set in get_connector_speed_cap_info(). Remove the redudant code. Reviewed-by:
Roman Li <roman.li@amd.com> Acked-by:
Wayne Lin <wayne.lin@amd.com> Tested-by:
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Yihan Zhu authored
[WHY] OPPs couldn't disconnect from the ODM that cause the double buffer pending not being latched due to missing VUPDATE. [HOW] Moving memory blanking before OTG turn off to make sure double buffer latched correctly. Reviewed-by:
Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> Acked-by:
Yihan Zhu <yihan.zhu@amd.com> Tested-by:
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Alex Deucher authored
This mirrors what the driver does for older DCN generations. Should fix: [ 26.924055] BUG: sleeping function called from invalid context at include/linux/sched/mm.h:306 [ 26.924060] in_atomic(): 1, irqs_disabled(): 0, non_block: 0, pid: 1022, name: modprobe [ 26.924063] preempt_count: 2, expected: 0 [ 26.924064] RCU nest depth: 0, expected: 0 [ 26.924066] Preemption disabled at: [ 26.924067] [<ffffffffc089e5e0>] dc_fpu_begin+0x30/0xd0 [amdgpu] [ 26.924322] CPU: 9 PID: 1022 Comm: modprobe Not tainted 6.8.0+ #20 [ 26.924325] Hardware name: System manufacturer System Product Name/CROSSHAIR VI HERO, BIOS 6302 10/23/2018 [ 26.924326] Call Trace: [ 26.924327] <TASK> [ 26.924329] dump_stack_lvl+0x37/0x50 [ 26.924333] ? dc_fpu_begin+0x30/0xd0 [amdgpu] [ 26.924589] dump_stack+0x10/0x20 [ 26.924592] __might_resched+0x16a/0x1c0 [ 26.924596] __might_sleep+0x42/0x70 [ 26.924598] __kmalloc_node_track_caller+0x2ad/0x4b0 [ 26.924601] ? dm_helpers_allocate_gpu_mem+0x12/0x20 [amdgpu] [ 26.924855] ? dcn401_update_bw_bounding_box+0x2a/0xf0 [amdgpu] [ 26.925122] kmemdup+0x20/0x50 [ 26.925124] ? kernel_fpu_begin_mask+0x6b/0xe0 [ 26.925127] ? kmemdup+0x20/0x50 [ 26.925129] dcn401_update_bw_bounding_box+0x2a/0xf0 [amdgpu] [ 26.925393] dc_create+0x311/0x670 [amdgpu] [ 26.925649] amdgpu_dm_init+0x2aa/0x1fa0 [amdgpu] [ 26.925903] ? irq_work_queue+0x38/0x50 [ 26.925907] ? vprintk_emit+0x1e7/0x270 [ 26.925910] ? dev_printk_emit+0x83/0xb0 [ 26.925914] ? amdgpu_device_rreg+0x17/0x20 [amdgpu] [ 26.926133] dm_hw_init+0x14/0x30 [amdgpu] v2: drop extra memcpy Fixes: 669d6b07 ("drm/amd/display: avoid large on-stack structures") Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Acked-by:
Arnd Bergmann <arnd@arndb.de> Suggested-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
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Alex Deucher authored
This mirrors what the driver does for older DCN generations. Should fix: BUG: sleeping function called from invalid context at include/linux/sched/mm.h:306 in_atomic(): 1, irqs_disabled(): 0, non_block: 0, pid: 449, name: kworker/u64:8 preempt_count: 2, expected: 0 RCU nest depth: 0, expected: 0 Preemption disabled at: ffffffffc0ce1580>] dc_fpu_begin+0x30/0xd0 [amdgpu] CPU: 5 PID: 449 Comm: kworker/u64:8 Tainted: G W 6.8.0+ #35 Hardware name: System manufacturer System Product Name/ROG STRIX X570-E GAMING WIFI II, BIOS 4204 02/24/2022 Workqueue: events_unbound async_run_entry_fn v2: drop extra memcpy Fixes: 88c61827 ("drm/amd/display: dynamically allocate dml2_configuration_options structures") Reviewed-by:
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Frank Min authored
1. Add dcc buffer flag for copy buffer 2. Add sdma 7.0 support copy dcc buffer Signed-off-by:
Likun Gao <Likun.Gao@amd.com> Signed-off-by:
Frank Min <Frank.Min@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Likun Gao authored
Deal with AMDGPU_GEM_CREATE_GFX12_DCC to set DCC bit when needed. Signed-off-by:
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Alex Deucher authored
Add additional VM PTE bits. Reviewed-by:
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Thorsten Blum authored
The if conditions !A || A && B can be simplified to !A || B. Fixes the following Coccinelle/coccicheck warnings reported by excluded_middle.cocci: WARNING !A || A && B is equivalent to !A || B WARNING !A || A && B is equivalent to !A || B WARNING !A || A && B is equivalent to !A || B Compile-tested only. Signed-off-by:
Thorsten Blum <thorsten.blum@toblux.com> Signed-off-by:
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Jack Chang authored
1. To support multiple PSRSU residency measurement mode Reviewed-by:
Wenjing Liu <wenjing.liu@amd.com> Acked-by:
Jack Chang <jack.chang@amd.com> Tested-by:
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Nicholas Kazlauskas authored
[Why] HPD sense changes can occur during low power states and need to be notified from firmware to driver. Upon notification the hotplug redetection routines should execute. [How] Add Support in DMUB srv and DMUB srv stat for receiving these notifications. DM can hook them up and process the HPD redetection once received. Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by:
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- 05 Jun, 2024 26 commits
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Tao Zhou authored
Set the flag to true if bad page number reaches threshold. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
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Srinivasan Shanmugam authored
This commit adds null checks for the 'stream' and 'plane' variables in the dcn30_apply_idle_power_optimizations function. These variables were previously assumed to be null at line 922, but they were used later in the code without checking if they were null. This could potentially lead to a null pointer dereference, which would cause a crash. The null checks ensure that 'stream' and 'plane' are not null before they are used, preventing potential crashes. Fixes the below static smatch checker: drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn30/dcn30_hwseq.c:938 dcn30_apply_idle_power_optimizations() error: we previously assumed 'stream' could be null (see line 922) drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn30/dcn30_hwseq.c:940 dcn30_apply_idle_power_optimizations() error: we previously assumed 'plane' could be null (see line 922) Cc: Tom Chung <chiahsuan.chung@amd.com> Cc: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Cc: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Roman Li <roman.li@amd.com> Cc: Hersen Wu <hersenxs.wu@amd.com> Cc: Alex Hung <alex.hung@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
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Jesse Zhang authored
Since gmc_pg is false, setting mcFlags with SISLANDS_SMC_MC_PG_EN cannot be reach. Signed-off-by:
Jesse Zhang <Jesse.Zhang@amd.com> Suggested-by:
Tim Huang <Tim.Huang@amd.com> Reviewed-by:
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Fangzhi Zuo authored
IPX involvment proven to affect LT, causing link loss. Need to prevent IPX enabled in LT process in which link detect and set mode are main procedures that have LT taken place. Reviewed-by:
Fangzhi Zuo <jerry.zuo@amd.com> Tested-by:
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Jesse Zhang authored
idr_for_each_entry can ensure that mem is not empty during the loop. So don't need check mem again. Signed-off-by:
Felix Kuehling <felix.kuehling@amd.com> Signed-off-by:
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Lin.Cao authored
Flag "mes.ring.shced.ready" will be set as true after mes hw init and set as false when mes hw fini to avoid duplicate initialization. But hw fini will not be called when function level reset, which will cause mes hw init be skipped during FLR, which will leads to mapping legacy queue fail. Set this flag as false when post reset will fix this issue. Signed-off-by:
Lin.Cao <lincao12@amd.com> Acked-by:
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Daniel Sa authored
[Why] When performing P-State switching with Subvp on 8k (downscaled to 4k). corruption can be seen on the screen. MALL data was not being fetched from DC, and the system things there is more MALL space then what is actually available. [How] Read MALL size from dc caps. Reviewed-by:
Daniel Sa <daniel.sa@amd.com> Tested-by:
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Samson Tam authored
[Why] Missing check causes sequence error which results in chroma filter coefficients not being updated in certain modes when we display YUV video in fullscreen. This results in color corruption in video [How] Add back chroma_coef_mode check in dscl_set_scl_filter so that filter coefficients are calculated and updated when we have YUV surface Reviewed-by:
Samson Tam <samson.tam@amd.com> Tested-by:
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Eric Huang authored
reset cause is requested by customer as additional info for gpu reset smi event. v2: integerate reset sources suggested by Lijo Lazar Signed-off-by:
Eric Huang <jinhuieric.huang@amd.com> Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
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Frank Min authored
Update to latest changes. Signed-off-by:
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Frank Min authored
Set PTE_IS_PTE bit while PRT is enabled on gfx12. Signed-off-by:
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Relja Vojvodic authored
why: optc_401_set_drr was using an old optc3 function to update vtotal min and max, causing crashes when disabling FAMS2 how: Updated dcn401 to point to opt401 function for vtotal updates. This version of the function has FAMS2 logic that allows for FAMS2 to be disabled. Reviewed-by:
Relja Vojvodic <relja.vojvodic@amd.com> Tested-by:
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Eric Huang authored
reset source or reset cause is very useful info for reset context, it will be used by events API. Suggested-by:
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Dillon Varone authored
[WHY&HOW] Improves on the SMU interface to explicitly declare P-State support. Reviewed-by:
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Alvin Lee authored
[Description] When checking the subvp type of the previous state we must pass in current_state to the interface instead of context otherwise we will get the wrong result. Reviewed-by:
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Bob Zhou authored
Check return value to avoid null pointer dereference. Signed-off-by:
Bob Zhou <bob.zhou@amd.com> Reviewed-by:
Yang Wang <kevinyang.wang@amd.com> Signed-off-by:
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Bob Zhou authored
Check return value and conduct null pointer handling to avoid null pointer dereference. Signed-off-by:
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Shane Xiao authored
This patch changes the implementation of AMDGPU_PTE_MTYPE_VG10, clear the bits before setting the new one. Suggested-by:
longlyao <Longlong.Yao@amd.com> Signed-off-by:
Shane Xiao <shane.xiao@amd.com> Reviewed-by:
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Jesse Zhang authored
kfd_create_vcrat_image_gpu itself checks the avail_size at the start. So the value of avail_size is at least VCRAT_SIZE_FOR_GPU(16384), minus struct crat_header(40UL) and struct crat_subtype_compute(40UL) it cannot be less than 0. Signed-off-by:
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Jesse Zhang authored
The expression caps | HSA_CAP_TRAP_DEBUG_PRECISE_MEMORY_OPERATIONS_SUPPORTED and caps | HSA_CAP_TRAP_DEBUG_PRECISE_ALU_OPERATIONS_SUPPORTED are always 1/true regardless of the values of its operand. Fixes: 9243240b ("drm/amdkfd: enable single alu ops for gfx12") Signed-off-by:
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Jesse Zhang authored
To fix the warning about unused value, remove the use_static and use the parameter is_static directly. Signed-off-by:
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Alvin Lee authored
[Description] Refactor code and move fpo_in_use into stream_status to avoid unexpected changes to previous dc_state (i.e., current_state). Since stream pointers are shared between current and new dc_states, updating parameters of one stream will update the other as well which causes unexpected behaviors (i.e., checking that fpo_in_use isn't set in previous state and set in the new state is invalid). To avoid incorrect updates to current_state, move the fpo_in_use flag into dc_stream_status since stream_status is owned by dc and are not shared between different dc_states. Reviewed-by:
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Alvin Lee authored
[Description] Today for MED update type we do not call update clocks. However, for FPO the assumption is that update clocks should be called to disable P-State switch before any HW programming since FPO in FW and driver are not synchronized. This causes an issue where on a MED update, an FPO P-State switch could be taking place, then driver forces P-State disallow in the below code and prevents FPO from completing the sequence. In this case we add a check to avoid re-programming (and thus re-setting) the P-State force register by only reprogramming if the pipe was not previously Subvp or FPO. The assumption is that the P-State force register should be programmed correctly the first time SubVP / FPO was enabled, so there's no need to update / reset it if the pipe config has never exited SubVP / FPO. Reviewed-by:
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Joan Lee authored
[why & how] Sometimes read DPCD return fail while result not retrieved yet. Add retries mechanism in Replay handle hpd irq to get real result. Reviewed-by:
Joan Lee <joan.lee@amd.com> Tested-by:
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Nicholas Susanto authored
[Why] When an eDP with high clock states is going into s0i3, stream_count is 0. This causes DML to not update the clks to the lowest state and blocking us to enter s0i3 since eDP is out of vmin. [How] When stream_count is 0, set all the clocks to the lowest state. Reviewed-by:
Jun Lei <jun.lei@amd.com> Acked-by:
Nicholas Susanto <nicholas.susanto@amd.com> Tested-by:
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Jay Cornwall authored
A wavefront may deallocate its VGPRs at the end of a program while waiting for memory transactions to complete. If it subsequently receives a context save exception it will be unable to save, since this requires VGPRs. In this case the trap handler should terminate the wavefront. Fixes intermittent VM faults under context switching load. V2: Use S_ENDPGM instead of S_ENDPGM_SAVED for performance counters Signed-off-by:
Jay Cornwall <jay.cornwall@amd.com> Reviewed-by:
Lancelot Six <lancelot.six@amd.com> Signed-off-by:
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