- 11 Nov, 2012 16 commits
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Damien Lespiau authored
We were writing DSP_ADDR and DSP_SURF unconditionally. This did not trigger an unclaimed write before HSW as the address of DSP_ADDR has been repurposed as DSP_LINOFF. On HSW, though, DSP_LINOFF has been removed and then writting to it triggers an unclaimed write. This patch writes to DSP_ADDR or DSP_SURF to flush the display plane configuration depending on the gen we're running on. Signed-off-by:
Damien Lespiau <damien.lespiau@intel.com> Reviewed-by:
Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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Daniel Vetter authored
Comment says for eaglelake/cantiga, but it's listed in the ilk table, too. So apply it to both. Reviewed-by:
Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
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Daniel Vetter authored
Or at least our best understanding of it. v2: Fixup commit message and put the wa name into the comment block. And actually update the commit, too. Reviewed-by:
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Damien Lespiau authored
Just like in: commit c2c75131 Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Thu Jul 5 12:17:30 2012 +0200 drm/i915: adjust framebuffer base address on gen4+ but this time, for the sprite planes. This ensures that the sprite offset are always inside the supported hardware limits since it becomes the offset into a page and we adjust the base address to a page boundary. Signed-off-by:
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Damien Lespiau authored
HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET register. v2: Remove a useless level of indentation (Paulo Zanoni) Signed-off-by:
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Damien Lespiau authored
Haswell consolidates DSP_TILEOFF and DSP_LINOFF into DSP_OFFSET (aka PRI_OFFSET). Signed-off-by:
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Damien Lespiau authored
v2: Use a switch for consistency (Chris Wilson) Signed-off-by:
Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by:
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Damien Lespiau authored
Instead of writing to the DSP_ADDR ourselves. This will do the right thing on gen >= 4 as well. Signed-off-by:
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Daniel Vetter authored
And properly toggle the chicken bit in the pch to enable/disable fdi C rx. If we don't set this bit correctly, the rx gets confused in link training, which can result in an fdi link that silently fails to train the link (since the corresponding register reports success). Note that both fdi link B and C can suffer when this bit is not set correctly. The code as-is has a few deficiencies: - We presume all pipes use the pch which is not the case for cpu edp. - We don't bother with disabling both pipes when we could make things work, e.g. when pipe B switched from 4 to 2 lanes due to a mode change, we don't bother updating the w/a bit. - It's ugly. All of these are because we compute ->fdi_lanes way too late, when we're already setting up individual pipes. We need to have this information in ->modeset_global_resources already, to set things up correctly. But that is a much larger reorg of the code. Note that we actually hit the 2 lanes limit in practice rather quickly: Even though the 1920x1200 mode native mode of my screen fits into 2 lanes, it needs 3 lanes for the 1920x1080 (since that somehow has much more blanking ...). Not obeying this restriction seems to results in cute-looking digital noise. v2: Only ever clear the chicken bit when both pipes are off. v3: Use the new ->modeset_global_resources callback. v4: Move the WARNs to the right place. Oh how I hate hacks. v5: Fix spelling, noticed by Paulo Zanoni. Reviewed-by:
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Daniel Vetter authored
After all relevant pipes are disabled and after we've updated all the state with the staged state, but before we call the per-crtc ->mode_set functions there's a very natural point to set up any shared/global resources like - shared plls (obviously only the setup, the enabling needs to be separately handling with a separate refcount) - global watermark state like the DSPARB on gmch platforms - workaround bits that depend upon the exact global output configuration - enabling the right set of refclocks - enabling/disabling manual power wells. Now for a lot of these things we can't move them into this function yet, most often because we only compute the required information in the per-crtc ->mode_set callback. Which is too late. But due to a bunch of reasons (check-only atomic modeset, fastboot&hw state checks, ...) we need to separate the computation of that state from the actual hw frobbery anyway. So we can move things into this new callback step- by-step. Others can't be moved here (or implemented at all) because our code lacks the smarts to properly update them. E.g. the DSPARB can only be updated when all pipes are disabled, so if we decide to change it's value, we need to disable _all_ pipes. The infrastructure for that is already in place (with the various pipe masks that driver the modeset logic). But again we need to move a few things out of ->mode_set first before we can even implement the correct decision making. In any case, we need to start somewhere, so let's start with the callback: Some small follow-up patches will make immediate good use of it. Reviewed-by:
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Daniel Vetter authored
Since it is one. We need to move this code to encoder specific callbacks eventually, to kill all that inversion of control ... Reviewed-by:
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Daniel Vetter authored
Atm we have a few funny issues where we enable/disable shared pll clocks. To make it clear that we are not required to enable/ disable the pch plls together with the other pch resources (and so should keep it running when it's used by another pipe in a shared pll configuration) add a comment. This note is lifted from "Graphics BSpec: vol4g North Display Engine Registers [IVB], Display Mode Set Sequence", step 9.d. of the enable sequence: "Configure and enable PCH DPLL, wait for PCH DPLL warmup (Can be done anytime before enabling PCH transcoder)." Since fixing the pll sharing code to no longer disable shared plls if they're still in use is more involved, let's just stick with the comment for now. v2: Make the comment in the code clearer, to address questions raised by Paulo Zanoni in review. Reviewed-by:
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Daniel Vetter authored
My machine here has the correct ones already, but better safe than sorry. IBX has different settings for that register, and on IBX the device defaults match the recommended values. Hence I did not add the respective writes for IBX. LPT needs the same settings, but that has been done already commit 4acf5186 Author: Eugeni Dodonov <eugeni.dodonov@intel.com> Date: Wed Jul 4 20:15:16 2012 -0300 drm/i915: program FDI_RX TP and FDI delays Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by:
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Daniel Vetter authored
For reference, see "Graphics BSpec: vol4g North Display Engine Registers [IVB], Display Mode Set Sequence", step 4 of the enabling sequence: a. "Enable PCH FDI Receiver PLL, wait for warmup plus DMI latency b. "Switch from Rawclk to PCDclk in FDI Receiver c. "Enable CPU FDI Transmitter PLL, wait for warmup" Cc: Paulo Zanoni <przanoni@gmail.com> Reviewed-by:
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Daniel Vetter authored
According to "Graphics BSpec: vol4g North Display Engine Registers [IVB], Display Mode Set Sequence" We need to write the TU size register of the fdi RX unit _before_ starting to train the link. Note: The current code is actually correct as Paulo mentioned in review, but it's a bit confusion since only the fdi rx/tx plls need to be enabled before the cpu pipes/planes. Hence it's still a good idea to move the TU_SIZE setting to the "right" spot in the sequence, to better match Bspec. Reviewed-by:
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Daniel Vetter authored
The debug message is only relevant on CPT/PPT PCH ports, so move it into the correct if clause. Reviewed-by:
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- 02 Nov, 2012 1 commit
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Jani Nikula authored
Daniel's backmerge commit c2fb7916 Merge: 29de6ce5 6f0c0580 Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Mon Oct 22 14:34:51 2012 +0200 Merge tag 'v3.7-rc2' into drm-intel-next-queued to solve conflicts blew up (either git or Daniel was trying to be too clever for their own good; it's usually convenient to blame tools ;) and caused the changes of commit 0c96c65b Author: Jani Nikula <jani.nikula@intel.com> Date: Wed Sep 26 18:43:10 2012 +0300 drm/i915: use adjusted_mode instead of mode for checking the 6bpc force flag in ironlake_crtc_mode_set() to be dropped. Fix the call in ironlake_crtc_mode_set() again, and while at it, also fix the new, copy-pasted haswell_crtc_mode_set() to use adjusted_mode. Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Signed-off-by:
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- 26 Oct, 2012 23 commits
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Yuly Novikov authored
Signed-off-by:
Yuly Novikov <ynovikov@chromium.org> [Jani: ripped this change separate from the scaling mode change support] Signed-off-by:
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Yuly Novikov authored
LVDS allowed changing panel fitting scaling mode, while eDP didn't. Copied relevant code from LVDS to eDP. Signed-off-by:
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Jani Nikula authored
Prepare for supporting scaling mode configuration also in eDP. Includes a drive-by-removal of an outdated comment about fitting mode. Signed-off-by:
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Jani Nikula authored
At some point the DPCD size was increased, but the debug print not. While at it, switch to using hex dump. Signed-off-by:
Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by:
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Damien Lespiau authored
Just like HSW, VLV does not have a sprite scale. Set intel_plane->can_scale accordingly. Signed-off-by:
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Jani Nikula authored
SDVOB may be multiplexed with HDMIB. If it's not SDVOB, the same i2c adapter may be used for HDMIB, with the adjusted config (i.e. with GPIO bit-banging instead of gmbus). Restore i2c adapter config before error return from intel_sdvo_init(), letting HDMIB enjoy the joys of gmbus. Signed-off-by:
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Jani Nikula authored
commit 63abf3ed Author: Chris Wilson <chris@chris-wilson.co.uk> Date: Wed Dec 8 16:48:21 2010 +0000 drm/i915/sdvo: Only use the SDVO pin if it is in the valid range added a default fallback if BIOS provides an invalid pin mapping, but failed to force GPIO bit-banging on it. Finish the job, and also clean up the function a bit. With bit-banging, setting the gmbus speed has no effect, so drop it. Signed-off-by:
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Paulo Zanoni authored
Now that all the eDP enablement bits are there, we can actually try to use the eDP. Signed-off-by:
Rodrigo Vivi <rodrigo.vivi@gmail.com> Signed-off-by:
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Paulo Zanoni authored
It's an important step :) Signed-off-by:
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Paulo Zanoni authored
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Paulo Zanoni authored
The cdclk frequency is not always the same, so the value here should be adjusted to match it. Version 2: call intel_ddi_get_cdclk_freq instead of reading CDCLK_FREQ, because the register is just for earlier HW steppings. Signed-off-by:
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Paulo Zanoni authored
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Paulo Zanoni authored
See the documentation for the DDI_FUNC_CTL register, EDP Input Select bits: when the EDP input selection is B, the VTOTAL_B must be programmed with the VTOTAL_EDP value, same thing for selection C. V2: Use I915_READ as suggested by Daniel Vetter. Signed-off-by:
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Paulo Zanoni authored
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Paulo Zanoni authored
Same thing as the previous commits. Not renaming this one since it exists since way before Haswell. Signed-off-by:
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Paulo Zanoni authored
Same as the other registers. This one also appeared on Haswell for the first time, so that's why we are renaming it. Signed-off-by:
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Paulo Zanoni authored
Because the PIPECONF register is actually part of the CPU transcoder, not the CPU pipe. Ideally we would also rename PIPECONF to TRANSCONF to remind people that they should use the transcoder instead of the pipe, but let's keep it like this for now since most Gens still name it PIPECONF. Signed-off-by:
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Paulo Zanoni authored
We need to check if any of the pipes is using TRANSCODER_EDP. V2: DDI_BUF_CTL was renamed, so fix the usage here. Signed-off-by:
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Paulo Zanoni authored
Because there's one instance of the register per CPU transcoder and not per CPU pipe. This is another register that appeared for the first time on Haswell, and even though its Haswell name is PIPE_DDI_FUNC_CTL, it will be renamed to TRANS_DDI_FUNC_CTL, so let's just use the new naming scheme before it confuses more people. Notice that there's a big improvement on intel_ddi_get_hw_state due to the new TRANSCODER_EDP. V2: Also rename the register to TRANS_DDI_FUNC_CTL as suggested by Damien Lespiau. Signed-off-by:
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Paulo Zanoni authored
This register appeared in Haswell. It does not have an EDP version because the EDP transcoder is always tied to the DDIA clock. Notice that if we call PIPE_CLK_SEL(pipe) when pipe is PIPE_A and transcoder is TRANSCODER_EDP we might introduce a bug, that's why this is a transcoder register even though it does not have an EDP version. Even though Haswell names this register PIPE_CLK_SEL, it will be renamed to TRANS_CLK_SEL in the future, so let's just start using the real name that makes more sense and avoids misusage. Signed-off-by:
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Paulo Zanoni authored
Before Haswell we used to have the CPU pipes and the PCH transcoders. We had the same amount of pipes and transcoders, and there was a 1:1 mapping between them. After Haswell what we used to call CPU pipe was split into CPU pipe and CPU transcoder. So now we have 3 CPU pipes (A, B and C), 4 CPU transcoders (A, B, C and EDP) and 1 PCH transcoder (only used for VGA). For all the outputs except for EDP we have an 1:1 mapping on the CPU pipes and CPU transcoders, so if you're using CPU pipe A you have to use CPU transcoder A. When have an eDP output you have to use transcoder EDP and you can attach this CPU transcoder to any of the 3 CPU pipes. When using VGA you need to select a pair of matching CPU pipes/transcoders (A/A, B/B, C/C) and you also need to enable/use the PCH transcoder. For now we're just creating the cpu_transcoder definitions and setting cpu_transcoder to TRANSCODER_EDP on DDI eDP code, but none of the registers was ported to use transcoder instead of pipe. The goal is to keep the code backwards-compatible since on all cases except when using eDP we must have pipe == cpu_transcoder. V2: Comment the haswell_crtc_off chunk, suggested by Damien Lespiau and Daniel Vetter. We currently need the haswell_crtc_off chunk because TRANSCODER_EDP can be used by any CRTC, so when you stop using it you have to stop saying you're using it, otherwise you may have at some point 2 CRTCs claiming they're using TRANSCODER_EDP (a disabled CRTC and an enabled one), then the HW state readout code will get completely confused. In other words: Imagine the following case: xrandr --output eDP1 --auto --crtc 0 xrandr --output eDP1 --off xrandr --output eDP1 --auto --crtc 2 After the last command you could get a "pipe A assertion failure (expected off, current on)" because CRTC 0 still claims it's using TRANSCODER_EDP, so the HW state readout function will read it (through PIPECONF) and expect it to be off, when it's actually on because it's being used by CRTC 2. So when we make "intel_crtc->cpu_transcoder = intel_crtc->pipe" we make sure we're pointing to our own original CRTC which is certainly not used by any other CRTC. Signed-off-by:
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Paulo Zanoni authored
On Ironlake we have one PCH transcoder and FDI per pipe, so we know that if ironlake_crtc_driving_pch returns false we can disable the PCH transcoder and we also know that when we disable the crtc we can also disable the PCH transcoder. On Haswell there is only 1 PCH transcoder and FDI and they can be used by any CRTC. So if for one specific crtc haswell_crtc_driving_pch returns false we can't assert anything about the state of the PCH transcoder or the FDI link without checking if any other CRTC is using the PCH. So on this commit remove the "assert_fdi_{t,r}x_disabled" form haswell_crtc_enable and also only disable FDI and the PCH transcoder if the port being disabled was actually a PCH port (we only have one port using PCH: the VGA port). Signed-off-by: -
Paulo Zanoni authored
By forking Ironlake and Haswell functions. The only callers are {ironlake,haswell}_crtc_enable anyway, and this way we won't need to add other checks on the Haswell version for the next gens. V2: Even simpler, as pointed by Jani Nikula. Signed-off-by:
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