1. 22 Feb, 2018 3 commits
    • Andrew Lunn's avatar
      net: dsa: mv88e6xxx: scratch registers and external MDIO pins · 2510babc
      Andrew Lunn authored
      MV88E6352 and later switches support GPIO control through the "Scratch
      & Misc" global2 register. Two of the pins controlled this way on the
      mv88e6390 family are the external MDIO pins. They can either by used
      as part of the MII interface for port 0, GPIOs, or MDIO. Add a
      function to configure them for MDIO, if possible, and call it when
      registering the external MDIO bus.
      Suggested-by: default avatarRussell King <rmk@armlinux.org.uk>
      Signed-off-by: default avatarAndrew Lunn <andrew@lunn.ch>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      2510babc
    • Thomas Falcon's avatar
      ibmvnic: Fix TX descriptor tracking · aa902947
      Thomas Falcon authored
      With the recent change, transmissions that only needed
      one descriptor were being missed. The result is that such
      packets were tracked as outstanding transmissions but never
      removed when its completion notification was received.
      
      Fixes: ffc385b9 ("ibmvnic: Keep track of supplementary TX descriptors")
      Signed-off-by: default avatarThomas Falcon <tlfalcon@linux.vnet.ibm.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      aa902947
    • David S. Miller's avatar
      Merge tag 'mlx5-updates-2018-02-21' of git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux · f4af1db4
      David S. Miller authored
      Saeed Mahameed says:
      
      ====================
      mlx5-updates-2018-02-21
      
      This series includes shared code updates for mlx5 core driver for both
      netdev and rdma subsystems.
      
      By Saeed,
      First six patches of the series are meant to address a performance issue
      and should provide a performance boost for multi core IRQ interrupt hungry
      workloads.  The issue is fixed in the first patch, all other patches are
      meant to refactor the code in light of this fix.
      
      The problem it comes to fix, is a shared spinlock accessed across all HCA
      IRQs which protects the CQ database.  To solve this we simply move the CQ
      database and its spinlock to be per EQ (IRQ), thus per core.
      
      By Yonatan,
      Fragmented completion queue (CQ) for RDMA,
      core driver implementation to create fragmented CQ buffers rather than
      one large contiguous memory buffer, the implementation scheme already
      exist and used by the netdev CQs, the patch shares that code with the
      rdma CQ creation flow and makes use of the new API in mlx5_ib driver.
      ====================
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      f4af1db4
  2. 21 Feb, 2018 28 commits
  3. 20 Feb, 2018 9 commits