- 20 Jun, 2024 4 commits
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Ville Syrjälä authored
The DSB code will need to know the hardware's idea of vertical active, as that is also what defines the start of undelayed vblank. Introduce a helper that gives us that information, in line with the other intel_mode_v*() functions. Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240611133344.30673-5-ville.syrjala@linux.intel.comReviewed-by:
Jani Nikula <jani.nikula@intel.com>
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Ville Syrjälä authored
Add a tracepoint to see exactly when async flips complete. Signed-off-by:
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Ville Syrjälä authored
Add a separate tracepoint for async flips vs. sync plane updates to make it a bit easier to figure out what is happening. Signed-off-by:
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Ville Syrjälä authored
We'll need to arm the vblank event also from the future DSB based codepath. Extract the function that does the whold dance for us. Signed-off-by:
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- 19 Jun, 2024 17 commits
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Ville Syrjälä authored
MTL has some new IOMMU thing that has a few new fault interrupts. Enable those so we can know if things are going poorly. Signed-off-by:
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Ville Syrjälä authored
PipeDMC has its own fault interrupt. Enable that so that we can know if things are failing. While at it, define the other pipeDMC interrupt as well, even though we're not currently using it. Signed-off-by:
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Ville Syrjälä authored
GEN8_DE_PIPE_IRQ_FAULT_ERRORS & co. don't really achieve anything. Get rid of them and just declare all the bits directly in gen8_de_pipe_fault_mask(). Signed-off-by:
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Ville Syrjälä authored
GEN9_PIPE_PLANE_FLIP_DONE() only works for planes 1-4. Extend it handle planes 5-7 as well. Somewhat annoyingly the bits are spread around into two distinct clumps. Currently this doesn't achieve anything, but if we ever extend async flip support to more than just the first plane then we'll need this. Signed-off-by:
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Ville Syrjälä authored
It's really hard to figure out which bdw+ pipe interrupt bits we've defined and which we have not. Sort the defines to make that a bit easier (still not super easy since the bits have been shuffled a bit over the years). Signed-off-by:
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Ville Syrjälä authored
Sprinkle some notes indicating which platforms have which pipe interrupt bits. Signed-off-by:
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Ville Syrjälä authored
Replace the hand rolled (1<<n) with the modern REG_BIT() approach for the bdw+ pipe interrupt bits. Signed-off-by:
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Jani Nikula authored
Sync to v6.10-rc3. Signed-off-by: -
Jouni Högander authored
PORT_ALPM_* registers are using MMIO_TRANS2 macro. This is not correct as they are port register. Use _PORT_MMIO instead. Fixes: 4ee30a44 ("drm/i915/alpm: Add ALPM register definitions") Signed-off-by:
Jouni Högander <jouni.hogander@intel.com> Reviewed-by:
Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240618053026.3268759-10-jouni.hogander@intel.com
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Jouni Högander authored
This reverts commit f3c2031d. We want to notice possible issues faced with PSR2 Region Early Transport as early as possible -> let's revert patch disabling Region Early Transport by default. Also eDP 1.5 Panel Replay requires Early Transport. Signed-off-by:
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Jouni Högander authored
Add new debug bit to be used with i915_edp_psr_debug debugfs interface. This can be used to disable Panel Replay. v2: ensure that fastset is performed when the bit changes Signed-off-by:
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Jouni Högander authored
Enabling/disabling Panel Replay on sink side has to be done before link training. We can't disable it in sink side on PSR disable. Fixes: 88ae6c65 ("drm/i915/psr: Unify panel replay enable/disable sink") Signed-off-by:
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Jouni Högander authored
Currently PSR2 SU Region Early Transport is enabled by default on Lunarlake if panel supports it despite enable_psr module parameter value. This patch makes it possible for user to limit used PSR mode and prevent SU Region Early Transport by setting enable_psr as 2. With default (-1) PSR2 SU Region Early Transport is allowed. v2: fix/improve commit desciption Signed-off-by:
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Jouni Högander authored
If user is specifically limiting PSR mode to PSR1 or PSR2: disable Panel Replay. With default value -1 all modes are allowed including Panel Replay. Disabling PSR using value 0 disables Panel Replay as well. Also own compute config helper is added for Panel Replay. This makes sense because number of Panel Replay specific checks are increasing. v2: Squash adding Panel Replay compute config helper Signed-off-by:
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Jouni Högander authored
Port clock is link rate in 10 kbit/s units. Take this into account when calculating AUX Less wake time. Fixes: da6a9836 ("drm/i915/psr: Calculate aux less wake time") Signed-off-by:
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Jouni Högander authored
Wa 16021440873 is writing wrong register. Instead of PIPE_SRCSZ_ERLY_TPT write CURPOS_ERLY_TPT. v2: use right offset as well Fixes: 29cdef85 ("drm/i915/display: Implement Wa_16021440873") Signed-off-by:
Mika Kahola <mika.kahola@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240618053026.3268759-3-jouni.hogander@intel.com
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Jouni Högander authored
Currently SU area width is set as MAX_INT. This is causing problems. Instead set it as pipe src width. Fixes: 86b26b6a ("drm/i915/psr: Carry su area in crtc_state") Signed-off-by:
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- 17 Jun, 2024 14 commits
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Mitul Golani authored
Update calculation to avoid overflow. -v2: Remove extra line between cc and signed-off. Fixes: 1676ecd3 ("drm/i915: Compute CMRR and calculate vtotal") Cc: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by:
Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by:
Ankit Nautiyal <ankit.k.nautiyal@intel.com> Acked-by:
Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240614044213.377710-1-mitulkumar.ajitkumar.golani@intel.comSigned-off-by:
Rodrigo Vivi <rodrigo.vivi@intel.com>
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Vinod Govindapillai authored
Move the handling of the disabling FBC when VT-d is active wa as part of the intel_fbc_check_plane(). As the hw is still there, intel_fbc_sanitize should be able to handle the state properly. v2: update the patch description (Jani Nikula) v3: fix the return value in wa handling (Jani Nikula) Bspec: 21664 Suggested-by:
Vinod Govindapillai <vinod.govindapillai@intel.com> Reviewed-by:
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Jani Nikula authored
Move the comment about FSB straps to where the relevant register is read. Suggested-by:
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Jani Nikula authored
Instead of duplicating the CLKCFG parsing, reuse i9xx_fsb_freq() to figure out rawclk_freq where applicable. Reviewed-by:
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Jani Nikula authored
Reuse i9xx_fsb_freq() for GT clock frequency initialization instead of depending on rawclk_freq. Note: If the init order was changed, we could use i915->fsb_freq directly. However, GT clock initialization is done in i915_driver_mmio_probe(), but intel_dram_detect() later in i915_driver_hw_probe(), with a dependency on intel_pcode_init(). Reviewed-by:
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Jani Nikula authored
Initialize fsb frequency for more platforms to be able to use it for GT clock and rawclk frequency initialization. Note: There's a discrepancy between existing pnv_fsb_freq() and i9xx_hrawclk() regarding CLKCFG interpretation. Presume all PNV is mobile. Default to 1333 MHz for unknown values, similar to i9xx_hrawclk(). v2: - Add MISSING_CASE() (Ville) - Default to the same frequency for both branches (Ville) Reviewed-by:
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Jani Nikula authored
We'll want to use fsb frequency for deriving GT clock and rawclk frequencies in the future. Increase the accuracy by converting to kHz. Do the same for mem freq to be aligned. Round the frequencies ending in 666 to 667. v2: Also handle mem_freq in gen5_rps_init() (Ville) Reviewed-by:
Matt Roper <matthew.d.roper@intel.com> Reviewed-by:
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Jani Nikula authored
It's a bit out of place, and only printed for VLV/CHV. Reviewed-by:
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Jani Nikula authored
Follow the same style in mem freq init as in fsb freq init, returning the value instead of assigning in multiple places. Reviewed-by:
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Jani Nikula authored
Split out the PNV DDR3 detection to a distinct step instead of conflating it with mem freq detection. Reviewed-by:
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Jani Nikula authored
To simplify further changes, add separate functions for reading the fsb frequency. This ends up reading CLKCFG register twice, but it's not a big deal. Reviewed-by:
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Jani Nikula authored
Clarify and unify the logging on not finding PNV CxSR latency config. Just let the i915->fsb_freq == 0 || i915->mem_freq == 0 case go through the table instead of checking for it separately. v2: Do not check for fsb == 0 || mem == 0 separately (Matt) Reviewed-by:
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Jani Nikula authored
Clarify that the function is specific to PNV, making subsequent changes slightly easier to grasp. Reviewed-by:
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Jani Nikula authored
It's not possible to use the joiner at the same time with eDP MSO. When a panel needs MSO, it's not optional, so MSO trumps joiner. v3: Only change intel_dp_has_joiner(), leave debugfs alone (Ville) Fixes: bc71194e ("drm/i915/edp: enable eDP MSO during link training") Cc: <stable@vger.kernel.org> # v5.13+ Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/1668Reviewed-by:
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- 14 Jun, 2024 5 commits
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Ville Syrjälä authored
No idea what this MST checks is doing in intel_dp_has_audio(). Looks completely pointless, so get rid of it. Signed-off-by:
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Ville Syrjälä authored
Disable eDP DSC usage when instructed to do so by the VBT. Signed-off-by:
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Ville Syrjälä authored
intel_dp_supports_dsc() now works for MST as well, reuse it. Signed-off-by:
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Ville Syrjälä authored
Reuse intel_dp_has_dsc() during .compute_config() instead of repeating some of the checks again by hand. We'll be adding more checks to intel_dp_has_dsc() and this will make sure we cover both .mode_valid() and .compute_config() with them. Signed-off-by:
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Ville Syrjälä authored
Utilize intel_dp_has_dsc() for MST as well. Signed-off-by:
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