- 25 May, 2011 5 commits
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Alex Deucher authored
- no longer in staging - all radeons supported Signed-off-by:
Alex Deucher <alexdeucher@gmail.com> Signed-off-by:
Dave Airlie <airlied@redhat.com>
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Alex Deucher authored
Uses a different method than other evergreen asics. Signed-off-by:
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Alex Deucher authored
The rest of the code is already in place. Signed-off-by:
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Alex Deucher authored
Allows us to use the 3D engine for memory management and allows us to use vram beyond the BAR aperture. v2: fix copy paste typo Reported-by:
Nils Wallménius <nils.wallmenius@gmail.com> Signed-off-by:
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Alex Deucher authored
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- 23 May, 2011 6 commits
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Andrew Morton authored
udelay() doesn't like 8-bit arguments: drivers/gpu/drm/radeon/atom.c: In function 'atom_op_delay': drivers/gpu/drm/radeon/atom.c:653: warning: comparison is always false due to limited range of data type while we're there, use msleep() rather than open-coding it. Cc: David Airlie <airlied@linux.ie> Reviewed-by:
Andrew Morton <akpm@linux-foundation.org> Signed-off-by:
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Alex Deucher authored
- proper bank size for fusion for 2D tiling. Signed-off-by:
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Alex Deucher authored
Needed by userspace for 2D tiled buffer alignment Signed-off-by:
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Alex Deucher authored
It only needs to be called once at startup, not for every modeset. Signed-off-by:
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Alex Deucher authored
Noticed by Droste on IRC. Signed-off-by:
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Alex Deucher authored
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- 22 May, 2011 8 commits
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Dave Airlie authored
cayman is reporting the wrong tile config value to userspace, this causes piglit mipmap generation tests to fail. Reviewed-by:
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Dave Airlie authored
This was leading to a bogus value being programmed to the backend routing register. Reviewed-by:
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Dave Airlie authored
None of the latest GPUs had this hooked up, this is necessary for correct operation in a lot of cases, however we should test this on a few GPUs in these families as we've had problems in this area before. Reviewed-by:
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Dave Airlie authored
On cayman we need to set the bit to cause HDP flushes to invalidate the HDP cache also. Reviewed-by:
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Alex Deucher authored
This needs to be explicitly set on btc. It's set by default on evergreen/fusion, so it fine to just unconditionally enable it for all chips. Signed-off-by:
Dave Airlie <airlied@gmail.com>
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Michel Dänzer authored
This was based on a description by Ben Herrenschmidt: > I've removed that SBA reset from the normal TLB invalidation path and > left it only once after turning AGP on. About six months ago, he said: > I did it a bit differently, but yeah, you get the idea. I'm doing a > patch series so don't bother pushing things too hard yet. But I haven't seen anything from him about this since then, and people are regularly hitting these lockups, so here we are... Signed-off-by:
Michel Dänzer <daenzer@vmware.com> Acked-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by:
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Alex Deucher authored
For DP/eDP, always use the standard DP SS indices. Signed-off-by:
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Alex Deucher authored
If the ss clock is external, the CLK_REF bit needs to be set in the SetPixelClock parameters. This should fix DP failures in the channel equalization loop. Signed-off-by:
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- 20 May, 2011 19 commits
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Alex Deucher authored
It's more like LVDS then DP in some ways. Signed-off-by:
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Alex Deucher authored
Don't try and en/disable the port as it may be a hpd event from powering up/down the panel during a modeset or dpms. Signed-off-by:
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Alex Deucher authored
In the hotplug handler, just use the drm dpms functions. If the monitor is plugged in, turn it on, if it's not, turn it off. This also reduces power usage by turning off the encoder and crtc when the monitor is unplugged. Signed-off-by:
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Alex Deucher authored
- reorganize the functions based on use - clean up function naming - rework link training to better match what we use internally - add initial support for DP 1.2 (no MST yet) Signed-off-by:
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Alex Deucher authored
Required for proper operation with DP bridges. Signed-off-by:
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Alex Deucher authored
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Alex Deucher authored
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Alex Deucher authored
Fusion hardware often has DP to VGA/LVDS/TMDS bridges to handle non-DP encoders. Internally we treat them mostly like DP. Signed-off-by:
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Alex Deucher authored
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Alex Deucher authored
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Alex Deucher authored
Used for dp1.2 support and for dp bridges. Signed-off-by:
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Alex Deucher authored
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Alex Deucher authored
need to wait for the panel to power up. Signed-off-by:
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Alex Deucher authored
eDP is usually used as an LVDS replacement, so treat it more like LVDS from the user perspective. v2: encoder mode is always DP for eDP. Signed-off-by:
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Alex Deucher authored
In DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock, depending on the asic. The crtc virtual pixel clock is derived from the DP ref clock. - DCE4: PPLL or ext clock - DCE5: DCPLL or ext clock Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip PPLL/DCPLL programming and only program the DP DTO for the crtc virtual pixel clock. Signed-off-by:
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Alex Deucher authored
- properly mask the ss type - don't enable ss if type is external or percentage is 0 - if ss enabled and type is external, set ref_div_src to ext clock - prefer ASIC_INTERNAL_SS_ON_DP to LCD_Info SS_Id for eDP - fix ss amount calculation Signed-off-by:
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Alex Deucher authored
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Alex Deucher authored
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Dave Airlie authored
* 'keithp/drm-intel-next' of ../drm-next: drm/i915: initialize gen6 rps work queue on Sandy Bridge and Ivy Bridge drm/i915/sdvo: Reorder i2c initialisation before ddc proxy drm/i915: FDI link training broken on Ironlake by Ivybridge integration drm/i915: enable rc6 by default drm/i915: add fbc enable flag, but disable by default drm/i915: clean up unused ring_get_irq/ring_put_irq functions drm/i915: fix user irq miss in BSD ring on g4x
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- 18 May, 2011 2 commits
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Jesse Barnes authored
It's not used on Ironlake, but is used on later generations, so make sure it exists before we try to use it in the interrupt handlers. Signed-off-by:
Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by:
Keith Packard <keithp@keithp.com> Signed-off-by:
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Chris Wilson authored
The ddc proxy depends upon the underlying i2c bus being selected. Under certain configurations, the i2c-adapter functionality is queried during initialisation and so may trigger an OOPS during boot. Hence, we need to reorder the initialisation of the ddc proxy until after we hook up the i2c adapter for the SDVO device. The condition under which it fails is when the i2c_add_adapter calls into i2c_detect which will attempt to probe all valid addresses on the adapter iff there is a pre-existing i2c_driver with the same class as the freshly added i2c_adapter. So it appears to depend upon having compiled in (or loaded such a module before i915.ko) an i2c-driver that likes to futz over the i2c_adapters claiming DDC support. Reported-by:
Mihai Moldovan <ionic@ionic.de> Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by:
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