- 16 Aug, 2024 16 commits
-
-
Alex Deucher authored
It's not supported under SR-IOV at the moment. Acked-by:
Vitaly Prosyak <vitaly.prosyak@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
-
Jiadong Zhu authored
Using mmio to do queue reset. Enter safe mode before writing mmio registers. v2: set register instance offset according to xcc id. Acked-by:
Jiadong Zhu <Jiadong.Zhu@amd.com> Reviewed-by:
-
Jiadong Zhu authored
Using mmio to do queue reset. Enter safe mode when writing registers. Acked-by:
-
Jiadong Zhu authored
Add reset_hw_queue in kiq_pm4_funcs callbacks. Acked-by:
-
Jiadong Zhu authored
There is a racing condition that cp firmware modifies MQD in reset sequence after driver updates it for remapping. We have to wait till CP_HQD_ACTIVE becoming false then remap the queue. v2: fix KIQ locking (Alex) v3: fix KIQ locking harder Acked-by:
-
Jiadong Zhu authored
Kiq command unmap_queues only does the dequeueing action. We have to map the queue back with clean mqd. Acked-by:
-
Alex Deucher authored
Add ring reset callback for compute. Acked-by:
-
Jiadong Zhu authored
There is a racing condition that cp firmware modifies MQD in reset sequence after driver updates it for remapping. We have to wait till CP_HQD_ACTIVE becoming false then remap the queue. v2: fix KIQ locking (Alex) v3: fix KIQ locking harder Acked-by:
-
Jiadong Zhu authored
Kiq command unmap_queues only does the dequeueing action. We have to map the queue back with clean mqd. Acked-by:
-
Alex Deucher authored
Add ring reset callback for compute. Acked-by:
-
Prike Liang authored
Update the reset counter for the amdgpu_cs_query_reset_state() Acked-by:
Prike Liang <Prike.Liang@amd.com> Reviewed-by:
-
Alex Deucher authored
If a specific job is hung, try and reset just the ring associated with the job. v2: move to amdgpu_job.c v3: fix drm_sched_stop() handling when ring reset fails v4: drop unnecessary amdgpu_fence_driver_clear_job_fences() and drm_sched_increase_karma() v5: rework sched_stop handling Acked-by: -
Alex Deucher authored
Use this to reset just a single ring. Acked-by:
-
Soham Dandapat authored
As we don't trigger preemption is sw ring muxer when mcbp is disabled,so return earlier in amdgpu_sw_ring_ib_end function if mcbp is disabled ,not required to call amdgpu_ring_mux_end_ib Signed-off-by:
Soham Dandapat <sdandapa@amd.com> Acked-by:
-
Sunil Khatri authored
Add gfx9_4_3 print support of CP queue registers for all queues to be used by devcoredump. Signed-off-by:
Sunil Khatri <sunil.khatri@amd.com> Reviewed-by:
-
Sunil Khatri authored
Add gfx9 support of CP queue registers for all queues to be used by devcoredump. Signed-off-by:
-
- 13 Aug, 2024 24 commits
-
-
Srinivasan Shanmugam authored
The descriptor for `hwss_wait_for_all_blank_complete` was previously misaligned with the actual implementation. This commit refines the descriptor to reflect the implementation of `hwss_wait_for_all_blank_complete` Fixes the below with gcc W=1: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_hw_sequencer.c:991: warning: expecting prototype for hwss_wait_for_blank_complete(). Prototype was for hwss_wait_for_all_blank_complete() instead Cc: Tom Chung <chiahsuan.chung@amd.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Roman Li <roman.li@amd.com> Cc: Alex Hung <alex.hung@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by:
Tom Chung <chiahsuan.chung@amd.com> Signed-off-by:
-
Sunil Khatri authored
Add support of gfx9_4_3 ipdump print so devcoredump could trigger it to dump the captured registers in devcoredump. Signed-off-by:
-
Sunil Khatri authored
Add general registers of gfx9_4_3 in ipdump for devcoredump support. Signed-off-by:
-
David (Ming Qiang) Wu authored
Because gpu_addr is updated in the calling routine (amdgpu_cs_patch_ibs()),it is removed in the callback. Use .patch_cs_in_place instead of .parse_cs for amdgpu_vce_ring_parse_cs_vm() as there is no need for keeping a temporary IB, therefore ib->sa_bo is NULL and amdgpu_ib_free() is removed. Reviewed-by:
David (Ming Qiang) Wu <David.Wu3@amd.com> Signed-off-by:
-
David (Ming Qiang) Wu authored
Add JPEG IB command parser to ensure registers in the command are within the JPEG IP block. Reviewed-by:
-
Jack Xiao authored
Use mes pipe to unmap kcq and kgq. Signed-off-by:
Jack Xiao <Jack.Xiao@amd.com> Acked-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
-
Jack Xiao authored
Free memory for two pipes and unmap pipe0 via pipe1. Signed-off-by:
-
Jack Xiao authored
Configure two pipes with different hardware resources. Signed-off-by:
-
Jack Xiao authored
Adjust mes12 sw/hw initiailization for both pipe0 and pipe1 enablement. The two pipes are almost identical pipe. Pipe0 behaves like schq and pipe1 like kiq, pipe0 was mapped by pipe1. Signed-off-by:
-
Jack Xiao authored
Add mes pipe switch to let caller choose pipe to submit packet. Signed-off-by:
-
Victor Skvortsov authored
Register access from userspace should be blocked until reset is complete. Signed-off-by:
Victor Skvortsov <victor.skvortsov@amd.com> Reviewed-by:
-
Jonathan Kim authored
If queue reset fails, tell the CP to reset the pipe. Since queues multiplex context per pipe and we've issued a device wide preemption prior to the hang, we can assume the hung pipe only has one queue to reset on pipe reset. Signed-off-by:
Jonathan Kim <jonathan.kim@amd.com> Reviewed-by:
-
Lijo Lazar authored
On EFI BIOSes, PCI ROM may be exported through EFI_PCI_IO_PROTOCOL and expansion ROM BARs may not be enabled. Choose to read from EFI exported ROM data before reading PCI Expansion ROM BAR. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
-
Jack Xiao authored
Enable unified mes firmware to load on pipe0 and pipe1. Signed-off-by:
-
Victor Skvortsov authored
VFs do not perform HW fini/suspend in FLR, so the dpm_enabled is incorrectly kept enabled. Add interface to disable it in virt_pre_reset call. v2: Made implementation generic for all asics v3: Re-order conditionals so PP_MP1_STATE_FLR is only evaluated on VF Signed-off-by:
-
Victor Skvortsov authored
KIQ timeouts no longer seen. This reverts commit 3a19a8af. Signed-off-by:
Zhigang Luo <zhigang.luo@amd.com> Signed-off-by:
-
Yinjie Yao authored
kmd_fw_shared changed in VCN5 Signed-off-by:
Yinjie Yao <yinjie.yao@amd.com> Reviewed-by:
Ruijing Dong <ruijing.dong@amd.com> Acked-by:
-
Lijo Lazar authored
If there are multiple nodes per kfd device, add nodeid to location_id to differentiate. Signed-off-by:
-
Kenneth Feng authored
add HDP_SD support on gc 12.0.0/1 Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
Yang Wang <kevinyang.wang@amd.com> Signed-off-by:
-
Victor Zhao authored
on MI300/MI308 UBB products, when doing mode1 reset, since 1 gpu need to wait all 8 gpus finish mode1 reset and then do re-init. As observed, sometimes the gpu which triggered the reset need to wait 15s for all gpus to finish. If poll msg timeout, guest driver will send the reset message again, and may mess up the following reinit sequence on other gpus. So extend the time to cover the maximum time needed to recover. Signed-off-by:
Victor Zhao <Victor.Zhao@amd.com> Acked-by:
-
Martin Leung authored
This version brings along following fixes: - Fix some cursor issue - Fix print format specifiers in DC_LOG_IPS - Fix minor coding errors in dml21 phase 5 - Fix MST BW calculation Regression - Improve FAM control for DCN401 - Add null pointer checks for some code - Refactor 3DLUT for non-DMA - Optimize vstartup position for AS-SDP - Update to using new dccg callbacks - Enable otg synchronization logic for DCN321 - Disable DCN401 UCLK P-State support on full updates Acked-by:
Wayne Lin <wayne.lin@amd.com> Signed-off-by:
Martin Leung <Martin.Leung@amd.com> Signed-off-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
-
Rodrigo Siqueira authored
[why & how] Remove unnecessary call to REG_SEQ_SUBMIT and REG_SEQ_WAIT_DONE, since those macros are not necessary anymore at the dpp1 set degamma. Those are part of an old implementation. Acked-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
-
Rodrigo Siqueira authored
[why & how] When the commit 9d84c7ef ("drm/amd/display: Correct cursor position on horizontal mirror") was introduced, it used the wrong calculation for the position copy for X. This commit uses the correct calculation for that based on the original patch. Fixes: 9d84c7ef ("drm/amd/display: Correct cursor position on horizontal mirror") Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Acked-by:
-
Melissa Wen authored
[why & how] Cursor gets clipped off in the middle of the screen with hw rotation 180. Fix a miscalculation of cursor offset when it's placed near the edges in the pipe split case. Cursor bugs with hw rotation were reported on AMD issue tracker: https://gitlab.freedesktop.org/drm/amd/-/issues/2247 The issues on rotation 270 was fixed by: https://lore.kernel.org/amd-gfx/20221118125935.4013669-22-Brian.Chang@amd.com/ that partially addressed the rotation 180 too. So, this patch is the final bits for rotation 180. Reported-by:
Xaver Hugl <xaver.hugl@gmail.com> Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/2247Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Fixes: 9d84c7ef ("drm/amd/display: Correct cursor position on horizontal mirror") Signed-off-by:
Melissa Wen <mwen@igalia.com> Signed-off-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
-
