- 23 Sep, 2022 1 commit
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Ville Syrjälä authored
The plane ratio stuff got implemented in commit bb6ae9e6 ("drm/i915: Allow planes to declare their minimum acceptable cdclk") so these FIXMEs have no business being here. Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220916165206.1499-1-ville.syrjala@linux.intel.comReviewed-by:
Luca Coelho <luciano.coelho@intel.com>
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- 20 Sep, 2022 2 commits
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Ville Syrjälä authored
Replace the mutex_is_locked() stuff with lockdep_assert_held() since that's what it's there for. Also sprinkle these around so that we have more or less mirrored coverage for the enable vs. disable instead of the current situation where the asserts seem to be more or less randomly thrown around. Signed-off-by:
Mika Kahola <mika.kahola@intel.com>
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Ville Syrjälä authored
Move the flip_pending assignment into __intel_fbc_post_update() from intel_fbc_post_update(). Now mirrors the pre_update() side. The only reason the assignment was in the higher level function is that we used to call __intel_fbc_post_update() from elsewhere as well. That got cleaned up in commit b39d2c62 ("drm/i915/fbc: Call intel_fbc_activate() directly from frontbuffer flush") Signed-off-by:
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- 19 Sep, 2022 4 commits
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Ville Syrjälä authored
We don't parse the VBT vswing/preemphassis tables at all currently. Let's WARN if a port wants to use them so we get a heads up that whether we really need to implement this stuff or not. My current stash contains no VBTs with this bit set. v2: Move to print_ddi_port() (Jani) Reviewed-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
Jani Nikula <jani.nikula@intel.com>
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Jani Nikula authored
The ipc_enabled member was supposed to be moved under the display wm sub-struct, but due to a rebase fail only the new one was added and the old one was left behind. Finish the job. Fixes: 70296670 ("drm/i915/display: move IPC under display wm sub-struct") Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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Jani Nikula authored
Rename intel_hpd_init_work() to the more generic intel_hpd_init_early(), and move the hotplug storm initialization there. This lets us move the HPD_STORM_DEFAULT_THRESHOLD macro to intel_hotplug.c too. Signed-off-by:
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Jani Nikula authored
The debugfs should be where the implementation details are. v2: Rebase Signed-off-by:
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- 15 Sep, 2022 1 commit
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Nathan Huckleberry authored
All of the functions used for intel_dvo_dev_ops.mode_valid have a return type of enum drm_mode_status, but the mode_valid field in the struct definition has a return type of int. The mismatched return type breaks forward edge kCFI since the underlying function definitions do not match the function hook definition. The return type of the mode_valid field should be changed from int to enum drm_mode_status. Reported-by:
Dan Carpenter <error27@gmail.com> Link: https://github.com/ClangBuiltLinux/linux/issues/1703 Cc: llvm@lists.linux.dev Signed-off-by:
Nathan Huckleberry <nhuck@google.com> Reviewed-by:
Nathan Chancellor <nathan@kernel.org> Reviewed-by:
Andrzej Hajda <andrzej.hajda@intel.com> Signed-off-by:
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- 14 Sep, 2022 3 commits
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Madhumitha Tolakanahalli Pradeep authored
In Display version 14, Transcoder Chicken Registers have updated address. This patch performs checks to use the right register when required. v2: Omit display version check in i915_reg.h(Jani) v3: - Remove extra whitespace introduced - Fix reg definitions for MTL_CHICKEN_TRANS(MattR) Bspec: 34387, 50054 Cc: Jani Nikula <jani.nikula@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by:
Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com> Signed-off-by:
Radhakrishna Sripada <radhakrishna.sripada@intel.com> Reviewed-by:
Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220913183341.908028-6-radhakrishna.sripada@intel.com
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Radhakrishna Sripada authored
Display version 14 platforms have different credits values compared to ADL-P. Update the credits based on pipe usage. v2: Simplify DBOX BW Credit definition(MattR) v3: - Simplify only pipe per dbuf bank check(MattR) - Skip modeset check to handle the case when a new pipe within dbuf bank gets added/removed.(MattR) Bspec: 49213 Cc: Jose Roberto de Souza <jose.souza@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Original Author: Caz Yokoyama Signed-off-by:
José Roberto de Souza <jose.souza@intel.com> Signed-off-by:
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Swati Sharma authored
Convert dsc debugfs entry from output_bpp to input_bpc. The rationale is to validate different input bpc across various platforms. v2: -improved commit message (Jani N) -styling fixes (Jani N) Signed-off-by:Swati Sharma <swati2.sharma@intel.com> Reviewed-by:
Manasi Navare <manasi.d.navare@intel.com> Acked-by:
Uma Shankar <uma.shankar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220902190658.9459-2-swati2.sharma@intel.com
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- 13 Sep, 2022 13 commits
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Jani Nikula authored
Don't duplicate the rmw function. Signed-off-by:
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Jani Nikula authored
Move display IPC related member under drm_i915_private display sub-struct. Signed-off-by:
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Jani Nikula authored
It looks like trying to enable IPC via debugfs on platforms that don't have IPC resulted in dmesg info message about IPC being enabled, which is clearly not possible and would not happen. Seems sensible to register IPC debugfs only on platforms that have IPC. Signed-off-by:
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Jani Nikula authored
Follow the new direction for debugfs files, moving the details where the implementation is. It seems quite natural skl_watermark.c is the place that controls IPC details, even for debugfs, not intel_display_debugfs.c. Rename the functions and convert dev_priv->i915 while at it. Signed-off-by:
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Jani Nikula authored
Rename the IPC functions to have skl_watermark_ipc_ prefix, rename enable to update to reflect what the function actually does, and add enabled function to abstract direct ->ipc_enabled access for state query. Signed-off-by:
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Jouni Högander authored
Use existing drm_atomic_helper_damage_merged from generic drm code instead of implementing own loop to iterate over damage_clips. Signed-off-by:
Jouni Högander <jouni.hogander@intel.com> Signed-off-by:
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Jouni Högander authored
drm_plane_state->src is modified when offset is calculated: before calculation: src.x1 = 8192, src.y1 = 8192 after calculation (pitch = 65536, cpp = 4, alignment = 262144) src.x1 = 8192, src.y1 = 0, offset = 0x20000000 Damage clips are relative to original coodrdinates provided by user-space. To compare these against src coordinates we need to use original coordinates as provided by user-space. These can be obtained by using drm_plane_state_src. Signed-off-by:
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Jouni Högander authored
Selective update doesn't work if SU start address is 0 and start/end SDP is configured to be sent prior to SU start/end lines. PSR2 has to be disabled in this case for Alder Lake. HSDES: 22012279113 Cc: Mika Kahola <mika.kahola@intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by:
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Jouni Högander authored
Equation for sending start/end SDP prior to the SU region start/end has changed. Update used formula. Bspec: 49274 Cc: Mika Kahola <mika.kahola@intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by:
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Ville Syrjälä authored
The TV encoder has its own special clocking strategy, which means we can't just use intel_crtc_dotclock() to figure out what the resulting dotclock will be given the actual DPLL port_clock. Additionally the DPLL can't always generate exactly the frequency we initially asked for. This results in us computing a bogus dotclock/etc., and it won't match the readout which is handled by the encoder itself properly. Naturally the state checker becomes unhappy with the mismatch. To do this sanely we'll need to move the DPLL computation into encoder->compute_config() so that all the derived state gets correctly computed based on the actual DPLL output frequency. Start doing that just for the TV encoder initally as intel_crtc_dotclock() should be able to handle other encoder types well enough. Though eventually this should be done for all encoder types rather than doing it from intel_crtc_compute_config(). With this we actually do some of the DPLL state computation twice, but we can skip the second actual .find_dpll() search by flagging .clock_set=true after we've done it once. We also still need to avoid clobbering the correct adjusted_mode.crtc_clock set up by encoder->compute_config() when called a second time from intel_crtc_compute_config(). Fixes: 665a7b04 ("drm/i915: Feed the DPLL output freq back into crtc_state") Signed-off-by:
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Ville Syrjälä authored
The child device block has gained a new bit for disabling compression for external displays. Seems stupid, but there it is. Signed-off-by:
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Ville Syrjälä authored
We have the ACPI vs. not ACPI DPMS bit polarity the wrong way around. Fix it. Signed-off-by:
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Jani Nikula authored
Drop the local intel_dp_phy_name() function, and replace with drm_dp_phy_name(). This lets us drop a number of local buffers. v2: Rebase Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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- 12 Sep, 2022 6 commits
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Radhakrishna Sripada authored
From Meteorlake, Latency Level, SAGV bloack time are read from LATENCY_SAGV register instead of the GT driver pcode mailbox. DDR type and QGV information are also to be read from Mem SS registers. v2: - Simplify MTL_MEM_SS_INFO_QGV_POINT macro(MattR) - Nit: Rearrange the bit def's from higher to lower(MattR) - Restore platform definition for ADL-P(MattR) - Move back intel_qgv_point def to intel_bw.c(Jani) v3: - Rebase Bspec: 64636, 64608 Cc: Jani Nikula <jani.nikula@intel.com> Reviewed-by:
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Imre Deak authored
On MTL TypeC ports the AUX_CH_CTL and AUX_CH_DATA addresses have changed wrt. previous platforms, adjust the code accordingly. Signed-off-by:
Imre Deak <imre.deak@intel.com> Signed-off-by:
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Imre Deak authored
Add support for display power wells on MTL. The differences from XE_LPD: - The AUX HW block is moved to the PICA block, where the registers are on an always-on power well and the functionality needs to be powered on/off via the AUX_CH_CTL register: [1], [2] - The DDI IO power on/off programming sequence is moved to the PHY PLL enable/disable sequence. [3], [4], [5] Bspec: [1] 49233, [2] 65247, [3] 64568, [4] 65451, [5] 65450 v2: - Update the comment in aux power well enable - Reuse the noop sync fn for aux sync. - Use REG_BIT for new register bit definitions Signed-off-by:
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Radhakrishna Sripada authored
Add tables to map the GMBUS pin pairs to GPIO registers and port to DDC. From spec we have registers GPIO_CTL[1-5] mapped to native display phys and GPIO_CTL[9-12] are mapped to TC ports. v2: - Drop unused GPIO pins(MattR) BSpec: 49306 Cc: Matt Roper <matthew.d.roper@intel.com> Original Author: Brian J Lovin Signed-off-by:
Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Reviewed-by:
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Radhakrishna Sripada authored
Future platforms can read the IP version from a register and the IP version numbers need not be hard coded in device info. Move the ip version for media and display to runtime info. On platforms where hard coding of IP version is required, update the IP version in __runtime under device_info. v2: - Avoid name collision for ip versions(Jani) v4.1: - Fix build error in mock_gem_device.c v4.2: - Use ip instead of version for ip_vesion member.(MattR) Suggested-by:
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Jani Nikula authored
Backmerge to sync the DP MST atomic changes to drm-intel-next. Signed-off-by:
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- 11 Sep, 2022 2 commits
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Melissa Wen authored
Replace vkms_formats macro for fixed-point operations with functions from drm/drm_fixed.h to do the same job and fix 32-bit compilation errors. v2: - don't cast results to s32 (Igor) - add missing drm_fixp2int conversion (Igor) Fixes: a19c2ac9858 ("drm: vkms: Add support to the RGB565 format") Tested-by: Sudip Mukherjee <sudipm.mukherjee@gmail.com> (v1) Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (v1) Reported-by:Sudip Mukherjee <sudipm.mukherjee@gmail.com> Reported-by:
kernel test robot <lkp@intel.com> Signed-off-by:
Melissa Wen <mwen@igalia.com> Signed-off-by:
Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220910190303.682897-1-mwen@igalia.com
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git://anongit.freedesktop.org/drm/drm-miscDave Airlie authored
drm-misc-next for v6.1-rc1: [airlied - fix sun4i_tv build] UAPI Changes: - Hide unregistered connectors from GETCONNECTOR ioctl. - drm/virtio no longer advertises LINEAR modifier, as it doesn't work. - Cross-subsystem Changes: - Fix GPF in udmabuf failure path. Core Changes: - Rework TTM placement to use intersect/compatible functions. - Drop legacy DP-MST support. - More DP-MST related fixes, and move all state into atomic. - Make DRM_MIPI_DBI select DRM_KMS_HELPER. - Add audio_infoframe packing for DP. - Add logging when some atomic check functions fail. - Assorted documentation updates and fixes. Driver Changes: - Assorted cleanups and fixes in msm, lcdif, nouveau, virtio, panel/ilitek, bridge/icn6211, tve200, gma500, bridge/*, panfrost, via, bochs, qxl, sun4i. - Add add AUO B133UAN02.1, IVO M133NW4J-R3, Innolux N120ACA-EA1 eDP panels. - Improve DP-MST modeset state handling in amdgpu, nouveau, i915. - Drop DP-MST from radeon driver, it was broken and only user of legacy DP-MST. - Handle unplugging better in vc4. - Simplify drm cmdparser tests. - Add DP support to ti-sn65dsi86. - Add MT8195 DP support to mediatek. - Support RGB565, XRGB64, and ARGB64 formats in vkms. - Convert sun4i tv support to atomic. - Refactor vc4/vec TV Modesetting, and fix timings. - Use atomic helpers instead of simple display helpers in ssd130x. Maintainer changes: - Add Douglas Anderson as reviewer for panel-edp. Signed-off-by:
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- 09 Sep, 2022 4 commits
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Ville Syrjälä authored
Replace the hand rolled stuff with REG_FIELD_GET() for reading out the skl+ watermark latencies. Signed-off-by:
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Ville Syrjälä authored
Pull all the skl+ watermark code (and the dbuf/sagv/ipc code since it's all sort of intertwined and I'm too lazy to think of a finer grained split right now) into its own file from the catch-all intel_pm.c. Also sneak in the s/dev_priv/i915/ rename while at it. Signed-off-by:
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Ville Syrjälä authored
No reaon to have this humongous if ladder in intel_read_wm_latency(). Just split it into nicer per-platforms functions. Also do the s/dev_priv/i915/ while touching all of this code. Signed-off-by:
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Jani Nikula authored
struct intel_dsb can be an opaque type, hidden in intel_dsb.c. Make it so. Reduce related includes while at it. Signed-off-by:
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- 08 Sep, 2022 4 commits
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Imre Deak authored
When an MST connector stays enabled during a commit the connector's MST state needs to be added to the atomic state, but the corresponding MST payload allocation shouldn't be set for deletion; fix such modesets by ensuring the above even if the connector was already enabled before the modeset. The issue led to the following: [ 761.992923] i915 0000:00:02.0: drm_WARN_ON(payload->delete) [ 761.992949] WARNING: CPU: 6 PID: 1401 at drivers/gpu/drm/display/drm_dp_mst_topology.c:4221 drm_dp_atomic_find_time_slots+0x236/0x280 [drm_display_helper] [ 761.992955] Modules linked in: snd_hda_intel i915 drm_buddy drm_display_helper drm_kms_helper ttm drm snd_hda_codec_hdmi snd_intel_dspcfg snd_hda_codec snd_hwdep snd_hda_core snd_pcm prime_numbers i2c_algo_bit syscopyarea sysfillrect sysimgblt fb_sys_fops x86_pkg_temp_thermal cdc_ether coretemp crct10dif_pclmul usbnet crc32_pclmul mii ghash_clmulni_intel e1000e mei_me ptp i2c_i801 pps_core mei i2c_smbus intel_lpss_pci fuse [last unloaded: drm] [ 761.992986] CPU: 6 PID: 1401 Comm: testdisplay Tainted: G U 6.0.0-rc4-imre+ #565 [ 761.992989] Hardware name: Intel Corporation Alder Lake Client Platform/AlderLake-P DDR5 RVP, BIOS ADLPFWI1.R00.3135.A00.2203251419 03/25/2022 [ 761.992990] RIP: 0010:drm_dp_atomic_find_time_slots+0x236/0x280 [drm_display_helper] [ 761.992994] Code: 4c 8b 67 50 4d 85 e4 75 03 4c 8b 27 e8 03 28 4e e1 48 c7 c1 8b 26 2c a0 4c 89 e2 48 c7 c7 a8 26 2c a0 48 89 c6 e8 31 d5 88 e1 <0f> 0b 49 8b 85 d0 00 00 00 4c 89 fa 48 c7 c6 a0 41 2c a0 48 8b 78 [ 761.992995] RSP: 0018:ffffc9000177ba60 EFLAGS: 00010286 [ 761.992998] RAX: 0000000000000000 RBX: ffff88810d2f1540 RCX: 0000000000000000 [ 761.992999] RDX: 0000000000000001 RSI: ffffffff82368a25 RDI: 00000000ffffffff [ 761.993000] RBP: ffff888142299d80 R08: ffff8884adbfdfe8 R09: 00000000ffefffff [ 761.993001] R10: ffff8884a6bfe000 R11: ffff8884ac443c30 R12: ffff888102972f90 [ 761.993002] R13: ffff8881163e2cf0 R14: 00000000000003ac R15: ffff88810c501000 [ 761.993003] FS: 00007f81e4c459c0(0000) GS:ffff888496500000(0000) knlGS:0000000000000000 [ 761.993004] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 761.993005] CR2: 0000555dac962a98 CR3: 0000000123a34006 CR4: 0000000000770ee0 [ 761.993006] PKRU: 55555554 [ 761.993007] Call Trace: [ 761.993009] <TASK> [ 761.993012] intel_dp_mst_compute_config+0x19a/0x350 [i915] [ 761.993090] intel_atomic_check+0xf37/0x3180 [i915] [ 761.993168] drm_atomic_check_only+0x5d3/0xa60 [drm] [ 761.993182] drm_atomic_commit+0x56/0xc0 [drm] [ 761.993192] ? drm_plane_get_damage_clips.cold+0x1c/0x1c [drm] [ 761.993204] drm_atomic_helper_set_config+0x78/0xc0 [drm_kms_helper] [ 761.993214] drm_mode_setcrtc+0x1ed/0x750 [drm] [ 761.993232] ? drm_mode_getcrtc+0x180/0x180 [drm] [ 761.993241] drm_ioctl_kernel+0xb5/0x150 [drm] [ 761.993252] drm_ioctl+0x203/0x3d0 [drm] [ 761.993261] ? drm_mode_getcrtc+0x180/0x180 [drm] [ 761.993276] __x64_sys_ioctl+0x8a/0xb0 [ 761.993281] do_syscall_64+0x38/0x90 [ 761.993285] entry_SYSCALL_64_after_hwframe+0x63/0xcd [ 761.993287] RIP: 0033:0x7f81e551aaff [ 761.993288] Code: 00 48 89 44 24 18 31 c0 48 8d 44 24 60 c7 04 24 10 00 00 00 48 89 44 24 08 48 8d 44 24 20 48 89 44 24 10 b8 10 00 00 00 0f 05 <41> 89 c0 3d 00 f0 ff ff 77 1f 48 8b 44 24 18 64 48 2b 04 25 28 00 [ 761.993290] RSP: 002b:00007fff4304af10 EFLAGS: 00000246 ORIG_RAX: 0000000000000010 [ 761.993292] RAX: ffffffffffffffda RBX: 00007fff4304afa0 RCX: 00007f81e551aaff [ 761.993293] RDX: 00007fff4304afa0 RSI: 00000000c06864a2 RDI: 0000000000000004 [ 761.993294] RBP: 00000000c06864a2 R08: 0000000000000000 R09: 0000555dac8a9c68 [ 761.993294] R10: 0000000000000000 R11: 0000000000000246 R12: 00000000000008c4 [ 761.993295] R13: 0000000000000004 R14: 0000555dac8a9c68 R15: 00007fff4304b098 [ 761.993301] </TASK> Fixes: 083351e9 ("drm/display/dp_mst: Fix modeset tracking in drm_dp_atomic_release_vcpi_slots()") Testcase: igt@testdisplay Cc: Lyude Paul <lyude@redhat.com> Signed-off-by:
Lyude Paul <lyude@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220907142542.1681994-1-imre.deak@intel.com
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Chen-Yu Tsai authored
This panel has the same delay timing as N116BCA-EA1 from the same company, which is also the same as delay_200_500_e80_d50. Add an entry for it. Signed-off-by:
Chen-Yu Tsai <wenst@chromium.org> Reviewed-by:
Douglas Anderson <dianders@chromium.org> Signed-off-by:
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Maxime Ripard authored
Our mode_set implementation can be merged into our atomic_enable implementation to simplify things, so let's do this. Acked-by:
Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by:
Maxime Ripard <maxime@cerno.tech> Link: https://patchwork.freedesktop.org/patch/msgid/20220728-rpi-analog-tv-properties-v2-36-459522d653a7@cerno.tech
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Ville Syrjälä authored
Use round-to-nearest behavour when calculating the TMDS clock. Matches what we do for most other clock related things. Acked-by:
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