- 06 Apr, 2023 1 commit
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Rob Clark authored
Preparing for better lockdep annotations for things that happen in runpm suspend/resume path vs shrinker/reclaim in the following patches, we need to avoid allocations that can trigger reclaim in the icc_set_bw() path. In the RPMh case, rpmh_write_batch() already uses GFP_ATOMIC, so it should be reasonable to use in the smd-rpm case as well. Alternatively, 256bytes is small enough for a function that isn't called recursively to allocate on-stack. Signed-off-by:
Rob Clark <robdclark@chromium.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230320144356.803762-21-robdclark@gmail.com
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- 05 Apr, 2023 2 commits
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Vinod Koul authored
Document the compatible for Qualcomm sc8180x SCM. Acked-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
Vinod Koul <vkoul@kernel.org> Signed-off-by:
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Konrad Dybcio authored
Add a compatible for SM6375 IMEM. Acked-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
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- 04 Apr, 2023 2 commits
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Konrad Dybcio authored
The BWMON hardware has two sets of registers: one for the monitor itself and one called "global". It has what seems to be some kind of a head switch and an interrupt control register. It's usually 0x200 in size. On fairly recent SoCs (with the starting point seemingly being moving the OSM programming to the firmware) these two register sets are contiguous and overlapping, like this (on sm8450): /* notice how base.start == global_base.start+0x100 */ reg = <0x90b6400 0x300>, <0x90b6300 0x200>; reg-names = "base", "global_base"; Which led to some confusion and the assumption that since the "interesting" global registers begin right after global_base+0x100, there's no need to map two separate regions and one can simply subtract 0x100 from the offsets. This is however not the case for anything older than SDM845, as the global region can appear in seemingly random spots on the register map. Handle the case where the global registers are mapped separately to allow proper functioning of BWMONv4 on MSM8998 and older. Add specific compatibles for 845, 8280xp, 7280 and 8550 (all of which use the single reg space scheme) to keep backwards compatibility with old DTs. Signed-off-by:
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Konrad Dybcio authored
bwmon->regmap was never used, as the regmap for bwmon is registered through devres and accessed through bwmon's regmap_field members. Remove it Fixes: ec63dcd3 ("soc: qcom: icc-bwmon: use regmap and prepare for BWMON v5") Reviewed-by:
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- 24 Mar, 2023 1 commit
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Ye Xingchen authored
Replace the open-code with dev_err_probe() to simplify the code. Signed-off-by:
Ye Xingchen <ye.xingchen@zte.com.cn> Signed-off-by:
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- 22 Mar, 2023 7 commits
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Konrad Dybcio authored
While it was introduced in bindings, requiring a core clock, and added into the DT, this compatible was apparently forgotten about on the driver side of things. Fix it. Signed-off-by:
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Danila Tikhonov authored
Add LLCC configuration data for SM7150 SoC. Signed-off-by:
Danila Tikhonov <danila@jiaxyga.com> Reviewed-by:
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Danila Tikhonov authored
Add LLCC compatible for SM7150 SoC. Signed-off-by:
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Krzysztof Kozlowski authored
Re-add the qcom,rpm-msm8994 compatible, dropped during conversion from TXT to DT schema: apq8094-sony-xperia-kitakami-karin_windy.dtb: smd: rpm:rpm-requests:compatible:0: 'qcom,rpm-msm8994' is not one of ['qcom,rpm-apq8084' ...] Fixes: f935a752 ("dt-bindings: soc: qcom: smd-rpm: Convert binding to YAML schema") Signed-off-by:
Rob Herring <robh@kernel.org> Reviewed-by:
Petr Vorel <petr.vorel@gmail.com> Reviewed-by:
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Neil Armstrong authored
Only register UCSI on know working devices, like on the SM8450 or SM8550 which requires UCSI to get USB mode switch events. Signed-off-by:
Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
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Neil Armstrong authored
Document the SM8550 compatible used to describe the pmic glink on this platform. Acked-by:
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Neil Armstrong authored
Document the SM8450 compatible used to describe the pmic glink on this platform. Acked-by:
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- 20 Mar, 2023 1 commit
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Mukesh Ojha authored
During normal restart of a system download bit should be cleared irrespective of whether download mode is set or not. Fixes: 8c1b7dc9 ("firmware: qcom: scm: Expose download-mode control") Signed-off-by:
Mukesh Ojha <quic_mojha@quicinc.com> Signed-off-by:
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- 16 Mar, 2023 3 commits
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Melody Olvera authored
Add compatible for QDU1000 and QRU1000 aoss devices. Signed-off-by:
Melody Olvera <quic_molvera@quicinc.com> Acked-by:
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Melody Olvera authored
Update compatible for QDU1000 and QRU1000 to include the interconnect these devices have. Signed-off-by:
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Devi Priya authored
Document the compatible for RPM communication over SMD for IPQ9574 SoC Signed-off-by:
Devi Priya <quic_devipriy@quicinc.com> Acked-by:
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- 15 Mar, 2023 23 commits
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Elliot Berman authored
The maximum VMID for assign_mem is 63. Use a u64 to represent this bitmap instead of architecture-dependent "unsigned int" which varies in size on 32-bit and 64-bit platforms. Acked-by: Kalle Valo <kvalo@kernel.org> (ath10k) Tested-by:
Gokul krishna Krishnakumar <quic_gokukris@quicinc.com> Signed-off-by:
Elliot Berman <quic_eberman@quicinc.com> Reviewed-by:
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Kathiravan T authored
Document the compatible for IPQ5332 SCM. Acked-by:
Kathiravan T <quic_kathirav@quicinc.com> Signed-off-by:
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Poovendhan Selvaraj authored
Add the scm compatible string for IPQ9574 SoC Acked-by:
Poovendhan Selvaraj <quic_poovendh@quicinc.com> Signed-off-by:
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Konrad Dybcio authored
It goes without saying that socname_rpmpds[] is the array of the RPM power domains associated with socname. Remove these comments. Signed-off-by:
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Konrad Dybcio authored
The GPU core clock requires that both VDDGX and VDDMX domains are scaled at the same rate at the same time (well, MX just before GX but you get the idea). Set MX as parent of GX to take care of that. Suggested-by:
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Konrad Dybcio authored
In some cases (like with the GPU core clock on GMU-less SoCs) it's required that we scale more than one voltage domain. This can be achieved by linking them in a parent-child relationship. Add support for specifying a parent PD, similarly to what has been done in the RPMhPD driver. Signed-off-by:
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Konrad Dybcio authored
Currently the whitespace between [DT_BINDING] = &struct is all over the place.. some SoC structs have a space, others have a tab, others have N tabs.. Make that a single tab for everybody to keep things coherent. Signed-off-by:
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Konrad Dybcio authored
Now that we aren't bound by the preprocessor macros, improve the naming to be a bit less preprocessor-y and touch up some rpmpd.pd.name fields while at it. Signed-off-by:
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Konrad Dybcio authored
Expand the struct definition macros to make things easier to see and maintain. Now that the macros are unnecessary, remove them. Signed-off-by:
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Konrad Dybcio authored
It's rather obvious by the characteristic of these resources that they correspond to some voltage lines governed by RPM. Remove the "vdd" unnecessary prefix from them. Signed-off-by:
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Konrad Dybcio authored
Up until now, we had 2 separate entries for VDD_LPI[CM]X and VDD_LPI_[CM]X which both pointed to the same RPM resource. Fix it. Signed-off-by:
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Konrad Dybcio authored
Keep all definitions in one place in preparation for a cleanup to make things tidier. Signed-off-by:
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Konrad Dybcio authored
Replace the SoC names with type+id_key (or type+id+..name..+key for fixed-key definitions) and remove duplicate entries. Signed-off-by:
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David Wronek authored
Add Soc ID table entries for Qualcomm SM7150. Signed-off-by:
David Wronek <davidwronek@gmail.com> Signed-off-by:
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David Wronek authored
Add the ID for the Qualcomm SM7150 SoC. Signed-off-by:
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Bhupesh Sharma authored
Add the ID for QRB4210 variant. Signed-off-by:
Bhupesh Sharma <bhupesh.sharma@linaro.org> Signed-off-by:
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Bhupesh Sharma authored
Add the ID for QRB4210 variant. Signed-off-by:
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Varadarajan Narayanan authored
Add SOC ID for Qualcomm IPQ9574, IPQ9570, IPQ9554, IPQ9550, IPQ9514 and IPQ9510 Signed-off-by:
Varadarajan Narayanan <quic_varada@quicinc.com> Reviewed-by:
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Varadarajan Narayanan authored
Add SOC ID for Qualcomm IPQ9574, IPQ9570, IPQ9554, IPQ9550, IPQ9514 and IPQ9510 Signed-off-by:
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Manivannan Sadhasivam authored
The platforms based on SDM845 SoC locks the access to EDAC registers in the bootloader. So probing the EDAC driver will result in a crash. Hence, disable the creation of EDAC platform device on all SDM845 devices. The issue has been observed on Lenovo Yoga C630 and DB845c. While at it, also sort the members of `struct qcom_llcc_config` to avoid any holes in-between. Cc: <stable@vger.kernel.org> # 5.10 Reported-by:
Steev Klimaszewski <steev@kali.org> Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by:
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Manivannan Sadhasivam authored
Not all Qcom platforms support IRQ mode for ECC handling. For those platforms, the current EDAC driver will not be probed due to missing ECC IRQ in devicetree. So add support for polling mode so that the EDAC driver can be used on all Qcom platforms supporting LLCC. The polling delay of 5000ms is chosen based on Qcom downstream/vendor driver. Reported-by:
Luca Weiss <luca.weiss@fairphone.com> Tested-by:
Borislav Petkov (AMD) <bp@alien8.de> Signed-off-by:
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Manivannan Sadhasivam authored
The Qualcomm LLCC/EDAC drivers were using a fixed register stride for accessing the (Control and Status Registers) CSRs of each LLCC bank. This stride only works for some SoCs like SDM845 for which driver support was initially added. But the later SoCs use different register stride that vary between the banks with holes in-between. So it is not possible to use a single register stride for accessing the CSRs of each bank. By doing so could result in a crash. For fixing this issue, let's obtain the base address of each LLCC bank from devicetree and get rid of the fixed stride. This also means, there is no need to rely on reg-names property and the base addresses can be obtained using the index. First index is LLCC bank 0 and last index is LLCC broadcast. If the SoC supports more than one bank, then those need to be defined in devicetree for index from 1..N-1. Reported-by:
Parikshit Pareek <quic_ppareek@quicinc.com> Tested-by:
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Manivannan Sadhasivam authored
Register regions of the LLCC banks are located at different addresses. Currently, the binding just lists the LLCC0 base address and tries to cover all the banks using a single size. This is entirely wrong as there are other register regions that happen to lie inside the size covered by the binding such as the memory controller and holes. So this needs to be fixed by specifying the base address of individual LLCC banks. This approach will break the existing users of this binding as the register regions are split and the drivers now cannot use LLCC0 register region for accessing rest of the banks (which is wrong anyway). But considering the fact that the binding was wrong from the day one and also the device drivers going wrong by the binding, this breakage is acceptable. Reported-by:
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