- 08 Apr, 2015 6 commits
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git://git.pengutronix.de/git/pza/linuxDave Airlie authored
imx-drm limit fixes Fix IPU IC downscaler to its hardware limitation of 4:1 and the IPU DI pixel clock divider integer part to 8-bit. * tag 'imx-drm-fixes-2015-03-31' of git://git.pengutronix.de/git/pza/linux: gpu: ipu-v3: turns out the IPU can only downsize 4:1 gpu: ipu-v3: limit pixel clock divider to 8-bits drm/radeon: programm the VCE fw BAR as well drm/radeon: always dump the ring content if it's available radeon: Do not directly dereference pointers to BIOS area. drm/radeon/dpm: fix 120hz handling harder
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git://people.freedesktop.org/~robclark/linuxDave Airlie authored
1) support for "stolen mem" for splash-screen take-over 2) additional hdmi pixel clks 3) various pipe flush related fixes 4) support for snapdragon 410 (8x16) 5) support for DSI and dual-DSI It includes one small patch to export tile-group functions (which was ack'd by you), as these are used to explain to userspace dual-dsi configurations (with left and right tile). * 'msm-next' of git://people.freedesktop.org/~robclark/linux: (24 commits) drm/msm/mdp5: Enable DSI connector in msm drm driver drm/msm: Initial add DSI connector support drm/msm: Add split display interface drm/msm/mdp5: Move *_modeset_init out of construct_encoder function drm: export tile-group functions drm/msm/mdp5: Remove CTL flush dummy bits drm/msm/mdp5: Update headers (add CTL flush bits) drm/msm/mdp5: Add hardware configuration for msm8x16 drm/msm/mdp5: Get SMP client list from mdp5_cfg drm/msm/mdp5: Update headers (remove enum mdp5_client_id) drm/msm/mdp5: Separate MDP5 domain from MDSS domain drm/msm/mdp5: Update headers (introduce MDP5 domain) drm/msm/dsi: Update generated DSI header file drm/msm/mdp5: Fix PIPE source image size settings drm/msm/mdp5: Update generated mdp5 header file with DSI support drm/msm/mdp5: Add pingpong entry to mdp5 config table drm/msm/mdp5: Make the intf connection in config module drm/msm/mdp5: Add START signal to kick off certain pipelines drm/msm/mdp5: Enhance operation mode for pipeline configuration drm/msm/mdp5: Update generated header files ...
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git://anongit.freedesktop.org/tegra/linuxDave Airlie authored
drm/panel: Changes for v4.1-rc1 This set of changes adds support for a whole bunch of new panels, mostly simple ones. There's now also support for panels to provide display timings rather than fixed modes, which should allow panels to work with a larger number of display drivers. Eventually drivers should migrate to this new interface and the fixed modes removed from panels. There are also a couple of sparse fixes for the PS8622 and PS8625 bridge drivers. * tag 'drm/panel/for-4.1-rc1' of git://anongit.freedesktop.org/tegra/linux: drm/panel: Add support for Ampire AM-800480R3TMQW-A1H 800x480 7" panel of: Add vendor prefix for Ampire Co., Ltd. drm/panel: Add display timing for HannStar HSD070PWW1 drm/panel: simple: Add display timing support drm/panel: Add display timing support drm/panel: Add support for OrtusTech COM43H4M85ULC panel of: Add vendor prefix for Ortus Technology Co., Ltd. drm/panel: Add bus format for Giantplus GPG482739QS5 panel drm/panel: simple: Add support for AUO b101ean01 panel drm/panel: simple: Add support for Innolux ZJ070NA-01P drm/panel: simple: Add support for Innolux AT043TN24 drm/panel: simple: Add support for Shelly SCA07010-BFN-LNN drm/panel: simple: Add support for Samsung LTN140AT29 panel drm: Remove unused DRM_MODE_OBJECT_BRIDGE drm/bridge: ptn3460: Fix sparse warnings drm/bridge: ps8622: Fix sparse warnings drm/bridge: Add I2C based driver for ps8622/ps8625 bridge
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git://anongit.freedesktop.org/tegra/linuxDave Airlie authored
drm/tegra: Changes for v4.1-rc1 Perhaps the most noteworthy change in this set is the implementation of a hardware VBLANK counter using host1x syncpoints. The SOR registers can now be dumped via debugfs, which can be useful while debugging. The IOVA address space maintained by the driver can also be dumped via debugfs. Other than than, these changes are mostly cleanup work, such as making register names more consistent or removing unused code (that was left over after the atomic mode-setting conversion). There's also a fix for eDP that makes the driver cope with firmware that already initialized the display (such as the firmware on the Tegra-based Chromebooks). * tag 'drm/tegra/for-4.1-rc1' of git://anongit.freedesktop.org/tegra/linux: drm/tegra: sor: Reset during initialization drm/tegra: gem: Return 64-bit offset for mmap(2) drm/tegra: hdmi: Name register fields consistently drm/tegra: hdmi: Resets are synchronous drm/tegra: dc: Document tegra_dc_state_setup_clock() drm/tegra: dc: Remove unused callbacks drm/tegra: dc: Remove unused function drm/tegra: dc: Use base atomic state helpers drm/atomic: Add helpers for state-subclassing drivers drm/tegra: dc: Implement hardware VBLANK counter gpu: host1x: Export host1x_syncpt_read() drm/tegra: sor: Dump registers via debugfs drm/tegra: sor: Registers are 32-bit drm/tegra: Provide debugfs file for the IOVA space drm/tegra: dc: Check for valid parent clock
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git://git.kernel.org/pub/scm/linux/kernel/git/tomba/linuxDave Airlie authored
omapdrm changes for 4.1 * universal plane support * refactoring to prepare work atomic modesetting work * a lot of small fixes * tag 'omapdrm-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/tomba/linux: (36 commits) drm/omap: tiler: add hibernation callback drm/omap: add hibernation callbacks drm/omap: keep ref to old_fb drm/omap: fix race conditon in DMM drm/omap: fix race condition with dev->obj_list drm/omap: do not use BUG_ON(!spin_is_locked(x)) drm/omap: only ignore DIGIT SYNC LOST for TV output drm/omap: fix race with error_irq drm/omap: use DRM_ERROR_RATELIMITED() for error irqs drm/omap: stop connector polling during suspend drm/omap: remove dummy PM functions drm/omap: tiler: fix race condition with engine->async drm/omap: fix plane's channel selection drm/omap: fix TILER on OMAP5 drm/omap: handle incompatible buffer stride and pixel size drm/omap: fix error handling in omap_framebuffer_create() drm/omap: fix operation without fbdev drm/omap: add a comment why locking is missing drm/omap: add pin refcounting to omap_framebuffer drm/omap: clear omap_obj->paddr in omap_gem_put_paddr() ...
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git://github.com/markyzq/kernel-drm-rockchipDave Airlie authored
These are based on drm-next branch, fix some drm/rockchip problem. Please pull them. * 'drm-next0401' of git://github.com/markyzq/kernel-drm-rockchip: drm/rockchip: vop: add vop power domain support drm: rockchip: Turn off VT switching on suspend drm/rockchip: register all connectors after bind drm/rockchip: fix clk enable disable mismatch in vop_crtc_mode_set
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- 03 Apr, 2015 4 commits
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Mark Yao authored
Reference the power domain incase vop power down when in use. Signed-off-by: Mark Yao <yzq@rock-chips.com>
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Caesar Wang authored
drm/rockchip already has support for disabling all displays on suspend and enabling them on resume. Disable automatic VT switching on suspend by the pm console tracking layer. Tested on veyron, used `echo mem > sys/power/state` => verified no VT switch Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
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Daniel Kurtz authored
Register connectors with userspace after all components are bound. Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-by: Dominik Behr <dbehr@chromium.org> drm_connector_get_name -> connector->name This patch is necessary to make X11 see screens it seems. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Heiko Stuebner authored
The function disables the dclk at the beginning, so don't simply return when an error happens, but instead enable the clock again, so that enable and disable calls are balanced. ret_clk is introduced to hold the clk_enable result and not mangle the original error code. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
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- 02 Apr, 2015 28 commits
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Philipp Zabel authored
This adds support for the AM-800480R3TMQW-A1H 7" 800x480 panel to the DRM simple panel driver. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Philipp Zabel authored
Add Ampire Co., Ltd. to the list of device tree vendor prefixes. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Philipp Zabel authored
The HannStar HSD070PWW1 LVDS panel data sheet lists allowed ranges additionally to the typical values for pixel clock rate (64.3-82 MHz) and blanking intervals (54-681 clock cycles horizontally, 3-23 lines vertically). This patch replaces this panel's display mode with the display timing information to describe acceptable timings. Since the HSYNC and VSYNC are unused, the distribution between front porches, back porches, and sync pulse lengths was chosen at will. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Philipp Zabel authored
The simple panel driver's ->get_modes() implementation calculates the display mode list from the typical timings and the ->get_timings() implementation returns the timings to the connected encoder for mode validation and fixup. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> [treding@nvidia.com: select VIDEOMODE_HELPERS] Signed-off-by: Thierry Reding <treding@nvidia.com>
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Philipp Zabel authored
Many panel data sheets, additionally to typical values, list allowed ranges for timings such as hsync/vsync lengths, porches, and the pixel clock rate. These can be stored in a struct display_timing, to be used by an encoder mode_fixup callback to clamp user provided timing values or to validate workarounds for clock source limitations. This patch adds a new drm_panel_funcs callback that returns the panel's available display_timing entries. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Philipp Zabel authored
This adds support for the COM43H4M85ULC 3.7" 800x480 panel to the DRM simple panel driver. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Philipp Zabel authored
Add Ortus Technology Co., Ltd. to the list of device tree vendor prefixes. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Philipp Zabel authored
This patch adds the bus_format field to the GPG482739QS5 panel structure. Signed-off-by: Philipp Zabel <philipp.zabel@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Huang Lin authored
The AUO b101ean01 panel is a 10.1" 1280x800 panel which can be supported by the simple panel driver. Signed-off-by: Huang Lin <hl@rock-chips.com> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Michael Grzeschik authored
The Innolux ZJ070NA-01P is a 7.0" TFT LCD panel with an integrated LED backlight unit. This panel is used on the Technexion Toucan. Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Nicolas Ferre authored
The Innolux AT043TN24 4.3" WQVGA TFT LCD panel. This panel with backlight is found in PDA 4.3" LCD screen (TM43xx series for instance). Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Boris BREZILLON authored
The Shelly SCA07010-BFN-LNN is a 7.0" WVGA TFT LCD panel. This panel with backlight is found in PDA 7" LCD screen (TM70xx series for instance). Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Stéphane Marchesin authored
This panel is used by the Nyan Blaze board and can be supported by the simple-panel driver. Signed-off-by: Stéphane Marchesin <marcheu@chromium.org> [tomeu.vizoso@collabora.com: add device tree binding document] Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Acked-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Tomeu Vizoso authored
As there isn't a way for the firmware on the Nyan Chromebooks to hand over the display to the kernel, and the kernel isn't redoing the whole configuration at present. With this patch, the SOR is brought to a known state and we get correct display on every boot. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Sean Paul authored
On 64-bit targets, tegra_gem_mmap() only returns a partial offset to userspace. As such, subsequent calls to mmap(2) may fail. Change the arguments to use a 64-bit offset to fix this. Signed-off-by: Sean Paul <seanpaul@chromium.org> Acked-by: Erik Faye-Lund <kusmabite@gmail.com> [treding@nvidia.com: tweak commit message] Signed-off-by: Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
Name the fields of the SOR_SEQ_CTL register consistently. Signed-off-by: Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
Resets on Tegra are synchronous, so keep the clock enabled while asserting the reset. Signed-off-by: Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
This function is called by output drivers so should be documented. While at it, move it to a more appropriate location. Signed-off-by: Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
The ->mode_set() and ->mode_set_base() callbacks are no longer used with full atomic mode-setting drivers, so remove them. Signed-off-by: Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
The tegra_dc_setup_clock() function is unused after the conversion to atomic mode-setting, so remove it. Signed-off-by: Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
Instead of duplicating the code, make use of the newly introduced atomic state duplicate and destroy helpers. This allows changes to the base atomic state handling to automatically propagate to the Tegra driver and thereby prevent breakage resulting from both copies going out of sync. Signed-off-by: Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
Drivers that subclass CRTC, plane or connector state need to carefully duplicate the code that the atomic helpers have. This is bound to cause breakage eventually because it requires auditing all drivers and update them when code is added to the helpers. In order to avoid that, implement new helpers that perform the required steps when copying and destroying state. These new helpers are exported so that state-subclassing drivers can use them. The default helpers are implemented using them as well, providing a single location that needs to be changed when adding to base atomic states. Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
The display controller on Tegra can use syncpoints to count VBLANK events. syncpoints are 32-bit unsigned integers, so well suited as VBLANK counters. Signed-off-by: Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
This function is used to read the current value of the syncpt and is useful in situations where drivers don't schedule work and wait for the syncpoint to increment. One particular use-case is using the syncpoint as a VBLANK counter. Signed-off-by: Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
Use a sized unsigned 32-bit data type (u32) to store register contents. The SOR registers are 32 bits wide irrespective of the architecture's data width. Signed-off-by: Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
The Tegra DRM driver uses a single IO virtual address space for buffer mappings. Provide a table of the address space usage in debugfs. Signed-off-by: Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
Check that the desired parent clock is indeed a valid parent for the display controller clock. This is purely cosmetic at this point since the parent clocks are specified in DT and all the currently defined parents are in fact valid parents of the display controller clock. Signed-off-by: Thierry Reding <treding@nvidia.com>
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- 01 Apr, 2015 2 commits
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Hai Li authored
This change adds the support in mdp5 kms driver for single and dual DSI. Dual DSI case depends on the framework API and sequence change to support dual data path. v1: Initial change v2: Address Rob Clark's comment - Separate command mode encoder to a new file mdp5_cmd_encoder.c - Rebase to not depend on msm_drm_sub_dev change Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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Hai Li authored
This change adds the DSI connector support in msm drm driver. v1: Initial change v2: - Address comments from Archit + minor clean-ups - Rebase to not depend on msm_drm_sub_dev change [Rob's comment] v3: Fix issues when initialization is failed Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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