- 18 Sep, 2019 4 commits
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Peng Fan authored
pll BYPASS bit should be kept inside pll driver for glitchless freq setting following spec. If exposing the bit, that means pll driver and clk driver has two paths to touch this bit, which is wrong. So use EXT_BYPASS bit here. And drop uneeded set parent, because EXT_BYPASS default is 0. Suggested-by:
Jacky Bai <ping.bai@nxp.com> Reviewed-by:
Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by:
Peng Fan <peng.fan@nxp.com> Link: https://lkml.kernel.org/r/1568043491-20680-5-git-send-email-peng.fan@nxp.comSigned-off-by:
Stephen Boyd <sboyd@kernel.org>
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Peng Fan authored
pll BYPASS bit should be kept inside pll driver for glitchless freq setting following spec. If exposing the bit, that means pll driver and clk driver has two paths to touch this bit, which is wrong. So use EXT_BYPASS bit here. And drop uneeded set parent, because EXT_BYPASS default is 0. Fixes: ba5625c3 ("clk: imx: Add clock driver support for imx8mm") Suggested-by:
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Peng Fan authored
When registering the PLL, unbypass the PLL. The PLL has two bypass control bit, BYPASS and EXT_BYPASS. we will expose EXT_BYPASS to clk driver for mux usage, and keep BYPASS inside pll14xx usage. The PLL has a restriction that when M/P change, need to RESET/BYPASS pll to avoid glitch, so we could not expose BYPASS. To make it easy for clk driver usage, unbypass PLL which does not hurt current function. Fixes: 8646d4dc ("clk: imx: Add PLLs driver for imx8mm soc") Reviewed-by:
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Peng Fan authored
According to PLL1443XA and PLL1416X spec, "When BYPASS is 0 and RESETB is changed from 0 to 1, FOUT starts to output unstable clock until lock time passes. PLL1416X/PLL1443XA may generate a glitch at FOUT." So set BYPASS when RESETB is changed from 0 to 1 to avoid glitch. In the end of set rate, BYPASS will be cleared. When prepare clock, also need to take care to avoid glitch. So we also follow Spec to set BYPASS before RESETB changed from 0 to 1. And add a check if the RESETB is already 0, directly return 0; Fixes: 8646d4dc ("clk: imx: Add PLLs driver for imx8mm soc") Reviewed-by:
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- 04 Sep, 2019 1 commit
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Stephen Boyd authored
Merge tag 'clk-imx-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-imx Pull i.MX clock changes from Shawn Guo: - Add clock driver for i.MX8MN SoC - Switch i.MX8MM clock driver to platform driver - Add API for clk unregister when driver probe fail - Add Hifi4 DSP related clocks for i.MX8QXP SoC - Fix Audio PLL setting and parent clock for USB - Misc i.MX8 clock driver improvements and corrections * tag 'clk-imx-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (28 commits) clk: imx: imx8mn: fix audio pll setting clk: imx8mn: Add necessary frequency support for ARM PLL table clk: imx8mn: Add missing rate_count assignment for each PLL structure clk: imx8mn: fix int pll clk gate clk: imx8mn: Add GIC clock clk: imx8mn: Fix incorrect parents clk: imx8mm: Fix incorrect parents clk: imx8mq: Fix sys3 pll references clk: imx8mq: Unregister clks when of_clk_add_provider failed clk: imx8mm: Unregister clks when of_clk_add_provider failed clk: imx8mq: Mark AHB clock as critical clk: imx8mn: Keep uart clocks on for early console clk: imx: Remove unused function statement clk: imx7ulp: Make sure earlycon's clock is enabled clk: imx8mm: Switch to platform driver clk: imx: imx8mm: fix audio pll setting clk: imx8mm: GPT1 clock mux option #5 should be sys_pll1_80m clk: imx8mm: Fix typo of pwm3 clock's mux option #4 clk: imx: Remove unused clk based API clk: imx8mq: set correct parent for usb ctrl clocks ...
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- 24 Aug, 2019 1 commit
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Peng Fan authored
The AUDIO PLL max support 650M, so the original clk settings violate spec. This patch makes the output 786432000 -> 393216000, and 722534400 -> 361267200 to aligned with NXP vendor kernel without any impact on audio functionality and go within 650MHz PLL limit. Signed-off-by:
Shengjiu Wang <shengjiu.wang@nxp.com> Signed-off-by:
Shawn Guo <shawnguo@kernel.org>
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- 19 Aug, 2019 7 commits
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Anson Huang authored
i.MX8MN supports CPU running at 1.5GHz/1.4GHz/1.2GHz, add missing frequency for ARM PLL table. Signed-off-by:
Anson Huang <Anson.Huang@nxp.com> Signed-off-by:
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Anson Huang authored
Add .rate_count assignment which is necessary for searching required PLL rate from the each PLL table. Signed-off-by:
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Peng Fan authored
To Frac pll, the gate shift is 13, however to Int PLL the gate shift is 11. Signed-off-by:
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Leonard Crestez authored
This is enabled by default but if it's not explicitly defined and marked as critical then its parent might get turned off. Signed-off-by:
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Leonard Crestez authored
* Replace to audio_pll2_clk with audio_pll2_out * Replace sys3_pll2_out with sys_pll3_out * Replace sys1_pll_40m with sys_pll1_40m * qspi parent[2] is sys_pll2_333m not sys_pll1_800m Fixes: 96d6392b ("clk: imx: Add support for i.MX8MN clock driver") Signed-off-by:
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Leonard Crestez authored
* There is no video_pll2 on imx8mm, replace with dummy * Replace reference to sys_pll3_clk with sys_pll3_out * qspi parent[2] is sys_pll2_333m not sys_pll1_800m Fixes: ba5625c3 ("clk: imx: Add clock driver support for imx8mm") Signed-off-by:
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Leonard Crestez authored
The "sys3_pll2_out" CLK was removed in refactoring so all references need to be updated to "sys3_pll_out" Fixes: e9dda4af ("clk: imx: Refactor entire sccg pll clk") Signed-off-by:
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- 12 Aug, 2019 2 commits
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Anson Huang authored
When of_clk_add_provider failed, all clks should be unregistered. Signed-off-by:
Daniel Baluta <daniel.baluta@nxp.com> Signed-off-by:
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Anson Huang authored
When of_clk_add_provider failed, all clks should be unregistered. Signed-off-by:
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- 03 Aug, 2019 18 commits
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Abel Vesa authored
Initially, the TMU_ROOT clock was marked as critical, which automatically made the AHB clock to stay always on. Since the TMU_ROOT clock is not marked as critical anymore, following commit: "clk: imx8mq: Remove CLK_IS_CRITICAL flag for IMX8MQ_CLK_TMU_ROOT" all the clocks that derive from ipg_root clock (and implicitly ahb clock) would also have to enable, along with their own gate, the AHB clock. But considering that AHB is actually a bus that has to be always on, we mark it as critical in the clock provider driver and then all the clocks that derive from it can be controlled through the dedicated per IP gate which follows after the ipg_root clock. Signed-off-by:
Abel Vesa <abel.vesa@nxp.com> Tested-by:
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Anson Huang authored
Call imx_register_uart_clocks() API to keep uart clocks enabled when earlyprintk or earlycon is active. Signed-off-by:
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Anson Huang authored
imx_register_uart_clocks_hws() function is NOT implemented at all, remove it. Signed-off-by:
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Reviewed-by:
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Anson Huang authored
Earlycon's clock could be disabled during kernel boot up, if earlycon is enabled and its clock is gated, then kernel boot up will fail. Make sure earlycon's clock is enabled during kernel boot up. Signed-off-by:
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Abel Vesa authored
There is no strong reason for this to use CLK_OF_DECLARE instead of being a platform driver. Plus, this will now be aligned with the other i.MX8M clock drivers which are platform drivers. In order to make the clock provider a platform driver all the data and code needs to be outside of .init section. Signed-off-by:
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Peng Fan authored
The AUDIO PLL max support 650M, so the original clk settings violate spec. This patch makes the output 786432000 -> 393216000, and 722534400 -> 361267200 to aligned with NXP vendor kernel without any impact on audio functionality and go within 650MHz PLL limit. Cc: <stable@vger.kernel.org> Fixes: ba5625c3 ("clk: imx: Add clock driver support for imx8mm") Signed-off-by:
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Anson Huang authored
i.MX8MM's GPT1 clock mux option #5 should be sys_pll1_80m, NOT sys_pll1_800m, correct it. Fixes: ba5625c3 ("clk: imx: Add clock driver support for imx8mm") Signed-off-by:
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Anson Huang authored
i.MX8MM has no sys3_pll2_out clock, PWM3 clock's mux option #4 should be sys_pll3_out, sys3_pll2_out is a typo, fix it. Fixes: ba5625c3 ("clk: imx: Add clock driver support for imx8mm") Signed-off-by:
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Abel Vesa authored
Now that the i.MX6 and i.MX7 clock drivers have been switched to clk_hw based, we can remove the clk based API that is not used by any i.MX clock driver. The following APIs are going away now: - imx_clk_busy_divider - imx_clk_busy_mux - imx_clk_fixup_divider - imx_clk_fixup_mux - imx_clk_mux_ldb - imx_clk_gate_dis_flags - imx_clk_gate_flags Signed-off-by:
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Li Jun authored
Per latest imx8mq datasheet of CCM, the parent of usb1_ctrl_root_clk and usb2_ctrl_root_clk is usb_bus. Signed-off-by:
Li Jun <jun.li@nxp.com> Reviewed-by:
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Anson Huang authored
IMX8MQ_CLK_TMU_ROOT is ONLY used for thermal module, the driver should manage this clock, so no need to have CLK_IS_CRITICAL flag set. Signed-off-by:
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Fancy Fang authored
Rename 'share_count_dcss' to 'share_count_disp', since the DCSS module does not exist on imx8mm platform. So rename it to avoid any unnecessary confusion. Signed-off-by:
Fancy Fang <chen.fang@nxp.com> Signed-off-by:
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Li Jun authored
Per latest imx8mm datasheet of CCM, the parent of usb1_ctrl_root_clk should be usb_bus. Signed-off-by:
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Daniel Baluta authored
i.MX8QXP contains Hifi4 DSP. There are four clocks associated with DSP: * dsp_lpcg_core_clk * dsp_lpcg_ipg_clk * dsp_lpcg_adb_aclk * ocram_lpcg_ipg_clk Signed-off-by:
Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by:
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Anson Huang authored
This patch adds i.MX8MN clock driver support. Signed-off-by:
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Anson Huang authored
For i.MX clock drivers probe fail case, clks should be unregistered in the return path, this patch adds a common API for i.MX clock drivers to unregister clocks when fail. Signed-off-by:
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Anson Huang authored
1416X/1443X PLL are used on i.MX8MM and i.MX8MN and maybe other i.MX8M series SoC later, the macro definitions of these PLLs' initialization should be common for usage. Signed-off-by:
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Anson Huang authored
Add the clock binding doc for i.MX8MN. Signed-off-by:
Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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- 21 Jul, 2019 7 commits
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Linus Torvalds authored
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git://git.kernel.org/pub/scm/linux/kernel/git/robh/linuxLinus Torvalds authored
Pull Devicetree fixes from Rob Herring: "Fix several warnings/errors in validation of binding schemas" * tag 'devicetree-fixes-for-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: dt-bindings: pinctrl: stm32: Fix missing 'clocks' property in examples dt-bindings: iio: ad7124: Fix dtc warnings in example dt-bindings: iio: avia-hx711: Fix avdd-supply typo in example dt-bindings: pinctrl: aspeed: Fix AST2500 example errors dt-bindings: pinctrl: aspeed: Fix 'compatible' schema errors dt-bindings: riscv: Limit cpus schema to only check RiscV 'cpu' nodes dt-bindings: Ensure child nodes are of type 'object'
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git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfsLinus Torvalds authored
Pull vfs documentation typo fix from Al Viro. * 'work.misc' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs: typo fix: it's d_make_root, not d_make_inode...
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git://git.samba.org/sfrench/cifs-2.6Linus Torvalds authored
Pull cifs fixes from Steve French: "Two fixes for stable, one that had dependency on earlier patch in this merge window and can now go in, and a perf improvement in SMB3 open" * tag '5.3-smb3-fixes' of git://git.samba.org/sfrench/cifs-2.6: cifs: update internal module number cifs: flush before set-info if we have writeable handles smb3: optimize open to not send query file internal info cifs: copy_file_range needs to strip setuid bits and update timestamps CIFS: fix deadlock in cached root handling
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Qian Cai authored
The commit b3aa14f0 ("iommu: remove the mapping_error dma_map_ops method") incorrectly changed the checking from dma_ops_alloc_iova() in map_sg() causes a crash under memory pressure as dma_ops_alloc_iova() never return DMA_MAPPING_ERROR on failure but 0, so the error handling is all wrong. kernel BUG at drivers/iommu/iova.c:801! Workqueue: kblockd blk_mq_run_work_fn RIP: 0010:iova_magazine_free_pfns+0x7d/0xc0 Call Trace: free_cpu_cached_iovas+0xbd/0x150 alloc_iova_fast+0x8c/0xba dma_ops_alloc_iova.isra.6+0x65/0xa0 map_sg+0x8c/0x2a0 scsi_dma_map+0xc6/0x160 pqi_aio_submit_io+0x1f6/0x440 [smartpqi] pqi_scsi_queue_command+0x90c/0xdd0 [smartpqi] scsi_queue_rq+0x79c/0x1200 blk_mq_dispatch_rq_list+0x4dc/0xb70 blk_mq_sched_dispatch_requests+0x249/0x310 __blk_mq_run_hw_queue+0x128/0x200 blk_mq_run_work_fn+0x27/0x30 process_one_work+0x522/0xa10 worker_thread+0x63/0x5b0 kthread+0x1d2/0x1f0 ret_from_fork+0x22/0x40 Fixes: b3aa14f0 ("iommu: remove the mapping_error dma_map_ops method") Signed-off-by:
Qian Cai <cai@lca.pw> Reviewed-by:
Christoph Hellwig <hch@lst.de> Signed-off-by:
Linus Torvalds <torvalds@linux-foundation.org>
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Mike Rapoport authored
The hexagon implementation pte_alloc_one(), pte_alloc_one_kernel(), pte_free_kernel() and pte_free() is identical to the generic except of lack of __GFP_ACCOUNT for the user PTEs allocation. Switch hexagon to use generic version of these functions. Signed-off-by:
Mike Rapoport <rppt@linux.ibm.com> Signed-off-by:
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git://github.com/jonmason/ntbLinus Torvalds authored
Pull NTB updates from Jon Mason: "New feature to add support for NTB virtual MSI interrupts, the ability to test and use this feature in the NTB transport layer. Also, bug fixes for the AMD and Switchtec drivers, as well as some general patches" * tag 'ntb-5.3' of git://github.com/jonmason/ntb: (22 commits) NTB: Describe the ntb_msi_test client in the documentation. NTB: Add MSI interrupt support to ntb_transport NTB: Add ntb_msi_test support to ntb_test NTB: Introduce NTB MSI Test Client NTB: Introduce MSI library NTB: Rename ntb.c to support multiple source files in the module NTB: Introduce functions to calculate multi-port resource index NTB: Introduce helper functions to calculate logical port number PCI/switchtec: Add module parameter to request more interrupts PCI/MSI: Support allocating virtual MSI interrupts ntb_hw_switchtec: Fix setup MW with failure bug ntb_hw_switchtec: Skip unnecessary re-setup of shared memory window for crosslink case ntb_hw_switchtec: Remove redundant steps of switchtec_ntb_reinit_peer() function NTB: correct ntb_dev_ops and ntb_dev comment typos NTB: amd: Silence shift wrapping warning in amd_ntb_db_vector_mask() ntb_hw_switchtec: potential shift wrapping bug in switchtec_ntb_init_sndev() NTB: ntb_transport: Ensure qp->tx_mw_dma_addr is initaliazed NTB: ntb_hw_amd: set peer limit register NTB: ntb_perf: Clear stale values in doorbell and command SPAD register NTB: ntb_perf: Disable NTB link after clearing peer XLAT registers ...
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