- 07 Nov, 2023 36 commits
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Tao Zhou authored
The UE registe list is larger than CE list. Reported-by: yipeng.chai@amd.com Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
Stanley.Yang <Stanley.Yang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Tim Huang authored
For IMU enabled APUs, after sending the PrepareMp1ForUnload message to SMU in system_features_control, the RLC registers can't be touched. The driver to stop the rlc in suspending is no longer required. Signed-off-by:
Tim Huang <Tim.Huang@amd.com> Reviewed-by:
Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by:
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Bragatheswaran Manickavel authored
The member variable enable_hpo_pg_support is already initialized and hence the reinitialization instruction can be removed. Issue identified using the doubleinit.cocci Coccinelle semantic patch script. Signed-off-by:
Bragatheswaran Manickavel <bragathemanick0908@gmail.com> Signed-off-by:
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Lijo Lazar authored
Change return code to EOPNOTSUPP for unsupported functions. Use the error code information to hide sysfs nodes not valid for the SOC. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Yang Wang <kevinyang.wang@amd.com> Reviewed-by:
Asad Kamal <asad.kamal@amd.com> Signed-off-by:
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Lijo Lazar authored
Doorbell rptr/wptr can be set through multiple ways including direct register initialization. Disable doorbell during hw_fini once the ring is disabled so that during next module reload direct initialization takes effect. Also, move the direct initialization after minor update is set to 1 since rptr/wptr are reinitialized back to 0 which could be lower than the previous doorbell value (ex: cases like module reload). Signed-off-by:
Le Ma <le.ma@amd.com> Reviewed-by:
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Jiadong Zhu authored
Set the default reset method to mode2 for SMU IP v14.0.0 Signed-off-by:
Jiadong Zhu <Jiadong.Zhu@amd.com> Reviewed-by:
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George Shen authored
[Why] A recent refactor of DC's DP test pattern automation code requires the DC stream's test pattern and test pattern color space fields to be correctly populated before calling dc_link_dp_set_test_pattern. [How] Populate stream's test pattern type and color space fields before calling into DC to program DP test pattern. Reviewed-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by:
Hersen Wu <hersenxs.wu@amd.com> Signed-off-by:
George Shen <george.shen@amd.com> Signed-off-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Sung Joon Kim authored
[why] DML2 does not handle the case when we have a single stream sourcing 2 or more planes that are duplicates of one another. To properly handle this scenario, pipe index to plane index mapping is used to decide which plane is being processed and programmed. [how] Create static array of pipe index to plane index map. Populate the array properly and use in appropriate places. Reviewed-by:
Xi (Alex) Liu <xi.liu@amd.com> Acked-by:
Sung Joon Kim <sungkim@amd.com> Signed-off-by:
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Alvin Lee authored
[Description] - Similar to FPO, SubVP should also force cursor P-State allow instead of relying on natural assertion - Implement code path to force and unforce cursor P-State allow for SubVP Reviewed-by:
Samson Tam <samson.tam@amd.com> Acked-by:
Alvin Lee <alvin.lee2@amd.com> Tested-by:
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Daniel Miess authored
[Why] Enable the last of the RCO options for dcn35 [How] Breakout RCO from dccg35_set_physymclk so that physymclk RCO can be set in dccg_init without disabling physymclk Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by:
Jun Lei <jun.lei@amd.com> Acked-by:
Daniel Miess <daniel.miess@amd.com> Signed-off-by:
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Chaitanya Dhere authored
Clean-up the code to remove references of all unused dml architecture versions since only dml2 is actively used. Reviewed-by:
Chaitanya Dhere <chaitanya.dhere@amd.com> Signed-off-by:
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Aric Cyr authored
Summary: - Enable DCN35 physymclk root clock gating - Fix DP automation test pattern bug - Disable OTG for mode timing switch on DCN35 - Refactor DML2 - Revert Fix handling duplicate planes on one stream - Revert Enable DCN clock gating - Implement cursor P-State allow for SubVP - Optimize pipe otg allocation - Save and restore mall state while switching from ODM to Subvp Acked-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
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Wenjing Liu authored
[why] There is a case when we are switching from ODM combine to Subvp where minimal transition based off subvp state is required. In thise case, we need to save and restore mall state when applying minimal transition. Reviewed-by:
Dillon Varone <dillon.varone@amd.com> Acked-by:
Wenjing Liu <wenjing.liu@amd.com> Tested-by:
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Joshua Aberback authored
[Why] DCN32 uses ABM register definitions in dcn32_resource.h, remove duplicate from dce_abm.h to avoid confusion. Reviewed-by:
Joshua Aberback <joshua.aberback@amd.com> Signed-off-by:
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Rodrigo Siqueira authored
For all the components that participate in DCN architecture, there is a header in the dc/inch/hw. For some reason, OPTC broke this pattern and added all the primary functions/structs associated with that in the dcn10_optc.h file. For consistency's sake, this commit introduces a new optc.h file and extracts the code from dcn10_optc to this new file. Reviewed-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Acked-by:
Rodrigo Siqueira <rodrigo.siqueira@amd.com> Tested-by:
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Ovidiu Bunea authored
[why] Doing a mode timing change causes a hang when OTG is not disabled. [how] Add link_enc null check in disable_otg_wa to cover this case. Reviewed-by:
Ovidiu Bunea <ovidiu.bunea@amd.com> Signed-off-by:
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Dennis Chan authored
[Why] Current Desync IRQ handler will have some potential do not hit the desync error case. We change to check both desync error HPD and DPCD. Signed-off-by:
Dennis Chan <dennis.chan@amd.com> Acked-by:
Robin Chen <robin.chen@amd.com> Tested-by:
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Anthony Koo authored
- Increase number of bits for IPS boot option Reviewed-by:
Anthony Koo <anthony.koo@amd.com> Tested-by:
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Aric Cyr authored
This version brings along following fixes: Update test link rate DPCD bit field to match spec Enable RCO options for dcn35 Add missing dml2 init value for dcn35 Enable DCN clock gating DCN35 Disable cm power optimization Allow 16 max_slices for DP2 DSC Fix OTG disable workaround logic Enable more IPS options Fix FRL assertion on boot Fix missing blendTF programming Update DP HPO MSA with colorimetry from test request Fix handling duplicate planes on one stream Acked-by:
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Roman Li authored
[Why] For lighting up, some dml2 params needs to be initialized. One of them escaped initial patch under: "drm/amd/display: Add DCN35 DML2 support" [How] Add missing initialization. Fixes: 115009d1 ("drm/amd/display: Add DCN35 DML2 support") Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Acked-by:
Roman Li <roman.li@amd.com> Tested-by:
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Taimur Hassan authored
[Why] DENTIST was hanging when performing DISPCLK update with OTG enabled, as OTG disable workaround was not executing. [How] Workaround was checking against current_state before running, but when called from optimize_bandwidth (safe_to_lower), we should be checking against context instead. Reviewed-by:
Taimur Hassan <syed.hassan@amd.com> Tested-by:
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ChunTao Tso authored
[Why] For Replay, if we receive HPD, it doesn’t need to reboot the display. We don’t need to return anything exactly. [How] Return nothing just because we don’t need to reboot the display. Signed-off-by:
ChunTao Tso <chuntao.tso@amd.com> Acked-by:
Jerry Zuo <jerry.zuo@amd.com> Tested-by:
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Dennis Chan authored
[why] It's useful to disable the recovery mechanism when debugging replay desync errors. Signed-off-by:
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Yihan Zhu authored
[WHY & HOW] Enabling SCE after boot up will cause color distortion. Reviewed-by:
Yihan Zhu <yihan.zhu@amd.com> Tested-by:
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George Shen authored
[Why] Some DP link layer tests request a different colorimetry than the default one that is used. Currently, our test automation logic does not update the MSA with the test request value for DP HPO case. [How] Update HPO MSA colorimetry with test automation request value. Reviewed-by:
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George Shen authored
[Why] An SCR was made to the DP2.0 spec that updated the bit field definition for UHBR13.5 in the test link rate DPCD register. [How] Add new translation to match the SCR update. Keep old translation for backwards compatibility. Reviewed-by:
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Fangzhi Zuo authored
Enable 12 and 16 max_slices for DP2 DSC Reviewed-by:
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Sung Joon Kim authored
[why] To help isolate static screen and video playback tests, we want to enable an IPS option to allow IPS only on D3 cycle. [how] Add DISABLE_DYNAMIC and DISABLE_ALL IPS disable flags for user control. Reviewed-by:
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Daniel Miess authored
[Why & How] Enable root clock optimization options for dcn35 for power savings Reviewed-by:
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Sung Joon Kim authored
[why] Make sure to ungate the clocks on boot so programming sequence is done successfully. [how] Move the ungate logic after bios init. Reviewed-by:
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Ilya Bakoulin authored
[Why] When MPO surface pixel format is not ARGB8888, fast update can miss programming blendTF. [How] Set the gamma_change update flag on blend_tf change. Reviewed-by:
Ilya Bakoulin <ilya.bakoulin@amd.com> Tested-by:
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Aric Cyr authored
This version brings along following fixes: On boot disable domain22 force power on decouple dmcub execution to reduce lock granularity Enable fast update on blendTF change Fix blend LUT programming Program plane color setting correctly amend HPD handler for Replay Avoid NULL dereference of timing generator Acked-by:
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JinZe.Xu authored
[Why] On some systems dmub commands run at high IRQ, so long running commands will block other interrupts. [How] Decouple wait_for_idle from dmcub queue/execute/wait. Reviewed-by:
Josip Pavic <josip.pavic@amd.com> Acked-by:
JinZe.Xu <jinze.xu@amd.com> Tested-by:
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Anthony Koo authored
- Minor formatting changes - Update defines to match the bit width of the field it is used for - Add new boot up bits to control HW sub block regions power down Reviewed-by:
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Daniel Miess authored
[Why] HDCP2 enablement fails when domain22 is set to force power on [How] Disable force power on for domain22 on startup Reviewed-by:
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Surbhi Kakarya authored
The purpose of this patch is to disable XNACK or set XNACK OFF mode on SRIOV platform which doesn't support it. This will prevent user-space application to fail or result into unexpected behaviour whenever the application need to run test-case in XNACK ON mode. Signed-off-by:
Surbhi Kakarya <surbhi.kakarya@amd.com> Reviewed-by:
Shaoyun Liu <shaoyun.liu@amd.com> Signed-off-by:
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- 06 Nov, 2023 2 commits
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https://gitlab.freedesktop.org/agd5f/linuxDave Airlie authored
amd-drm-next-6.7-2023-11-03: amdgpu: - Fix RAS support check - RAS fixes - MES fixes - SMU13 fixes - Contiguous memory allocation fix - BACO fixes - GPU reset fixes - Min power limit fixes - GFX11 fixes - USB4/TB hotplug fixes - ARM regression fix - GFX9.4.3 fixes - KASAN/KCSAN stack size check fixes - SR-IOV fixes - SMU14 fixes - PSP13 fixes - Display blend fixes - Flexible array size fixes amdkfd: - GPUVM fix radeon: - Flexible array size fixes Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231103173203.4912-1-alexander.deucher@amd.com
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Dave Airlie authored
Merge tag 'drm-misc-next-fixes-2023-11-02' of git://anongit.freedesktop.org/drm/drm-misc into drm-next drm-misc-next-fixes for v6.7-rc1: - dt binding fix for ssd132x - Initialize ssd130x crtc_state to NULL. Signed-off-by:
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- 03 Nov, 2023 2 commits
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Ilya Bakoulin authored
[Why] Full update is not required on surface blend TF change. [How] Update full_update_required condition. Reviewed-by:
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Ilya Bakoulin authored
[Why] LUT write index does not get reset to zero when writing the LUT values for each separate RGB component, which results in wrong data for 2 of the 3 components. [How] Reset LUT write index to zero before writing each component's data. Reviewed-by:
Krunoslav Kovac <krunoslav.kovac@amd.com> Acked-by:
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