- 11 Aug, 2021 6 commits
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Paul Cercueil authored
The ingenic_set_bias() function's "bias" argument is not a "enum pin_config_param", so its value should not be compared against values of that enum. This should fix the bias config not working on the X2000(E) SoCs. Fixes: 943e0da1 ("pinctrl: Ingenic: Add pinctrl driver for X2000.") Cc: <stable@vger.kernel.org> # v5.12 Signed-off-by:
Paul Cercueil <paul@crapouillou.net> Tested-by: 周琰杰 (Zhou Yanjie)<zhouyanjie@wanyeetech.com> Link: https://lore.kernel.org/r/20210717174836.14776-2-paul@crapouillou.netSigned-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Paul Cercueil authored
Fix the pull up/down info for both the JZ4760 and JZ4770 SoCs, as the previous values sometimes contradicted what's written in the programming manual. Fixes: b5c23aa4 ("pinctrl: add a pinctrl driver for the Ingenic jz47xx SoCs") Cc: <stable@vger.kernel.org> # v4.12 Signed-off-by:
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周琰杰 (Zhou Yanjie) authored
Add support for probing the pinctrl-ingenic driver on the X2100 SoC from Ingenic. Signed-off-by:
周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Link: https://lore.kernel.org/r/1627108604-91304-5-git-send-email-zhouyanjie@wanyeetech.comSigned-off-by:
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周琰杰 (Zhou Yanjie) authored
Add the pinctrl bindings for the X2100 SoC from Ingenic. Signed-off-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/1627108604-91304-4-git-send-email-zhouyanjie@wanyeetech.comSigned-off-by:
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周琰杰 (Zhou Yanjie) authored
Add SSI pins support for the JZ4755 SoC and the JZ4760 SoC from Ingenic. Signed-off-by:
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周琰杰 (Zhou Yanjie) authored
1.Rename the original "dmicx" ABIs to "dmic-ifx", since these devices have only one DMIC module which has multiple input interfaces. The original naming is easy to make users mistakenly think that the device has multiple dmic modules. Currently, in the mainline, no other devicetree out there is using the "sfc" ABI, so we should be able to replace it safely. 2.Rename the original "ssix-ce0" ABIs to "ssix-ce", since the X2000 have only one ce pin. The original naming is easy to make users mistakenly think that the device has multiple ce pins. Currently, in the mainline, no other devicetree out there is using the "ssix-ce0" ABIs, so we should be able to replace it safely. 3.Split the original "sfc" ABI into "sfc-data", "sfc-ce", "sfc-clk" to increase the flexibility when configuring the pins. Currently, in the mainline, no other devicetree out there is using the "sfc" ABI, so we should be able to replace it safely. 4.There is more than one compatible string in the match table, so renaming "ingenic_xxxx_of_match[]" to "ingenic_xxxx_of_matches" is more reasonable, and remove the unnecessary commas in "ingenic_gpio_of_matches[]" to reduce code size as much as possible. Signed-off-by:
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- 10 Aug, 2021 7 commits
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Randy Dunlap authored
Eliminate kernel-doc warnings in drivers/pinctrl/aspeed by using proper kernel-doc notation. Fixes these kernel-doc warnings: drivers/pinctrl/aspeed/pinmux-aspeed.c:61: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * Query the enabled or disabled state for a mux function's signal on a pin drivers/pinctrl/aspeed/pinctrl-aspeed.c:135: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * Search for the signal expression needed to enable the pin's signal for the Signed-off-by:Randy Dunlap <rdunlap@infradead.org> Reported-by:
kernel test robot <lkp@intel.com> Cc: Aditya Srivastava <yashsri421@gmail.com> Cc: Andrew Jeffery <andrew@aj.id.au> Cc: linux-aspeed@lists.ozlabs.org Cc: openbmc@lists.ozlabs.org Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-gpio@vger.kernel.org Acked-by:
Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20210723034840.8752-1-rdunlap@infradead.orgSigned-off-by:
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Marc Zyngier authored
Casting a small array of u8 to an unsigned long is *never* OK: - it does funny thing when the array size is less than that of a long, as it accesses random places in the stack - it makes everything even more fun with a BE kernel Fix this by building the unsigned long used as a bitmap byte by byte, in a way that works across endianess and has no undefined behaviours. An extra BUILD_BUG_ON() catches the unlikely case where the array would be larger than a single unsigned long. Fixes: 1490d9f8 ("pinctrl: Add STMFX GPIO expander Pinctrl/GPIO driver") Signed-off-by:
Marc Zyngier <maz@kernel.org> Cc: stable@vger.kernel.org Cc: Amelie Delaunay <amelie.delaunay@foss.st.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Link: https://lore.kernel.org/r/20210725180830.250218-1-maz@kernel.orgSigned-off-by:
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Alexandre Torgue authored
STM32MP135 SoC embeds 9 GPIO banks of 16 gpios each. Those GPIO banks contain same features as STM32MP157 GPIO banks except that each GPIO line of the STM32MP135 can be secured. Signed-off-by:
Alexandre Torgue <alexandre.torgue@foss.st.com> Acked-by: Arnd Bergmann <arnd@arndb.de Link: https://lore.kernel.org/r/20210723132810.25728-3-alexandre.torgue@foss.st.comSigned-off-by:
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Alexandre Torgue authored
New compatible to manage ball out and pin muxing of STM32MP135 SoC. Signed-off-by:
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Zhen Lei authored
The value of pcs->flags is not overwritten in function pcs_parse_bits_in_pinctrl_entry() and its subfunctions, so moving this check to the beginning of the function eliminates unnecessary rollback operations. Signed-off-by:
Zhen Lei <thunder.leizhen@huawei.com> Reviewed-by:
Tony Lindgren <tony@atomide.com> Link: https://lore.kernel.org/r/20210722033930.4034-3-thunder.leizhen@huawei.comSigned-off-by:
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Zhen Lei authored
Fix to return -ENOTSUPP instead of 0 when PCS_HAS_PINCONF is true, which is the same as that returned in pcs_parse_pinconf(). Fixes: 4e7e8017 ("pinctrl: pinctrl-single: enhance to configure multiple pins of different modules") Reported-by:
Hulk Robot <hulkci@huawei.com> Signed-off-by:
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Bjorn Andersson authored
The SC8180x platform comes with PMC8180 and PMC8180c, add support for the GPIO controller in these PMICs. Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Acked-by:
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- 31 Jul, 2021 2 commits
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Iskren Chernev authored
Based on CAF implementation with egpio/wake_reg support removed. Similar function names were merged to reduce total number of functions. Signed-off-by:
Iskren Chernev <iskren.chernev@gmail.com> Reviewed-by:
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Iskren Chernev authored
Add device tree binding Documentation details for Qualcomm SM6115 and SM4250 pinctrl. Signed-off-by:
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- 30 Jul, 2021 8 commits
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Linus Walleij authored
Merge tag 'renesas-pinctrl-for-v5.15-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v5.15 - Add bias support for the R-Car D3 SoC, - Miscellaneous fixes and improvements.
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Sai Krishna Potthuri authored
Add support for generic pin parameter 'power-source'. To maintain the backward compatibility, 'io-standard' parameter is still supported in the driver. Signed-off-by:
Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> Link: https://lore.kernel.org/r/1626868353-96475-4-git-send-email-lakshmi.sai.krishna.potthuri@xilinx.comSigned-off-by:
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Sai Krishna Potthuri authored
Replace custom pin configuration option 'io-standard' with generic property 'power-source' for Zynq pinctrl also add dt-binding file contains pin configuration defines for Zynq pinctrl. Signed-off-by:
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Sai Krishna Potthuri authored
Convert the Zynq pinctrl binding file to yaml. Signed-off-by:
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Jiaxun Yang authored
So it will be avilable for generic MIPS kernel. -- Signed-off-by:
Jiaxun Yang <jiaxun.yang@flygoat.com> v3: Depend on OF as well Link: https://lore.kernel.org/r/20210721030134.10562-7-jiaxun.yang@flygoat.comSigned-off-by:
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Fabio Estevam authored
The imx_pinctrl_soc_info structure content is never changed, so it can be declared as 'const', like it is done on all other i.MX pinctrl drivers. Make it 'const' in this driver too. Reported-by:
Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by:
Fabio Estevam <festevam@gmail.com> Link: https://lore.kernel.org/r/20210716131341.3370620-1-festevam@gmail.comSigned-off-by:
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Fabio Estevam authored
The imx_pinctrl_soc_info structure content is never changed, so it can be declared as 'const', like it is done on all other i.MX pinctrl drivers. Make it 'const' in this driver too. Signed-off-by:
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Fabio Estevam authored
The imx_pinctrl_soc_info structure content is never changed, so it can be declared as 'const', like it is done on all other i.MX pinctrl drivers. Make it 'const' in this driver too. Signed-off-by:
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- 27 Jul, 2021 1 commit
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Geert Uytterhoeven authored
As R-Car H3 ES1.x (R8A77950) and R-Car ES2.0+ (R8A77951) use the same compatible value, the pin control driver relies on soc_device_match() with soc_id = "r8a7795" and the (non)matching of revision = "ES1.*" to match with and distinguish between the two SoC variants. The corresponding entries in the normal of_match_table are present only to make the optional sanity checks work. The R-Car H3e-2G (R8A779M1) SoC is a different grading of the R-Car H3 ES3.0 (R8A77951) SoC. It uses the same compatible values for individual devices, but has an additional compatible value for the root node. When running on an R-Car H3e-2G SoC, soc_device_match() with soc_id = "r8a7795" does not return a match. Hence the pin control driver falls back to the normal of_match_table, and, as the R8A77950 entry is listed first, incorrectly uses the sub-driver for R-Car H3 ES1.x. Fix this by moving the entry for R8A77951 before the entry for R8A77950. Simplify sh_pfc_quirk_match() to only handle R-Car H3 ES1,x, as R-Car H3 ES2.0+ can now be matched using the normal of_match_table as well. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by:
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/6cdc5bfa424461105779b56f455387e03560cf66.1626707688.git.geert+renesas@glider.be
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- 23 Jul, 2021 12 commits
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Fabio Estevam authored
The initialization of pin_reg is missing, causing the following build warning: drivers/pinctrl/freescale/pinctrl-imx8ulp.c:228:35: warning: 'pin_reg' is used uninitialized in this function [-Wuninitialized] Initialize pin_reg the same way as it is done on vf610 and imx7ulp to fix the problem. Fixes: 16b343e8 ("pinctrl: imx8ulp: Add pinctrl driver support") Reported-by:
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Bhupesh Sharma authored
SA8155p-adp PMIC (PMM8155AU) exposes 10 GPIOs. Add support for the same in the pinctrl driver. Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by:
Bhupesh Sharma <bhupesh.sharma@linaro.org> Link: https://lore.kernel.org/r/20210629123407.82561-5-bhupesh.sharma@linaro.orgSigned-off-by:
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Bhupesh Sharma authored
Arrange the compatibles inside qcom pinctrl-spmi gpio driver alphabetically. Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by:
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Bhupesh Sharma authored
Add pmic-gpio compatible string for pmm8155au pmic found on the SA8155p-adp board. Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by:
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Bhupesh Sharma authored
Arrange the compatibles inside qcom-pmic gpio device tree bindings alphabetically. While at it, also make some minor cosmetic changes to allow future compatible addition to the bindings simpler. Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by:
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kernel test robot authored
drivers/pinctrl/mediatek/pinctrl-mt8365.c:488:3-8: No need to set .owner here. The core will do it. Remove .owner field if calls are used which set it automatically Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci Fixes: e94d8b6f ("pinctrl: mediatek: add support for mt8365 SoC") CC: Fabien Parent <fparent@baylibre.com> Reported-by:
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Anson Huang authored
Add i.MX8ULP pinctrl driver support. Signed-off-by:
Anson Huang <Anson.Huang@nxp.com> Signed-off-by:
Jacky Bai <ping.bai@nxp.com> Reviewed-by:
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Jacky Bai authored
Add pinctrl binding doc for i.MX8ULP Signed-off-by:
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Marek Behún authored
The PWM pins on North Bridge on Armada 37xx can be configured into PWM or GPIO functions. When in PWM function, each pin can also be configured to drive low on 0 and tri-state on 1 (LED mode). The current definitions handle this by declaring two pin groups for each pin: - group "pwmN" with functions "pwm" and "gpio" - group "ledN_od" ("od" for open drain) with functions "led" and "gpio" This is semantically incorrect. The correct definition for each pin should be one group with three functions: "pwm", "led" and "gpio". Change the "pwmN" groups to support "led" function. Remove "ledN_od" groups. This cannot break backwards compatibility with older device trees: no device tree uses it since there is no PWM driver for this SOC yet. Also "ledN_od" groups are not even documented. Fixes: b835d695 ("pinctrl: armada-37xx: swap polarity on LED group") Signed-off-by:Marek Behún <kabel@kernel.org> Acked-by:
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Jason Wang authored
The if condition followed by BUG can be replaced to BUG_ON which is more compact and formal in linux source. Signed-off-by:
Jason Wang <wangborong@cdjrlc.com> Acked-by:
Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20210624064913.41788-1-wangborong@cdjrlc.comSigned-off-by:
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Konrad Dybcio authored
Add a pinctrl driver to allow for managing SoC pins. Signed-off-by:
Konrad Dybcio <konrad.dybcio@somainline.org> Reviewed-by:
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Konrad Dybcio authored
Document the newly added MDM9607 pinctrl driver. Signed-off-by:
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- 13 Jul, 2021 2 commits
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Geert Uytterhoeven authored
Implement support for pull-up (most pins, excl. DU_DOTCLKIN0) and pull-down (most pins, excl. JTAG) handling for the R-Car D3 SoC, using some parts from the common R-Car bias handling, which requires making rcar_pin_to_bias_reg() public. R-Car D3 needs special handling for the NFRE# (GP_3_0) and NFWE# (GP_3_1) pins. Unlike all other pins, they are controlled by different bits in the LSI pin pull-up/down control register (PUD2) than in the LSI pin pull-enable register (PUEN2). Signed-off-by:
Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/04aad2b0bf82a32fb08e5e21e4ac1fb03452724f.1625064076.git.geert+renesas@glider.be
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Geert Uytterhoeven authored
When disabling pin bias, there is no need to touch the LSI pin pull-up/down control register (PUDn), which selects between pull-up and pull-down. Just disabling the pull-up/down function through the LSI pin pull-enable register (PUENn) is sufficient. Signed-off-by:
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- 11 Jul, 2021 2 commits
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Linus Torvalds authored
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Hugh Dickins authored
I know nothing about zone_device pages and !device_private pages; but if try_to_migrate_one() will do nothing for them, then it's better that try_to_migrate() filter them first, than trawl through all their vmas. Signed-off-by:
Hugh Dickins <hughd@google.com> Reviewed-by:
Shakeel Butt <shakeelb@google.com> Reviewed-by:
Alistair Popple <apopple@nvidia.com> Link: https://lore.kernel.org/lkml/1241d356-8ec9-f47b-a5ec-9b2bf66d242@google.com/ Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Jason Gunthorpe <jgg@nvidia.com> Cc: Ralph Campbell <rcampbell@nvidia.com> Cc: Christoph Hellwig <hch@lst.de> Cc: Yang Shi <shy828301@gmail.com> Cc: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> Signed-off-by:
Linus Torvalds <torvalds@linux-foundation.org>
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