- 15 Jun, 2023 40 commits
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Luben Tuikov authored
Report the number of records stored in the RAS EEPROM table in debugfs. This can be used by user-space to calculate the capacity of the RAS EEPROM table since "bad_page_cnt_threshold" is also reported in the same place in debugfs. See commit 7fb64071 ("drm/amdgpu: Add bad_page_cnt_threshold to debugfs"). ras_num_recs can already be inferred by dumping the RAS EEPROM table, also in the same debugfs location, see commit reference c65b0805 (drm/amdgpu: RAS EEPROM table is now in debugfs, 2021-04-08). This commit makes it an integer value easily shown in a single file. Cc: Alex Deucher <Alexander.Deucher@amd.com> Cc: Hawking Zhang <Hawking.Zhang@amd.com> Cc: Tao Zhou <tao.zhou1@amd.com> Cc: Stanley Yang <Stanley.Yang@amd.com> Cc: John Clements <john.clements@amd.com> Signed-off-by:
Luben Tuikov <luben.tuikov@amd.com> Link: https://lore.kernel.org/r/20230603051043.211548-1-luben.tuikov@amd.comAcked-by:
Alex Deucher <Alexander.Deucher@amd.com> Signed-off-by:
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Mukul Joshi authored
Remove DUMMY_VRAM_SIZE as it is not needed and can result in reporting incorrect memory size. Signed-off-by:
Mukul Joshi <mukul.joshi@amd.com> Acked-by:
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Lijo Lazar authored
Release ECC irq only if irq is enabled - only when RAS feature is enabled ECC irq gets enabled. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Likun Gao authored
Spirom update typically requires extremely long duration for command execution, and special helper function to wait for it completion. Signed-off-by:
Likun Gao <Likun.Gao@amd.com> Reviewed-by:
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Srinivasan Shanmugam authored
Fixes the following W=1 kernel build warning: display/dc/dcn10/dcn10_optc.c:45: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * apply_front_porch_workaround TODO FPGA still need? display/dc/dcn10/dcn10_optc.c:136: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * program_timing_generator used by mode timing set display/dc/dcn10/dcn10_optc.c:391: warning: Function parameter or member 'optc' not described in 'optc1_set_timing_double_buffer' display/dc/dcn10/dcn10_optc.c:391: warning: Function parameter or member 'enable' not described in 'optc1_set_timing_double_buffer' display/dc/dcn10/dcn10_optc.c:404: warning: Function parameter or member 'optc' not described in 'optc1_unblank_crtc' display/dc/dcn10/dcn10_optc.c:404: warning: expecting prototype for unblank_crtc(). Prototype was for optc1_unblank_crtc() instead display/dc/dcn10/dcn10_optc.c:427: warning: Function parameter or member 'optc' not described in 'optc1_blank_crtc' display/dc/dcn10/dcn10_optc.c:427: warning: expecting prototype for blank_crtc(). Prototype was for optc1_blank_crtc() instead display/dc/dcn10/dcn10_optc.c:496: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * Enable CRTC display/dc/dcn10/dcn10_optc.c:895: warning: Cannot understand ***************************************************************************** on line 895 - I thought it was a doc line Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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Srinivasan Shanmugam authored
Fixes the following gcc with W=1: drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_resource_helpers.c:285: warning: Function parameter or member 'dc' not described in 'dcn32_determine_det_override' drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_resource_helpers.c:285: warning: Function parameter or member 'context' not described in 'dcn32_determine_det_override' drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_resource_helpers.c:285: warning: Function parameter or member 'pipes' not described in 'dcn32_determine_det_override' drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_resource_helpers.c:624: warning: Cannot understand * ***************************************************************** drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_resource_helpers.c:676: warning: Cannot understand * ***************************************************************** Cc: Alvin Lee <alvin.lee2@amd.com> Cc: Stylon Wang <stylon.wang@amd.com> Cc: Hamza Mahfooz <hamza.mahfooz@amd.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
Alvin Lee <alvin.lee2@amd.com> Signed-off-by:
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Srinivasan Shanmugam authored
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_optc.c:109: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * Enable CRTC Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Srinivasan Shanmugam authored
Fixes the following gcc with W=1: drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/dcn32_fpu.c:872: warning: Excess function parameter 'drr_pipe' description in 'subvp_drr_schedulable' drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/dcn32_fpu.c:1030: warning: Cannot understand * **************************************************** Cc: Stylon Wang <stylon.wang@amd.com> Cc: Hamza Mahfooz <hamza.mahfooz@amd.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
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Srinivasan Shanmugam authored
Fixes the following W=1 kernel build warning: display/dc/dcn10/dcn10_opp.c:52: warning: Function parameter or member 'oppn10' not described in 'opp1_set_truncation' display/dc/dcn10/dcn10_opp.c:52: warning: Function parameter or member 'params' not described in 'opp1_set_truncation' display/dc/dcn10/dcn10_opp.c:52: warning: expecting prototype for set_truncation(). Prototype was for opp1_set_truncation() instead display/dc/dcn10/dcn10_opp.c:161: warning: Function parameter or member 'oppn10' not described in 'opp1_set_pixel_encoding' display/dc/dcn10/dcn10_opp.c:161: warning: Function parameter or member 'params' not described in 'opp1_set_pixel_encoding' display/dc/dcn10/dcn10_opp.c:161: warning: expecting prototype for set_pixel_encoding(). Prototype was for opp1_set_pixel_encoding() instead display/dc/dcn10/dcn10_opp.c:183: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * Set Clamping Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Srinivasan Shanmugam authored
drm/amdgpu: Add missing function parameter 'optc' & 'enable' to kdoc in optc3_set_timing_double_buffer() Fixes the following gcc with W=1: drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_optc.c:285: warning: Function parameter or member 'optc' not described in 'optc3_set_timing_double_buffer' drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_optc.c:285: warning: Function parameter or member 'enable' not described in 'optc3_set_timing_double_buffer' Cc: Harry Wentland <harry.wentland@amd.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
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Ma Jun authored
Modify the debug information and print the clien id for these interrupts as well. Signed-off-by:
Ma Jun <Jun.Ma2@amd.com> Reviewed-by:
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Ruili Ji authored
Flag trap_en should be enabled for trap handler. Signed-off-by:
Ruili Ji <ruiliji2@amd.com> Signed-off-by:
Aaron Liu <aaron.liu@amd.com> Reviewed-by:
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Alex Deucher authored
Don't free the memory if we are hitting this as part of suspend. This way we don't free any memory during suspend; see amdgpu_bo_free_kernel(). The memory will be freed in the first non-suspend modeset or when the driver is torn down. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2568Acked-by:
Harry Wentland <harry.wentland@amd.com> Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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Alex Deucher authored
This reverts commit 58e67bb3. This patch was reverted, but came back again as commit 58e67bb3 ("drm/amd/display: fix dpms_off issue when disabling bios mode") Revert it again as it breaks Asus G513QY / 6800M laptops. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2259 Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Zhongwei <Zhongwei.Zhang@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Mike Lothian <mike@fireburn.co.uk> Reviewed-by:
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Jonathan Kim authored
Null check should be done on queue struct itself and not on the process queue list node. Signed-off-by:
Jonathan Kim <jonathan.kim@amd.com> Reviewed-by:
Felix Kuehling <felix.kuehling@amd.com> Signed-off-by:
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Tim Huang authored
Add the ability to control the vclk and dclk frequency by power_dpm_force_performance_level interface. Signed-off-by:
Tim Huang <Tim.Huang@amd.com> Acked-by:
Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by:
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Srinivasan Shanmugam authored
Fixes the following gcc with W=1: In file included from ./include/linux/string.h:253, from ./include/linux/bitmap.h:11, from ./include/linux/cpumask.h:12, from ./arch/x86/include/asm/cpumask.h:5, from ./arch/x86/include/asm/msr.h:11, from ./arch/x86/include/asm/processor.h:22, from ./arch/x86/include/asm/cpufeature.h:5, from ./arch/x86/include/asm/thread_info.h:53, from ./include/linux/thread_info.h:60, from ./arch/x86/include/asm/preempt.h:7, from ./include/linux/preempt.h:78, from ./include/linux/spinlock.h:56, from ./include/linux/mmzone.h:8, from ./include/linux/gfp.h:7, from ./include/linux/firmware.h:7, from drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/sienna_cichlid_ppt.c:26: In function ‘fortify_memcpy_chk’, inlined from ‘sienna_cichlid_append_powerplay_table’ at drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/sienna_cichlid_ppt.c:444:2, inlined from ‘sienna_cichlid_setup_pptable’ at drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/sienna_cichlid_ppt.c:506:8, inlined from ‘sienna_cichlid_setup_pptable’ at drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/sienna_cichlid_ppt.c:494:12: ./include/linux/fortify-string.h:413:4: warning: call to ‘__read_overflow2_field’ declared with attribute warning: detected read beyond size of field (2nd parameter); maybe use struct_group()? [-Wattribute-warning] 413 | __read_overflow2_field(q_size_field, size); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ the compiler complains about the size calculation in the memcpy() - "sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header)" is much larger than what fits into table_member. Hence, reuse 'smu_memcpy_trailing' for nv1x Fixes: 7077b19a ("drm/amd/pm: use macro to get pptable members") Suggested-by:Evan Quan <Evan.Quan@amd.com> Cc: Evan Quan <Evan.Quan@amd.com> Cc: Chengming Gui <Jack.Gui@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Tim Huang authored
PMFW use the left-shifted 16 bits argument to set the VCLK DPM frequency for SMU v13.0.5. Signed-off-by:
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Aric Cyr authored
This version brings along following fixes: - Improvement on eDP - PSR bug fixes - SubVP bug fixes - Improvements on pipe handling to address potential issues - Freesync bug fix - DPIA bug fix - Fix multi-display issues Acked-by:
Stylon Wang <stylon.wang@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Dmytro Laktyushkin authored
The k1/k2 pixel rate dividers in dccg should only be updated on stream enable and do not actually depend on whether odm combine is active. This removes an on flip update of these and fixes the calculate function to ignore odm status for dp steams. Acked-by:
Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> Reviewed-by:
Ariel Bernstein <Eric.Bernstein@amd.com> Tested-by:
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Samson Tam authored
Revert commit 5f3401ee ("drm/amd/display: reallocate DET for dual displays with high pixel rate ratio") [Why] Previously had modified DET allocation algorithm to allocate less DET segments for lower pixel rate display and more DET segments for higher pixel rate display. But noticed it is causing underflow when higher pixel rate display is not displaying at higher mode [How] Roll back change Acked-by:
Samson Tam <samson.tam@amd.com> Reviewed-by:
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Peichen Huang authored
[Why] DPIA doesn't support UHBR, driver should not enable UHBR for dp tunneling [How] limit DPIA link rate to HBR3 Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Acked-by:
Peichen Huang <peichen.huang@amd.com> Reviewed-by:
Mustapha Ghaddar <Mustapha.Ghaddar@amd.com> Tested-by:
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Alvin Lee authored
[Description] - Missed color / CSC updates in fast update path which caused Custom Color to break. - Add color / CSC updates to new fast update path to fix custom color Acked-by:
Jun Lei <jun.lei@amd.com> Tested-by:
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Austin Zheng authored
Why: Some EDIDs report a minimum refresh rate lower than what HW can support How: Add a check to calculate minimum supported refresh rate with current timing and use that as the minimum if a lower one is passed in Acked-by:
Austin Zheng <austin.zheng@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Tested-by:
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Artem Grishin authored
[Why] When iterating over all pipes in the loop, the CRB allocation algorithm may potentially skip some of the pipes. Previously, the current pipe index didn't get updated in this case, causing incorrect outcome. [How] Increment the pipe index when skipping over a pipe in the loop. Acked-by:
Artem Grishin <artem.grishin@amd.com> Reviewed-by:
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Alvin Lee authored
[Description] PSR implementation in FW has inline polling which can poll for up to 1ms. This will interfere with SubVP because SubVP is timing sensitive and can't tolerate up to 1ms worth of delay before handling vertical or VLINE interrupts. Therefore block SubVP + DRR cases if DRR is PSR capable Acked-by:
Saaem Rizvi <SyedSaaem.Rizvi@amd.com> Tested-by:
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Saaem Rizvi authored
[Why and How] We should not disable phantom pipes in this sequence, as this should be controlled by FW. Furthermore, the previous programming sequence would have enabled the phantom pipe in driver as well, causing corruption. This change should avoid this from occuring. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Acked-by:
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Alvin Lee authored
Re-enable SubVP high refresh now that it is fixed for displays with high refresh rates. Acked-by:
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Daniel Miess authored
[Why & How] Bugs preventing DPP/HUBP power gating have been addressed so this should be reenabled on dcn314 for sufficient hardware rev versions Acked-by:
Daniel Miess <daniel.miess@amd.com> Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by:
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Alvin Lee authored
[Description] - SubVP high refresh should only be enabled if all displays are >= 120hz. We do not want to accidentally enables configs such as 60hz[SubVP] + 120hz[SubVP] - Ensure that the SubVP config generation code does not produce configs such as 60hz[SubVP] + 120hz[SubVP] - Also add admissibility checks to ensure these configs do not pass as valid configs Acked-by:
Dillon Varone <Dillon.Varone@amd.com> Tested-by:
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Tom Chung authored
[Why] dmub_psr_get_state() return an invalid PSR state while disable the PSR because convert_psr_state() doesn't recognize the state that return from DMCUB. [How] Add a PSR state to make the dmub_psr_get_state() return a correct PSR state. Acked-by:
Tom Chung <chiahsuan.chung@amd.com> Reviewed-by:
Wayne Lin <Wayne.Lin@amd.com> Tested-by:
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Tom Chung authored
[Why] When the PSR enabled. If you try to adjust the timing parameters, it may cause system hang. Because the timing mismatch with the DMCUB settings. [How] Disable the PSR before adjusting timing parameters. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Acked-by:
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Aric Cyr authored
Acked-by:
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Fangzhi Zuo authored
Any invalid mode from hw perspective should be given corresponding error code, otherwise it leads to confusing warning message "[drm] Mode Validation Warning: Validation OK failed validation." Acked-by:
Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by:
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Austin Zheng authored
Why: Log DP2 data to be used for debugging purposes How: Check the reported link rate of the DP connection and translate it to the DP version. Acked-by:
Martin Leung <Martin.Leung@amd.com> Tested-by:
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Hersen Wu authored
[Why] within dc_link_detect, edp edid is read only for the first time and saved. edid will not be read after the first time read. to run edp edid read test, need read edp edid for each dc_link_detect. dc->config flag allow_edp_hotplug_detection could be used for edp edid test. [How] add debugfs for dc->config.allow_edp_hotplug_detection Acked-by:
Hersen Wu <hersenxs.wu@amd.com> Reviewed-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by:
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Hersen Wu authored
[Why] most edp support only timings from edid. applying non-edid timings, especially those timings out of edp bandwidth, may damage edp. [How] do not add non-edid timings for edp. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Acked-by:
Roman Li <roman.li@amd.com> Tested-by:
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Arunpravin Paneer Selvam authored
This reverts commit c1055186. This patch disables the TOPDOWN flag for APU and few dGPU cards which has the VRAM size equal to the BAR size. When we enable the TOPDOWN flag, we get the free blocks at the highest available memory region and we don't split the lower order blocks. This change is required to keep off the fragmentation related issues particularly in ASIC which has VRAM space <= 500MiB Hence, we are reverting this patch. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2270Signed-off-by:
Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Shiwu Zhang authored
Add these two dev attrs for xgmi info details which is helpful for developers checking the xgmi topology by catting the sys file directly. Take 4 cards with xgmi connection as an example, get the num_hops for each device or node through xmig_hive_info dir like, cat /sys/bus/pci/devices/0000:41:00.0/xgmi_hive_info/node1/num_hops will return "00 41 41 41" where "00" stands for the hops to node1 itself and "41" is the hops in hex format to every other node in the same hive. There are node1/node2/node3/node4 representing 4 cards in the hive. The same for num_links dev attr. Signed-off-by:
Shiwu Zhang <shiwu.zhang@amd.com> Acked-by:
Le Ma <le.ma@amd.com> Reviewed-by:
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Sonny Jiang authored
Only vcn0 can process AV1 codecx. In order to use both vcn0 and vcn1 in h264/265 transcode to AV1 cases, set vcn0 sched score to 1 at initialization time. Signed-off-by:
Sonny Jiang <sonjiang@amd.com> Reviewed-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
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