- 20 Mar, 2023 1 commit
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Mukesh Ojha authored
During normal restart of a system download bit should be cleared irrespective of whether download mode is set or not. Fixes: 8c1b7dc9 ("firmware: qcom: scm: Expose download-mode control") Signed-off-by:
Mukesh Ojha <quic_mojha@quicinc.com> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/1678979666-551-1-git-send-email-quic_mojha@quicinc.com
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- 16 Mar, 2023 3 commits
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Melody Olvera authored
Add compatible for QDU1000 and QRU1000 aoss devices. Signed-off-by:
Melody Olvera <quic_molvera@quicinc.com> Acked-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
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Melody Olvera authored
Update compatible for QDU1000 and QRU1000 to include the interconnect these devices have. Signed-off-by:
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Devi Priya authored
Document the compatible for RPM communication over SMD for IPQ9574 SoC Signed-off-by:
Devi Priya <quic_devipriy@quicinc.com> Acked-by:
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- 15 Mar, 2023 26 commits
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Elliot Berman authored
The maximum VMID for assign_mem is 63. Use a u64 to represent this bitmap instead of architecture-dependent "unsigned int" which varies in size on 32-bit and 64-bit platforms. Acked-by: Kalle Valo <kvalo@kernel.org> (ath10k) Tested-by:
Gokul krishna Krishnakumar <quic_gokukris@quicinc.com> Signed-off-by:
Elliot Berman <quic_eberman@quicinc.com> Reviewed-by:
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Kathiravan T authored
Document the compatible for IPQ5332 SCM. Acked-by:
Kathiravan T <quic_kathirav@quicinc.com> Signed-off-by:
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Poovendhan Selvaraj authored
Add the scm compatible string for IPQ9574 SoC Acked-by:
Poovendhan Selvaraj <quic_poovendh@quicinc.com> Signed-off-by:
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Konrad Dybcio authored
It goes without saying that socname_rpmpds[] is the array of the RPM power domains associated with socname. Remove these comments. Signed-off-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
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Konrad Dybcio authored
The GPU core clock requires that both VDDGX and VDDMX domains are scaled at the same rate at the same time (well, MX just before GX but you get the idea). Set MX as parent of GX to take care of that. Suggested-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
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Konrad Dybcio authored
In some cases (like with the GPU core clock on GMU-less SoCs) it's required that we scale more than one voltage domain. This can be achieved by linking them in a parent-child relationship. Add support for specifying a parent PD, similarly to what has been done in the RPMhPD driver. Signed-off-by:
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Konrad Dybcio authored
Currently the whitespace between [DT_BINDING] = &struct is all over the place.. some SoC structs have a space, others have a tab, others have N tabs.. Make that a single tab for everybody to keep things coherent. Signed-off-by:
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Konrad Dybcio authored
Now that we aren't bound by the preprocessor macros, improve the naming to be a bit less preprocessor-y and touch up some rpmpd.pd.name fields while at it. Signed-off-by:
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Konrad Dybcio authored
Expand the struct definition macros to make things easier to see and maintain. Now that the macros are unnecessary, remove them. Signed-off-by:
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Konrad Dybcio authored
It's rather obvious by the characteristic of these resources that they correspond to some voltage lines governed by RPM. Remove the "vdd" unnecessary prefix from them. Signed-off-by:
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Konrad Dybcio authored
Up until now, we had 2 separate entries for VDD_LPI[CM]X and VDD_LPI_[CM]X which both pointed to the same RPM resource. Fix it. Signed-off-by:
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Konrad Dybcio authored
Keep all definitions in one place in preparation for a cleanup to make things tidier. Signed-off-by:
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Konrad Dybcio authored
Replace the SoC names with type+id_key (or type+id+..name..+key for fixed-key definitions) and remove duplicate entries. Signed-off-by:
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David Wronek authored
Add Soc ID table entries for Qualcomm SM7150. Signed-off-by:
David Wronek <davidwronek@gmail.com> Signed-off-by:
Danila Tikhonov <danila@jiaxyga.com> Signed-off-by:
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David Wronek authored
Add the ID for the Qualcomm SM7150 SoC. Signed-off-by:
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Bhupesh Sharma authored
Add the ID for QRB4210 variant. Signed-off-by:
Bhupesh Sharma <bhupesh.sharma@linaro.org> Signed-off-by:
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Bhupesh Sharma authored
Add the ID for QRB4210 variant. Signed-off-by:
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Varadarajan Narayanan authored
Add SOC ID for Qualcomm IPQ9574, IPQ9570, IPQ9554, IPQ9550, IPQ9514 and IPQ9510 Signed-off-by:
Varadarajan Narayanan <quic_varada@quicinc.com> Reviewed-by:
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Varadarajan Narayanan authored
Add SOC ID for Qualcomm IPQ9574, IPQ9570, IPQ9554, IPQ9550, IPQ9514 and IPQ9510 Signed-off-by:
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Manivannan Sadhasivam authored
The platforms based on SDM845 SoC locks the access to EDAC registers in the bootloader. So probing the EDAC driver will result in a crash. Hence, disable the creation of EDAC platform device on all SDM845 devices. The issue has been observed on Lenovo Yoga C630 and DB845c. While at it, also sort the members of `struct qcom_llcc_config` to avoid any holes in-between. Cc: <stable@vger.kernel.org> # 5.10 Reported-by:
Steev Klimaszewski <steev@kali.org> Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by:
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Manivannan Sadhasivam authored
Not all Qcom platforms support IRQ mode for ECC handling. For those platforms, the current EDAC driver will not be probed due to missing ECC IRQ in devicetree. So add support for polling mode so that the EDAC driver can be used on all Qcom platforms supporting LLCC. The polling delay of 5000ms is chosen based on Qcom downstream/vendor driver. Reported-by:
Luca Weiss <luca.weiss@fairphone.com> Tested-by:
Borislav Petkov (AMD) <bp@alien8.de> Signed-off-by:
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Manivannan Sadhasivam authored
The Qualcomm LLCC/EDAC drivers were using a fixed register stride for accessing the (Control and Status Registers) CSRs of each LLCC bank. This stride only works for some SoCs like SDM845 for which driver support was initially added. But the later SoCs use different register stride that vary between the banks with holes in-between. So it is not possible to use a single register stride for accessing the CSRs of each bank. By doing so could result in a crash. For fixing this issue, let's obtain the base address of each LLCC bank from devicetree and get rid of the fixed stride. This also means, there is no need to rely on reg-names property and the base addresses can be obtained using the index. First index is LLCC bank 0 and last index is LLCC broadcast. If the SoC supports more than one bank, then those need to be defined in devicetree for index from 1..N-1. Reported-by:
Parikshit Pareek <quic_ppareek@quicinc.com> Tested-by:
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Manivannan Sadhasivam authored
Register regions of the LLCC banks are located at different addresses. Currently, the binding just lists the LLCC0 base address and tries to cover all the banks using a single size. This is entirely wrong as there are other register regions that happen to lie inside the size covered by the binding such as the memory controller and holes. So this needs to be fixed by specifying the base address of individual LLCC banks. This approach will break the existing users of this binding as the register regions are split and the drivers now cannot use LLCC0 register region for accessing rest of the banks (which is wrong anyway). But considering the fact that the binding was wrong from the day one and also the device drivers going wrong by the binding, this breakage is acceptable. Reported-by:
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Manivannan Sadhasivam authored
Both Rishabh and Sai have left Qualcomm, and there is no evidence of them maintaining with a new identity. So their entry needs to be removed. Listed Bjorn as the interim maintainer until someone volunteers to maintain this binding. Signed-off-by:
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Konrad Dybcio authored
Add the missing IDs for scuba and its QRB variant. Signed-off-by:
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Konrad Dybcio authored
Add the missing IDs for scuba and its QRB variant. Acked-by:
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- 14 Mar, 2023 1 commit
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Visweswara Tanuku authored
From QUP HW Version 3.10 and above the Tx and Rx fifo depth bits are increased to 23:16 bits from 21:16 bits in SE_HW_PARAM registers accomodating 256bytes of fifo depth. Updated geni_se_get_tx_fifo_depth and geni_se_get_rx_fifo_depth to retrieve right fifo depth based on QUP HW version. Signed-off-by:
Visweswara Tanuku <quic_vtanuku@quicinc.com> Signed-off-by:
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- 13 Mar, 2023 8 commits
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Konrad Dybcio authored
Add some missing PMICs based on the _SUBTYPE defines in include/soc/qcom/qcom-spmi-pmic.h Signed-off-by:
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Bartosz Golaszewski authored
Add SocInfo support for SA8775P. Signed-off-by:
Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by:
Eric Chanudet <echanude@redhat.com> Tested-by: Eric Chanudet <echanude@redhat.com> # sa8775p-ride Reviewed-by:
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Bartosz Golaszewski authored
Add the SoC ID entry for SA8775P. Signed-off-by:
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Bartosz Golaszewski authored
Update max processor count to reflect the number of co-processors on SA8775P SoCs. Signed-off-by:
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Krzysztof Kozlowski authored
The qcom,intents property is a list of pairs, thus it should be defined as uint32-matrix. Fixes: b2d7616e ("dt-bindings: soc: qcom: apr: add missing properties") Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Krzysztof Kozlowski authored
The QCOM_KRYO_L2_ACCESSORS can be compile tested only on ARM64 because it references asm/sysreg.h present only on ARM64. Mark the dependency correct, even though as a non-selectable option it does not have real effect. Signed-off-by:
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Rob Herring authored
It is preferred to use typed property access functions (i.e. of_property_read_<type> functions) rather than low-level of_get_property/of_find_property functions for reading properties. As part of this, convert of_get_property/of_find_property calls to the recently added of_property_present() helper when we just want to test for presence of a property and nothing more. Signed-off-by:
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Krzysztof Kozlowski authored
The driver can be compile tested with !CONFIG_OF making certain data unused: drivers/soc/qcom/qcom_gsbi.c:117:34: error: ‘tcsr_dt_match’ defined but not used [-Werror=unused-const-variable=] Signed-off-by:
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- 05 Mar, 2023 1 commit
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Linus Torvalds authored
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