- 09 Oct, 2023 40 commits
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Dmitry Baryshkov authored
Don't register the 'fb' debugfs file, if there is no KMS (and so no framebuffers). Reviewed-by:
Rob Clark <robdclark@gmail.com> Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/561650/Signed-off-by:
Rob Clark <robdclark@chromium.org>
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Dmitry Baryshkov authored
There is little point in having the empty debugfs file which always returns -ENODEV. Change this file to be created only if KMS is actually used. Reviewed-by:
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Dmitry Baryshkov authored
Switch to drmm_mode_config_init() instead of drm_mode_config_init(). Drop drm_mode_config_cleanup() calls. Reviewed-by:
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Dmitry Baryshkov authored
The msm_drv_shutdown function should only be used in the KMS case. Rename it accordingly. Reviewed-by:
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Dmitry Baryshkov authored
The msm_drv_shutdown only makes sense for the KMS-enabled devices, while msm_platform_driver is only used in the headless case. Remove the shutdown callback from the driver structure. Reviewed-by:
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Dmitry Baryshkov authored
Rename the msm_pm_prepare() and msm_pm_complete() to msm_kms_pm_prepare() and msm_kms_pm_complete() consequently. Reviewed-by:
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Dmitry Baryshkov authored
The msm_pm_prepare()/msm_pm_complete() only make sense for the KMS-enabled devices, they have priv->kms guards inside. Drop global msm_pm_ops, which were used only by the headless msm device. Reviewed-by:
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Dmitry Baryshkov authored
As all output devices have switched to devm_drm_bridge_add(), we can drop the bridges array from struct msm_drm_private. Reviewed-by:
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Dmitry Baryshkov authored
Make MSM DP driver use devm_drm_bridge_add() instead of plain drm_bridge_add(). As the driver doesn't require any additional cleanup, stop adding created bridge to the priv->bridges array. Reviewed-by:
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Dmitry Baryshkov authored
The dp_drm needs accessing the DP's platform device. Move pdev to the public structure. Reviewed-by:
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Dmitry Baryshkov authored
Make MSM HDMI driver use devm_drm_bridge_add() instead of plain drm_bridge_add(). As the driver doesn't require any additional cleanup, stop adding created bridge to the priv->bridges array. Reviewed-by:
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Dmitry Baryshkov authored
Make MSM DSI driver use devm_drm_bridge_add() instead of plain drm_bridge_add(). As the driver doesn't require any additional cleanup, stop adding created bridge to the priv->bridges array. Reviewed-by:
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Dmitry Baryshkov authored
To let the probe function bail early if any of the resources is unavailable, move resource allocattion from kms_init directly to the probe callback. Reviewed-by:
Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by:
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Dmitry Baryshkov authored
To let the probe function bail early if any of the resources is unavailable, move resource allocattion from kms_init directly to the probe callback. While we are at it, replace irq_of_parse_and_map() with platform_get_irq(). Reviewed-by:
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Dmitry Baryshkov authored
To let the probe function bail early if any of the resources is unavailable, move resource allocattion from kms_init directly to the probe callback. While we are at it, replace irq_of_parse_and_map() with platform_get_irq(). This also drops devm_iounmap() calls. It is too early to have them _dpu_kms_hw_destroy() (or it will break if for some reason DPU device is rebound into the composite device) and it doesn't make sense to have them in dpu_dev_remove (as everything will be torn down by the devres anyway after the device is unbound from the driver). Reviewed-by:
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Dmitry Baryshkov authored
In preparation of moving resource allocation to the probe time, allow MSM KMS drivers to pass struct msm_kms pointer via msm_drv_probe(). Reviewed-by:
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Konrad Dybcio authored
Downstream calls this the "speedbin 1", but that number is already occupied. Use index two. Signed-off-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/559607/Signed-off-by:
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Konrad Dybcio authored
Some (many?) devices with A635 expect a ZAP shader to be loaded. Set the file name to allow for that. Signed-off-by:
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Konrad Dybcio authored
When opp-supported-hw is present under an OPP node, but no form of opp_set_supported_hw() has been called, that OPP is ignored by the API and marked as unsupported. Before Commit c928a05e ("drm/msm/adreno: Move speedbin mapping to device table"), an unknown speedbin would result in marking all OPPs as available, but it's better to avoid potentially overclocking the silicon - the GMU will simply refuse to power up the chip. Currently, the Adreno speedbin code does just that (AND returns an invalid error, (int)UINT_MAX). Fix that by defaulting to speedbin 0 (which is conveniently always bound to fuseval == 0). Fixes: c928a05e ("drm/msm/adreno: Move speedbin mapping to device table") Signed-off-by:
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Konrad Dybcio authored
SM6375 comes with a patchlevel=1. Fix the chipid up to reflect that. Fixes: 90b593ce ("drm/msm/adreno: Switch to chip-id for identifying GPU") Signed-off-by:
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Konrad Dybcio authored
Some GPUs - particularly A7xx ones - are really really stubborn and sometimes take a longer-than-expected time to finish unhalting GBIF. Note that this is not caused by the request a few lines above. Poll for the unhalt ack to make sure we're not trying to write bits to an essentially dead GPU that can't receive data on its end of the bus. Failing to do this will result in inexplicable GMU timeouts or worse. This is a rather ugly hack which introduces a whole lot of latency. Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # sm8450 Signed-off-by:
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Konrad Dybcio authored
A740 builds upon the A730 IP, shuffling some values and registers around. More differences will appear when things like BCL are implemented. adreno_is_a740_family is added in preparation for more A7xx GPUs, the logic checks will be valid resulting in smaller diffs. Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # sm8450 Signed-off-by:
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Konrad Dybcio authored
Add support for Adreno 730, also known as GEN7_0_x, found on SM8450. Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # sm8450 Signed-off-by:
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Konrad Dybcio authored
Provide the necessary alternations to mostly support state dumping on A7xx. Newer GPUs will probably require more changes here. Crashdumper and debugbus remain untested. Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # sm8450 Signed-off-by:
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Konrad Dybcio authored
The QMP mailbox expects to be notified of the ACD (Adaptive Clock Distribution) state. Get a handle to the mailbox at probe time and poke it at GMU resume. Since we don't fully support ACD yet, hardcode the message to "val: 0" (state = disabled). Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # sm8450 Signed-off-by:
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Konrad Dybcio authored
A7xx GPUs are - from kernel's POV anyway - basically another generation of A6xx. They build upon the A650/A660_family advancements, skipping some writes (presumably more values are preset correctly on reset), adding some new ones and changing others. One notable difference is the introduction of a second shadow, called BV. To handle this with the current code, allocate it right after the current RPTR shadow. BV handling and .submit are mostly based on Jonathan Marek's work. All A7xx GPUs are assumed to have a GMU. A702 is not an A7xx-class GPU, it's a weird forked A610. Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # sm8450 Signed-off-by:
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Konrad Dybcio authored
Add some missing definitions required for A7 support. This may be substituted with a mesa header sync. Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # sm8450 Signed-off-by:
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Konrad Dybcio authored
Allow A7xx SKUs, such as the A730 GPU found on SM8450 and friends. They use GMU for all things DVFS, just like most A6xx GPUs. Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # sm8450 Signed-off-by:
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Konrad Dybcio authored
When booting the GMU, the QMP mailbox should be pinged about some tunables (e.g. adaptive clock distribution state). To achieve that, a reference to it is necessary. Allow it and require it with A730. Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # sm8450 Acked-by:
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Konrad Dybcio authored
The GMU on the A7xx series is pretty much the same as on the A6xx parts. It's now "smarter", needs a bit less register writes and controls more things (like inter-frame power collapse) mostly internally (instead of us having to write to G[PM]U_[CG]X registers from APPS) The only difference worth mentioning is the now-required DEMET clock, which is strictly required for things like asserting reset lines, not turning it on results in GMU not being fully functional (all OOB requests would fail and HFI would hang after the first submitted OOB). Describe the A730 and A740 GMU. Reviewed-by:
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Rob Herring authored
Make it explicit that child nodes have additional properties and the child node schema is not complete. The complete schemas are applied separately based the compatible strings. Signed-off-by:
Rob Herring <robh@kernel.org> Acked-by:
Conor Dooley <conor.dooley@microchip.com> Patchwork: https://patchwork.freedesktop.org/patch/559387/ Link: https://lore.kernel.org/r/20230925212434.1972368-2-robh@kernel.orgSigned-off-by:
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Rob Herring authored
Just as unevaluatedProperties or additionalProperties are required at the top level of schemas, they should (and will) also be required for child node schemas. That ensures only documented properties are present for any node. Signed-off-by:
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Dmitry Baryshkov authored
Read the downstream port info and set the subconnector type accordingly. Signed-off-by:
Stephen Boyd <swboyd@chromium.org> Patchwork: https://patchwork.freedesktop.org/patch/555531/ Link: https://lore.kernel.org/r/20230903222432.2894093-1-dmitry.baryshkov@linaro.org
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Stephen Boyd authored
Plugging in an Apple dongle without the HDMI cable attached prints out an error message in the kernel logs when nothing is actually wrong. no downstream ports connected This is because the downstream port for the HDMI connector is not connected, so the Apple dongle reports that as a zero sink count device. Cc: Vinod Polimera <quic_vpolimer@quicinc.com> Cc: Kuogee Hsieh <quic_khsieh@quicinc.com> Signed-off-by:
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Stephen Boyd authored
This function is basically a one-liner when you ignore the debug logging. Just inline the function and drop the log to simplify the code. Suggested-by:
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Dmitry Baryshkov authored
As the INTF is fixed at the encoder creation time, we can move the check whether INTF supports tearchck to dpu_encoder_phys_cmd_init(). This function can return an error if INTF doesn't have required feature. Performing this check in dpu_encoder_phys_cmd_tearcheck_config() is less useful, as this function returns void. Signed-off-by:
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Dmitry Baryshkov authored
The dpu_encoder_phys_cmd_te_rd_ptr_irq() function uses neither hw_intf nor hw_pp data, so we can drop the corresponding check. Reviewed-by:
Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by:
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Dmitry Baryshkov authored
Replace the only user of the DPU_INTF_TE feature flag with the direct DPU version comparison. Reviewed-by:
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Dmitry Baryshkov authored
The DPU_INTF_TE bit is set for all INTF blocks on DPU >= 5.0, however only INTF_1 and INTF_2 actually support tearing control (both are INTF_DSI). Rather than trying to limit the DPU_INTF_TE feature bit to those two INTF instances, check for the major && INTF type. Reviewed-by:
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Dmitry Baryshkov authored
Inline the _setup_intf_ops() function, it makes it easier to handle different conditions involving INTF configuration. Reviewed-by:
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