- 27 Oct, 2011 1 commit
-
-
Dave Airlie authored
This reverts commit d3ed7402. Further upstream discussion between Thomas and Marek decided this needed more work and driver specifics. So revert before it goes upstream. Signed-off-by:
Dave Airlie <airlied@redhat.com>
-
- 24 Oct, 2011 1 commit
-
-
git://people.freedesktop.org/~keithp/linuxDave Airlie authored
* 'drm-intel-next' of git://people.freedesktop.org/~keithp/linux: (72 commits) drm/i915/dp: Fix eDP on PCH DP on CPT/PPT drm/i915/dp: Introduce is_cpu_edp() drm/i915: use correct SPD type value drm/i915: fix ILK+ infoframe support drm/i915: add DP test request handling drm/i915: read full receiver capability field during DP hot plug drm/i915/dp: Remove eDP special cases from bandwidth checks drm/i915/dp: Fix the math in intel_dp_link_required drm/i915/panel: Always record the backlight level again (but cleverly) i915: Move i915_read/write out of line drm/i915: remove transcoder PLL mashing from mode_set per specs drm/i915: if transcoder disable fails, say which drm/i915: set watermarks for third pipe on IVB drm/i915: export a CPT mode set verification function drm/i915: fix transcoder PLL select masking drm/i915: fix IVB cursor support drm/i915: fix debug output for 3 pipe configs drm/i915: add PLL sharing support to handle 3 pipes drm/i915: fix PCH PLL assertion check for 3 pipes drm/i915: use transcoder select bits on VGA and HDMI on CPT ...
-
- 23 Oct, 2011 2 commits
-
-
Jakob Bornecrantz authored
Signed-off-by:
Jakob Bornecrantz <jakob@vmware.com> Signed-off-by:
Thomas Hellstrom <thellstrom@vmware.com> Signed-off-by:
-
Jakob Bornecrantz authored
Signed-off-by:
-
- 21 Oct, 2011 19 commits
-
-
Dave Jones authored
abrt files a lot of bug reports when users get GPU lockups, but there's not really enough context to do anything useful with them. Given the lack of GPU context being dumped, this patch removes the stack trace, so that abrt ignores the messages. Signed-off-by:
Dave Jones <davej@redhat.com> Signed-off-by:
-
Adam Jackson authored
According to the gen6 docs, only the DP_A port (on-CPU eDP) still uses the old IBX bit shift for the link training pattern setup bits. Signed-off-by:
Adam Jackson <ajax@redhat.com> Reviewed-by:
Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by:
Keith Packard <keithp@keithp.com>
-
Adam Jackson authored
The obvious counterpart to is_pch_edp(). Convert existing instances of the idiom to the new routine. Signed-off-by:
-
Jesse Barnes authored
SPD frames are actually type 0x83, not just 0x3. Signed-off-by:
-
Jesse Barnes authored
Misc fixes based on tests with an infoframe analyzer: - checksum *does* include header bytes - DIP enable & AVI infoframe are tied together in hw, so disable both and make sure AVI frames are enabled first - use every vsync flag for SPD frames to avoid reserved value in frequency field when enabling both AVI & SPD Fixes https://bugs.freedesktop.org/show_bug.cgi?id=40281. Signed-off-by: -
Jesse Barnes authored
DPCD 1.1+ adds some automated test infrastructure support. Add support for reading the IRQ source and jumping to a test handling routine if needed. Subsequent patches will handle particular tests; this patch just ACKs any requested tests by default. Signed-off-by:
-
Jesse Barnes authored
Read link status first, followed by the full DPCD receiver cap field rather than just the first 8 bytes. Signed-off-by:
-
Adam Jackson authored
These were just working around the math being wrong. Signed-off-by:
-
Adam Jackson authored
The previous code was confused about units, which is pretty reasonable given that the units themselves are confusing. Signed-off-by:
-
Takashi Iwai authored
The commit 47356eb6 introduced a mechanism to record the backlight level only at disabling time, but it also introduced a regression. Since intel_lvds_enable() may be called without disabling (e.g. intel_lvds_commit() calls it unconditionally), the backlight gets back to the last recorded value. For example, this happens when you dim the backlight, close the lid and open the lid, then the backlight suddenly goes to the brightest. This patch fixes the bug by recording the backlight level always when changed via intel_panel_set_backlight(). And, intel_panel_{enable|disable}_backlight() call the internal function not to update the recorded level wrongly. Cc: <stable@kernel.org> Signed-off-by:
Takashi Iwai <tiwai@suse.de> Reviewed-by:
-
Andi Kleen authored
With the tracing code in there they are far too big to inline. .text savings compared to a non force inline kernel: i915_restore_display 4393 12036 +7643 i915_save_display 4295 11459 +7164 i915_handle_error 2979 6666 +3687 i915_driver_irq_handler 2923 5086 +2163 i915_ringbuffer_info 458 1661 +1203 i915_save_vga - 1200 +1200 i915_driver_irq_uninstall 453 1624 +1171 i915_driver_irq_postinstall 913 2078 +1165 ironlake_enable_drps 719 1872 +1153 i915_restore_vga - 1142 +1142 intel_display_capture_error_state 784 2030 +1246 intel_init_emon 719 2016 +1297 and more ... [AK: these are older numbers, with the new SNB forcewake checks it will be even worse] Signed-off-by:
Andi Kleen <ak@linux.intel.com> Reviewed-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Acked-by:
Ben Widawsky <ben@bwidawsk.net> Signed-off-by:
-
Jesse Barnes authored
Belongs in PCH enable instead. The duplication is worrying and the specs explicitly list transcoder select *after* actual PLL enable, which doesn't occur until later. Signed-off-by:
Eugeni Dodonov <eugeni.dodonov@intel.com> Reviewed-By:
-
Jesse Barnes authored
Just some extra debug output. Signed-off-by:
-
Jesse Barnes authored
The watermark reg for the third pipe is in an unusual offset; add support for it and set watermarks for 3 pipe configs. Signed-off-by:
-
Jesse Barnes authored
At the point where we check, we can't do much about the failure, but it can aid debugging. Note that the auto-train override bit will be reset as part of normal mode setting with this patch if a pipe ever does get stuck, but that's consistent with the workaround for CPT provided by the hardware team. This patch helped catch the fact that the pipe wasn't running in the !composite sync FDI case on my IVB SDV, so has already shown to be useful. Signed-off-by:
-
Jesse Barnes authored
Transcoder A will always use PLL A and transcoder B will use PLL B. But transcoder C could use either, so always mask the select bits off before or'ing in a new value. Reported-by:
-
Jesse Barnes authored
The cursor regs have moved around, add the offsets and new macros for getting at them. Signed-off-by:
-
Jesse Barnes authored
We can have more than just A and B these days. Signed-off-by:
-
Jesse Barnes authored
Add two new fields to the intel_crtc struct for 3 pipe support: no_pll and use_pll_a. The no_pll field is only set on the 3rd pipe to indicate that it doesn't have a PLL of its own and so shouldn't try to write the main PLL regs. The use_pll_a field controls which PLL pipe 3 will share, A or B. The core code will try to share PLLs with whichever pipe has the same timings, rejecting the mode set if none is found. This means that pipe 3 must always be set after one of the other pipes has been configured with real PLL settings. Signed-off-by:
-
- 20 Oct, 2011 17 commits
-
-
Jesse Barnes authored
Add a couple of checks now that we're using the 3rd transcoder: 1) make sure the transcoder PLL enable bit is set for the transcoder in question 2) when checking actual PLL enable, use the selected PLL number rather than the transcoder number (they could be different now) Signed-off-by: -
Jesse Barnes authored
Required for 3 pipe functionality. Signed-off-by:
-
Jesse Barnes authored
Just a cleanup to make the mode_set function more manageable. Signed-off-by:
-
Jesse Barnes authored
Well almost anyway. IVB has 3 planes, pipes, transcoders, and FDI interfaces, but only 2 pipe PLLs. So two of the pipes must use the same pipe timings (e.g. 2 DP plus one other, or two HDMI with the same mode and one other, etc.). Signed-off-by:
-
Jesse Barnes authored
Add a macro for accessing the two pipe PLLs and add a check to make sure we don't access a non-existent one in the enable/disable functions. Signed-off-by:
-
Jesse Barnes authored
It's needed for 3 pipe support as well as just regular functionality (e.g. DisplayPort). Signed-off-by:
-
Jesse Barnes authored
v2 by danvet: Use a new flag to flush the render target cache on gen6+ (hw reuses the old write flush bit), as suggested by Ben Widawsdy. Signed-off-by:
Kenneth Graunke <kenneth@whitecape.org> [danvet: this seems to fix cairo-perf-trace hangs on my snb] Signed-Off-by:
-
Kenneth Graunke authored
"STALL_AT_SCOREBOARD" is much clearer than "STALL_EN" now that there are several different kinds of stalls. Also, "INSTRUCTION_CACHE_INVALIDATE" is a lot easier to understand at a glance than the terse "IS_FLUSH." Signed-off-by:
-
Kenneth Graunke authored
Not all PIPE_CONTROLs have a length of 2, so remove it from the #define and make each invocation specify the desired length. Signed-off-by:
-
Ben Widawsky authored
Add the addresses and definitions I care about for Panel Self Refresh, as documented in the eDP spec. I'm sending these out before some other patches because this should be a fairly simple one to get upstream and not require too much fuss (where the others may have some fuss). This file is a mess with white spacing. I tried to stay consistent with the surrounding code. v2: had some silly mistakes in v1 which Keith caught Cc: Dave Airlie <airlied@redhat.com> Cc: Keith Packard <keithp@keithp.com> Signed-off-by:
-
Ben Widawsky authored
Idle the GPU before doing any unmaps. We know if VT-d is in use through an exported variable from iommu code. This should avoid a known HW issue. Signed-off-by:
-
Ben Widawsky authored
[Description from: Daniel Vetter] I've just discussed this quickly with Chris on irc and it's probably best to just kill the list_empty early bailout. gpu_idle isn't a fastpath, so who cares. One candidate where we emit commands to the ring without adding anything onto these lists is e.g. pageflip. There are probably more. Signed-off-by:
-
David Woodhouse authored
We really don't want this to work in the general case; device drivers *shouldn't* care whether they are behind an IOMMU or not. But the integrated graphics is a special case, because the IOMMU and the GTT are all kind of smashed into one and generally horrifically buggy, so it's reasonable for the graphics driver to want to know when the IOMMU is active for the graphics hardware. Signed-off-by:
David Woodhouse <David.Woodhouse@intel.com> Signed-off-by:
-
David Woodhouse authored
To work around a hardware issue, we have to submit IOTLB flushes while the graphics engine is idle. The graphics driver will (we hope) go to great lengths to ensure that it gets that right on the affected chipset(s)... so let's not screw it over by deferring the unmap and doing it later. That wouldn't be very helpful. Signed-off-by:
-
Daniel Vetter authored
Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
-
Daniel Vetter authored
For the !HAVE_ATOMIC_IOMAP case the stub functions did not call pagefault_disable/_enable. The i915 driver relies on the map actually being atomic, otherwise it can deadlock with it's own pagefault handler in the gtt pwrite fastpath. This is exercised by gem_mmap_gtt from the intel-gpu-toosl gem testsuite. v2: Chris Wilson noted the lack of an include. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=38115 Cc: stable@kernel.org Signed-off-by:
-
Chris Wilson authored
We currently only round up the userspace size to the next page. We assume that userspace hasn't made a mistake and requested a zero-length gem object and all through our internal code we then presume that every object is backed by at least a single page. Fix that oversight and report EINVAL back to userspace if they try to create a zero length object. [danvet: This fixes tests/gem_bad_length] Signed-off-by:
-
