- 15 Dec, 2015 2 commits
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Dave Airlie authored
Merge branch 'exynos-drm-next' of git://git.kernel.org:/pub/scm/linux/kernel/git/daeinki/drm-exynos into drm-next - Support runtime pm . In case of most ARM SoC, each IP has each power domain which should be controlled by each IP driver using runtime pm interface. So this patch series makes each IP driver to control its own power domain when drm dpms is requested. - Support of_graph based dt binding for DP panel. . This patch series adds of_graph based dt binding for DP panel. And also it keeps backward compatibility. This includes dt binding patch so I got Acked-by from Krzysztof Kozlowski who is a Exynos SoC maintainer and from Rob Herring who is a device tree maintainer. - Cleanup for Exynos DRM IPP enhancement. . This patch series is a first step for enhancing existing IPP framework which will integrate existing IPP functions with DRM KMS part so that these can be transparent to userspace. For other portion of the patch series, we will have more times for the review.] * 'exynos-drm-next' of git://git.kernel.org:/pub/scm/linux/kernel/git/daeinki/drm-exynos: (29 commits) drm/exynos: gem: remove old unused prototypes drm/exynos: fimd: fix dma burst size setting for small plane size drm/exynos: fix clipping when scaling is enabled drm/exynos: mixer: use ratio precalculated in exynos_state drm/exynos: add generic check for plane state drm/exynos: introduce exynos_drm_plane_config structure drm/exynos: mixer: enable video overlay plane only when VP is available drm/exynos: mixer: use crtc->state->adjusted_mode instead of crtc->mode drm/exynos: introduce exynos_drm_plane_state structure drm/exynos: move dma_addr attribute from exynos plane to exynos fb drm/exynos: exynos7-decon: remove excessive check drm/exynos: rotator: convert to common clock framework drm/exynos: gsc: add device tree support and remove usage of static mappings drm/exynos: gsc: fix wrong pm_runtime state drm/exynos: gsc: prepare and unprepare gsc clock ARM: dts: Use OF graph for DP to panel connection in exynos5800-peach-pi dt-bindings: exynos-dp: update ports node binding for panel drm/exynos: dp: add of_graph dt binding support for panel drm/exynos: decon: remove unused variables drm/exynos: dsi: modify a error type when getting a node failed ...
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git://anongit.freedesktop.org/drm-intelDave Airlie authored
Last (very likely at least) drm-misc pull for 4.5. 3 big things: - piles of docs for kms vtables. - drm.debug dmesg output prettification from Ville (i915 parts are for 4.6 I think) - connector mode probing/validating/merging cleanup from Ville. [airlied : fix drm_encoder_init conflict.] * tag 'topic/drm-misc-2015-12-14' of git://anongit.freedesktop.org/drm-intel: (43 commits) drm: modes: Revert cc344980 "replace simple_strtoul by kstrtouint" drm: Expand the drm_helper_probe_single_connector_modes() docs drm: Allow override_edid to override the firmware EDID drm/sti: Drop bogus drm_mode_sort() call drm: Drop drm_helper_probe_single_connector_modes_nomerge() drm: Only merge mode type bits between new probed modes drm: Flatten drm_mode_connector_list_update() a bit drm: Rename MODE_UNVERIFIED to MODE_STALE drm: Don't overwrite UNVERFIED mode status to OK drm: Add plane->name and use it in debug prints drm: Add crtc->name and use it in debug messages drm: Use driver specified encoder name drm: Pass 'name' to drm_encoder_init() drm: Pass 'name' to drm_universal_plane_init() drm: Pass 'name' to drm_crtc_init_with_planes() drm: Documentation style guide drm: Document drm_encoder/crtc_helper_funcs drm: Move drm_display_mode an related docs into kerneldoc drm/atomic-helper: Mention the new system/resume helpers the docs drm: Document drm_connector_helper_funcs ...
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- 14 Dec, 2015 30 commits
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git://people.freedesktop.org/~robclark/linuxDave Airlie authored
Main thing this time around is DSI support for msm8960/apq8064, which should be helpful for getting an upstream kernel working on nexus7/nexus4/etc. * 'msm-next' of git://people.freedesktop.org/~robclark/linux: (29 commits) drm/msm/mdp: fix a problematic usage of WARN_ON() drm/msm/dsi: Added missing mutex_unlock drm/msm: ratelimit error irq msgs drm/msm: Use unlocked gem unreferencing drm/msm: trivial whitespace fix dt-bindings: msm/dsi: Add DSIv2 documentation dt-bindings: msm/dsi: Fix the order in which clocks are listed drm/msm/dsi: Enable MMSS SPFB port via syscon drm/msm/dsi: Don't use iommu for command TX buffer for DSIv2 drm/msm/dsi: Add dsi_cfg for APQ8064 drm/msm/dsi: Set up link clocks for DSIv2 drm/msm/dsi: Parse bus clocks from a list drm/msm/dsi: Delay dsi_clk_init drm/msm/dsi: Use a better way to figure out DSI version drm/msm/dsi: Add DSI PLL for 28nm 8960 PHY drm/msm/dsi: Add support for 28nm PHY on 8960 drm/msm/dsi: Don't get byte/pixel source clocks from DT drm/msm/mdp4: Initialize DSI encoders drm/msm/mdp4: Call custom round_pixclk helper only if the encoder type is TMDS drm/msm/dsi: Add a mdp4 encoder for DSI ...
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Geliang Tang authored
WARN_ON() takes a condition rather than a format string. This patch converted WARN_ON() to WARN() instead. Signed-off-by:
Geliang Tang <geliangtang@163.com> Signed-off-by:
Rob Clark <robdclark@gmail.com>
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saurabh authored
in case of failed to get iova, function was returning without releasing the mutex. Added it. Signed-off-by:
Saurabh Sengar <saurabh.truth@gmail.com> Signed-off-by:
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Rob Clark authored
When things go bad and don't recover, we can be getting an err irq every vblank. Signed-off-by: -
Daniel Vetter authored
For drm_gem_object_unreference callers are required to hold dev->struct_mutex, which these paths don't. Enforcing this requirement has become a bit more strict with commit ef4c6270 Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Thu Oct 15 09:36:25 2015 +0200 drm/gem: Check locking in drm_gem_object_unreference Cc: Rob Clark <robdclark@gmail.com> Signed-off-by:
Daniel Vetter <daniel.vetter@intel.com> Signed-off-by:
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Rob Clark authored
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Archit Taneja authored
Add additional property info needed for DSIv2 DT. Cc: devicetree@vger.kernel.org Cc: Rob Herring <robh@kernel.org> Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Archit Taneja <architt@codeaurora.org> Signed-off-by:
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Archit Taneja authored
List the clocks in the order that's used in DT. We don't have mdp/dsi DT nodes for any SoC in upstream yet, but we align with the order we intend to use. Cc: devicetree@vger.kernel.org Cc: Rob Herring <robh@kernel.org> Acked-by:
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Archit Taneja authored
For DSIv2 to work, we need to enable MMSS_AHB_ARB_MASTER_PORT in MMSS_SFPB. We enable the required bitfield by retrieving MMSS_SFPB regmap pointer via syscon. Signed-off-by:
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Archit Taneja authored
We currently use iommu allocated DMA buffers for sending DSI commands. DSIv2 doesn't have a port connected to the MDP iommu. Therefore, it can't use iommu allocated buffers to fetch DSI commands. Use a regular contiguous DMA buffer if we are DSIv2. Signed-off-by:
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Archit Taneja authored
Add a dsi_cfg entry for APQ8064. Since this is the first DSIv2 chip to be supported, add a list of bus clocks that are required by the DSIv2 block. Signed-off-by:
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Archit Taneja authored
DSIv2 (DSI on older A family chips) has slightly different link clock requirements. First, we have an extra clock called src_clk (with a dedicated RCG). This is required by the DSI controller to process the pixel data coming from MDP. It needs to be set at the rate "pclk * bytes_per_pixel". We also need to explicitly configure esc_clk. On DSI6G chips, we don't need to set a rate to esc_clk because its RCG is always sourced from crystal clock (19.2 Mhz in all cases), which is within the escape clock frequency range in the mipi DSI spec. For chips with DSIv2, the crystal clock rate may not be within the required range (27Mhz on APQ8064). Therefore, we derive it from the DSI byte clock. We calculate an esc_clck rate that is within the mipi spec and also divisible by the byte clock rate. When setting rate and enabling the link clocks, we make sure that byte_clk is configured before esc_clk, and src_clk before pixel_clk. We create two different link_enable funcs for DSI6G and DSIv2 since the sequences are different. We also obtain two extra source clocks (dsi_src_clk and esc_src_clk) and set their parent to the clocks provided by DSI PLL. Signed-off-by:
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Archit Taneja authored
DSI bus clocks seem to vary between different DSI host versions, and the SOC to which they belong. Even the enable/disable sequence varies. Provide a list of bus clock names in dsi_cfg. The driver will use this to retrieve the clocks, and enable/disable them. Add bus clock lists for DSI6G, and DSI for MSM8916(this is DSI6G too, but there is no MMSS_CC specific clock since there is no MMSS clock controller on 8916). Signed-off-by:
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Archit Taneja authored
Initialize clocks only after we get the DSI host version. This will allow us to get clocks using a pre-defined list based on the DSI major/minor version of the host. This is required since clock requirements of different major DSI revisions(v2 vs 6g) aren't the same. Modify dsi_get_version to get the interface clock, and then put it after it is used. Signed-off-by:
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Archit Taneja authored
The current version checking mechanism works fine for DSI6G blocks. It doesn't work so well for older generation DSIv2 blocks. The initial read of REG_DSI_6G_HW_VERSION(offset 0x0) would result in a read of REG_DSI_CTRL for DSIv2. This register won't necessarily be 0 on DSIv2. It can be non zero if DSI was previously initialized by the bootloader. Instead of reading offset 0x0, we now read offset 0x1f0. For DSIv2, this register is DSI_VERSION, and is bound to be non-zero. On DSI6G, this register(offset 0x1f0) is SCRATCH_REGISTER_0, which no one ever seems to touch, and from all register dumps I'vc seen, holds 0 all the time. Modify dsi_get_version to read REG_DSI_VERSION to determine whether we are DSI6G or DSIv2. Signed-off-by:
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Archit Taneja authored
Add DSI PLL common clock framework clocks for 8960 PHY. The PLL here is different from the ones found in B family msm chips. As before, the DSI provides two clocks to the outside world. dsixpll and dsixpllbyte (x = 1, 2). dsixpll is a regular clock divider, but dsixpllbyte is modelled as a custom clock divider. dsixpllbyte is the starting point of the PLL configuration. It is the one that sets up the VCO clock rate. We need the VCO clock rate in the form: F * byteclk, where F is a multiplication factor that varies on the byte clock the DSI driver is trying to set. We use the custom clk_ops for dsixpllbyte to ensure that the parent (VCO) is set at this rate. An additional divider (POSTDIV1) generates the bitclk. Since bit clock can be derived from byteclock, we calculate it internally, and don't expose it as a clock. Cc: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by:
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Archit Taneja authored
DSI PHY on MSM8960 and APQ8064 is a 28nm PHY that's different from the supported 28nm LP PHY found in newer chips. Add support for the new PHY. Signed-off-by:
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Archit Taneja authored
We retrieve the byte and pixel source clocks (RCG clocks) in the dsi driver via DT. These are needed so that we can re-parent these source clocks if we want to drive it using a different DSI PLL. We shouldn't get these via DT because they aren't clocks that directly serve as inputs to the dsi host. Fortunately, there is a static parent-child link between the byte_clk_src/pixel_clk_src and byte_clk/pixel_clk clocks. So, we can retrieve the source clocks via clk_get_parent. Do this instead of retrieving via DT. Cc: Rob Herring <robh@kernel.org> Cc: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by:
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Archit Taneja authored
Create DSI encoders during modeset_init. The 2 encoders should ideally be one command mode and one video mode DSI encoder respectively, but we don't support command mode yet. We just create 2 of the same because the dsi driver expects it, we end up using only the first one. Signed-off-by:
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Archit Taneja authored
The mdp_kms round_pixclk op creates problems when we have more interfaces in use. It calls the DTV encoder's helper by default. Check on encoder type and call the corresponding encoder's func meant for rounding pixel clock. DSI and LVDS don't require rounding, so just return rate in their case. Signed-off-by:
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Vinay Simha BN authored
Create an mdp4 incoder for DSI. Only DSI video mode is supported as of now. Signed-off-by:
Vinay Simha BN <vinaysimha@inforcecomputing.com> Signed-off-by:
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Archit Taneja authored
Currently, the driver defers if it doesn't find a drm_panel. This forces us to have a drm_panel, if not, the driver isn't usable. Make the lcdc encoder initialization independent of the availability of the drm panel. We only check if there is a panel node specified in DT. If it isn't, then we don't initialize the encoder at all. The panel node is passed to the lcdc encoder and lvds connector drivers. The connector driver takes the responsibility to retrieve the drm_panel from the panel node, and update the status on whether the panel is connected or not. This makes the panel usable even if the drm_panel driver is inserted as a module later on. Signed-off-by:
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Archit Taneja authored
modeset_init() for mdp4 isn't very flexible. That makes it hard to add more interfaces. Split out the encoder/connector creation code in modeset_init into a separate function. This is similar to what's done in modeset_init for mdp5. Signed-off-by:
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Archit Taneja authored
Remove CONFIG_OF checks in adreno_device.c. The downstream bus scaling stuff is included only when CONFIG_OF is not set. So, remove that too. Signed-off-by:
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Archit Taneja authored
We now only care about kernels that support DT. Remote the non-DT stuff. While we're at it, use of_device_get_match_data to retrieve match data. Signed-off-by:
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Archit Taneja authored
We don't intend to use downstream non-DT kernels anymore, so remove CONFIG_OF checks. Update the TODO comment so that we don't forget about max_clk setting for non APQ8064 chips having MDP4. Signed-off-by:
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Archit Taneja authored
Update DT bindings for mdp. We now have a more uniform and future-proof set of compatible strings. MDP5 bindings were missing. Add those and update details on the clock-names properties. Signed-off-by:
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Archit Taneja authored
Create distinct compatible strings for mdp4 and mdp5. Keep "qcom,mdss_mdp" as is to support downstream kernels. Signed-off-by:
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Archit Taneja authored
Support for non-DT kernels was mainly to use v3.4 downstream kernels. This is no longer a priority now as we have reasonable support upstream. Remove CONFIG_OF from the top level msm_drv.c file. While we're at it, clean up the data matching process using of_device_get_match_data. Signed-off-by:
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Archit Taneja authored
MDP5 has line count and frame count registers for each interface. Enable these counters and use them to implement the get_vblank_timestamp drm driver op. The line counter starts with the value 1 at the beginning of the VSYNC pulse and ends with value VTOTAL at the end of VFP. This value is used to determine whether we're in blanking period or not, and an adjusted value of this counter is used to get vpos as expected by get_scanout_position. Since there is no way to calculate hpos, we always set it to 0. Signed-off-by:
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- 13 Dec, 2015 8 commits
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Marek Szyprowski authored
This patch removes old, unused function prototypes from exynos_drm_gem.h. Signed-off-by:
Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by:
Inki Dae <inki.dae@samsung.com>
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Marek Szyprowski authored
This patch fixes trashed display of buffers cropped to very small width. Even if DMA is unstable and causes tearing when changing the burst size, it is still better than displaying a garbage. Signed-off-by:
Daniel Stone <daniels@collabora.com> Signed-off-by:
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Marek Szyprowski authored
This patch fixes calculation of src x/y offset for negative crtc x/y values when scaling is enabled. This fixes possible IOMMU fault when scaling is enabled. Signed-off-by:
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Marek Szyprowski authored
Common plane code already calculates and checks for supported scalling modes, so additional code in mixer driver can be now removed. Signed-off-by:
Gustavo Padovan <gustavo.padovan@collabora.co.uk> Signed-off-by:
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Marek Szyprowski authored
This patch adds generic check for plane state - display area dimensions, so drivers can always assume that they get valid plane state to set. Signed-off-by:
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Marek Szyprowski authored
This patch adds common structure for keeping plane configuration and capabilities data. This patch is inspired by similar code developed by Tobias Jakobi. Changelog v2: - fix vidi_win_types(i) call. vidi_win_types is not a function. Signed-off-by:
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Marek Szyprowski authored
Video overlay plane should be registered only when suitable hardware sub-block (Video Processor) is available. Signed-off-by:
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Marek Szyprowski authored
This patch replaces usage of crtc->mode with crtc->state->adjusted_mode like it is already done in common plane code. Signed-off-by:
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