- 01 Apr, 2022 18 commits
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Philip Yang authored
To fix two issues with unlocked update fence: 1. vm->last_unlocked store the latest fence without taking refcount. 2. amdgpu_vm_bo_update_mapping returns old fence, not the latest fence. Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Haowen Bai authored
The pointer edid_buf is dereferencing pointer edid before edid is being null checked. Fix this by assigning edid->raw_edid to edid_buf only if edid is not NULL, otherwise just NULL. Signed-off-by:
Haowen Bai <baihaowen@meizu.com> Signed-off-by:
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Roman Li authored
[Why] On resume we do link detection for all non-MST connectors. MST is handled separately. However the condition for telling if connector is on mst branch is not enough for mst hub case. Link detection for mst branch link leads to mst topology reset. That causes assert in dc_link_allocate_mst_payload() [How] Use link type as indicator for mst link. Reviewed-by:
Wayne Lin <Wayne.Lin@amd.com> Acked-by:
Alex Hung <alex.hung@amd.com> Signed-off-by:
Roman Li <Roman.Li@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Aric Cyr authored
- [FW Promotion] Release 0.0.110.0 - Revert FEC check in validation - Update LTTPR UHBR link rate support struct - Add support for USBC connector - Add work around for AUX failure on wake - Clear optc false state when disable otg - Enable power gating before init_pipes - Remove redundant dsc power gating from init_hw - Power down hardware if timer not trigger - Correct Slice reset calculation - Enable 3-plane MPO for DCN31 - Set fec register init value - Remove SW w/a for HDCP 1.4 1A-07 failure based on ECO fix - Create underflow interrupt IRQ type Acked-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
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Anthony Koo authored
- Revert save/restore PANEL_PWRSEQ_REF_DIV2 and other psr phy optimizations Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Tested-by:
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Martin Leung authored
why and how: causes failure on install on certain machines Reviewed-by:
George Shen <George.Shen@amd.com> Acked-by:
Martin Leung <Martin.Leung@amd.com> Tested-by:
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Michael Strauss authored
[WHY] Update field order to match DP2.0 spec SCR Reviewed-by:
Michael Strauss <michael.strauss@amd.com> Tested-by:
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Samson Tam authored
[Why] Add support for CONNECTOR_ID_USBC Reviewed-by:
Alvin Lee <Alvin.Lee2@amd.com> Acked-by:
Samson Tam <Samson.Tam@amd.com> Tested-by:
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Jimmy Kizito authored
[Why] When waking from low-power states, a DP sink may remain unresponsive to AUX transactions. [How] Try to toggle DPCD SET_POWER register repeatedly (up to a maximum timeout value) until DP sink becomes responsive. Reviewed-by:
Mustapha Ghaddar <Mustapha.Ghaddar@amd.com> Acked-by:
Jimmy Kizito <Jimmy.Kizito@amd.com> Tested-by:
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Charlene Liu authored
[why] when disable optc, need to clear the underflow status as well. Reviewed-by:
Chris Park <Chris.Park@amd.com> Acked-by:
Charlene Liu <Charlene.Liu@amd.com> Tested-by:
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Roman Li authored
[Why] In init_hw() we call init_pipes() before enabling power gating. init_pipes() tries to power gate dsc but it may fail because required force-ons are not released yet. As a result with dsc config the following errors observed on resume: "REG_WAIT timeout 1us * 1000 tries - dcn20_dsc_pg_control" "REG_WAIT timeout 1us * 1000 tries - dcn20_dpp_pg_control" "REG_WAIT timeout 1us * 1000 tries - dcn20_hubp_pg_control" [How] Move enable_power_gating_plane() before init_pipes() in init_hw() Reviewed-by:
Eric Yang <Eric.Yang2@amd.com> Acked-by:
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Roman Li authored
[Why] DSC Power down code has been moved from dcn31_init_hw into init_pipes() Need to remove it from dcn10_init_hw() as well to avoid duplicated action on dcn1.x/2.x [How] Remove DSC power down code from dcn10_init_hw() Fixes: 8fa6f4c5 ("drm/amd/display: fixed the DSC power off sequence during Driver PnP") Reviewed-by:
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Paul Hsieh authored
[WHY] In headless systems, if SetMode/Power down timer is not called, hardware will not be powered down causing HW/SW discrepancies. Powering down hardware on SetPowerState to D3 will ensure SW/HW state is accurate. [HOW] If PowerDownThread timer is not trigger but OS call SetPowerState to D3, power down hardware. Reviewed-by:
Paul Hsieh <paul.hsieh@amd.com> Tested-by:
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Chris Park authored
[Why] Once DSC slice cannot fit pixel clock, we incorrectly reset min slices to 0 and allow max slice to operate, even when max slice itself cannot fit the pixel clock properly. [How] Change the sequence such that we correctly determine DSC is not possible when both min slices and max slices cannot fit pixel clock per slice. Reviewed-by:
Wenjing Liu <Wenjing.Liu@amd.com> Acked-by:
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Krunoslav Kovac authored
[WHY&HOW] It can be enabled by users, but proper way is to report max_slave_planes in DC caps for each ASIC. Some structures use hardcoded max_plane=2, this is also addressed here. Reviewed-by:
Nevenko Stupar <Nevenko.Stupar@amd.com> Reviewed-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Tested-by:
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Jingwen Zhu authored
[Why] We don't include this eDP FEC init on fastboot. [How] Set the fec to init value when stopping driver &get the fec register value to check should enable FEC. Co-authored-by:
Jingwen Zhu <Jingwen.Zhu@amd.com> Reviewed-by:
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Oliver Logush authored
[why] W/a no longer needed Reviewed-by:
Oliver Logush <oliver.logush@amd.com> Tested-by:
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Angus Wang authored
[WHY] We want another entry in IRQ type that can be used to help find the underflow interrupt source. [HOW] Added another mapping in IRQ type enum. Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Angus Wang <Angus.Wang@amd.com> Tested-by:
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- 28 Mar, 2022 12 commits
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Mohammad Zafar Ziya authored
RAS error query support addition for JPEG 2.6 V2: removed unused options and corrected comment format. Moved register definition to header file. V3: poison query status check added. Removed the error query support V4: Return statement refactored. Signed-off-by:
Mohammad Zafar Ziya <Mohammadzafar.ziya@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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Mohammad Zafar Ziya authored
RAS error query support addition for VCN 2.6 V2: removed unused option and corrected comment format Moved the register definition under header file V3: poison query status check added. Removed error query interface V4: MMSCH poison check option removed, return true/false refactored. Signed-off-by:
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Mohammad Zafar Ziya authored
Adding vcn and jpeg ver 2.6 ras register definition Signed-off-by:
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Mohammad Zafar Ziya authored
Ras support addition for JPEG block V2: removed default callback Signed-off-by:
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Mohammad Zafar Ziya authored
VCN block ras feature support addition V2: default ras callback removed Signed-off-by:
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Mohammad Zafar Ziya authored
Add vcn and jpeg ras support options V2: vcn and jpeg ras flag enabled for aldebaran asic only V3: vcn and jpeg ras flag disabled for error counter query Generic poison query interface added VCN and JPEG ras enabled based on IP version check V4: vcn and jpeg ras flag moved under ecc flag for dGPU Signed-off-by:
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tiancyin authored
Some video card has more than one vcn instance, passing 0 to vcn_v3_0_pause_dpg_mode is incorrect. Error msg: Register(1) [mmUVD_POWER_STATUS] failed to reach value 0x00000001 != 0x00000002 Reviewed-by:
James Zhu <James.Zhu@amd.com> Signed-off-by:
tiancyin <tianci.yin@amd.com> Signed-off-by:
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Sean Paul authored
ATOMIC and DRIVER log categories do not typically contain per-frame log messages. This patch re-classifies some messages in amd to chattier categories to keep ATOMIC/DRIVER quiet. Acked-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Sean Paul <seanpaul@chromium.org> Signed-off-by:
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Lijo Lazar authored
Instead of ASIC type, use GC and MP1 IP versions for feature support checks. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Kevin Wang <kevinyang.wang@amd.com> Signed-off-by:
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Boyuan Zhang authored
For VCN FW to detect ASIC type, in order to use different mailbox registers. V2: simplify codes and fix format issue. Signed-off-by:
Boyuan Zhang <boyuan.zhang@amd.com> Acked-by Huang Rui <ray.huang@amd.com> Signed-off-by:
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Darren Powell authored
(v1) - implement emit_clk_levels for vega10, based on print_clk_levels, but using sysfs_emit rather than sprintf - modify local int vars to use uint32_t to match arg type of called functions - add return of error codes - refactor OD_XXX cases to return early with -EOPNOTSUPP if !(hwmgr->od_enabled) Signed-off-by:Darren Powell <darren.powell@amd.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Darren Powell authored
Extend commit 7f36948c92b2 ("amdgpu/pm: Implement new API function "emit" that accepts buffer base and write offset") Add new hwmgr API function "emit_clock_levels" - add member emit_clock_levels to pp_hwmgr_func - Implemented pp_dpm_emit_clock_levels - add pp_dpm_emit_clock_levels to pp_dpm_funcs Signed-off-by:
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- 25 Mar, 2022 10 commits
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Christian König authored
Better to leave the decision when to flush the VM changes in the TLB to the VM code. Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Christian König authored
Instead of hand rolling the table_freed parameter. v2: add some changes suggested by Philip Signed-off-by:
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Christian König authored
Instead of trying to figure out if a TLB flush is necessary or not use the information provided by the VM subsystem now. Signed-off-by:
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Christian König authored
Instead of tracking the VM updates through the dependencies just use a sequence counter for page table updates which indicates the need to flush the TLB. This reduces the need to flush the TLB drastically. v2: squash in NULL check fix (Christian) Signed-off-by:
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Christian König authored
Store the 64bit sequence directly. Makes it simpler to use and saves a bit of fence reference counting overhead. Signed-off-by:
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Christian König authored
Separate the VM page table backend operations from the state machine since the amdgpu_vm.c file is becoming to complex. The allocating, freeing and updating page tables and page directories can easily be moved into a separate file. While at it cleanup everything checkpatch.pl reported and rename the functions a bit to make more clear that they belong together. Signed-off-by:
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Christian König authored
Move the page tables to the idle list after updating the PDEs. We have gone back and forth with that a couple of times because of problems with the inter PD dependencies, but it should work now that we have the state handling cleanly separated. Signed-off-by:
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Melissa Wen authored
Moves FPU-related structs and dcn316_update_bw_bounding_box from dcn316 driver to dml/dcn31 that centralize FPU operations for DCN 3.1x Signed-off-by:
Melissa Wen <mwen@igalia.com> Reviewed-by:
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Melissa Wen authored
Moves related structs and dcn315_update_bw_bounding_box from dcn315 driver code to dml/dcn31_fpu that centralizes FPU code for DCN 3.1x. Signed-off-by:
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Melissa Wen authored
Creates FPU files in dml/dcn31 folder to centralize FPU operations from 3.1x drivers and moves all FPU-associated code from dcn31 driver to there. It includes the struct _vcs_dpi_ip_params_st and _vcs_dpi_soc_bounding_box_st and functions: - dcn31_calculate_wm_and_dlg_fp() - dcn31_update_bw_bounding_box() adding dc_assert_fp_enabled to them and drop DC_FP_START/END inside functions that was moved to dml folder, as required. Signed-off-by:
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