- 08 Nov, 2018 1 commit
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Chris Wilson authored
Ensure that the writes into the context image are completed prior to the register mmio to trigger execution. Although previously we were assured by the SDM that all writes are flushed before an uncached memory transaction (our mmio write to submit the context to HW for execution), we have empirical evidence to believe that this is not actually the case. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108656 References: https://bugs.freedesktop.org/show_bug.cgi?id=108315 References: https://bugs.freedesktop.org/show_bug.cgi?id=106887Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Acked-by:
Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181108081740.25615-1-chris@chris-wilson.co.uk Cc: stable@vger.kernel.org
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- 07 Nov, 2018 11 commits
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Imre Deak authored
To enable DC5/6 power well 2 has to be disabled as for previous platforms, so fix things up. Bspec: 4234 Fixes: 67ca07e7 ("drm/i915/icl: Add power well support") Cc: Animesh Manna <animesh.manna@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
Imre Deak <imre.deak@intel.com> Reviewed-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181102182200.17219-1-imre.deak@intel.com
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Lyude Paul authored
Unfortunately, it seems that the HPD IRQ storm problem from the early days of Intel GPUs was never entirely solved, only mostly. Within the last couple of days, I got a bug report from one of our customers who had been having issues with their machine suddenly booting up very slowly after having updated. The amount of time it took to boot went from around 30 seconds, to over 6 minutes consistently. After some investigation, I discovered that i915 was reporting massive amounts of short HPD IRQ spam on this system from the DisplayPort port, despite there not being anything actually connected. The symptoms would start with one "long" HPD IRQ being detected at boot: [ 1.891398] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00440000, dig 0x00440000, pins 0x000000a0 [ 1.891436] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - long [ 1.891472] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 5 - cnt: 0 [ 1.891508] [drm:intel_hpd_irq_handler [i915]] digital hpd port D - long [ 1.891544] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 7 - cnt: 0 [ 1.891592] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - long [ 1.891628] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port D - long … followed by constant short IRQs afterwards: [ 1.895091] [drm:intel_encoder_hotplug [i915]] [CONNECTOR:66:DP-1] status updated from unknown to disconnected [ 1.895129] [drm:i915_hotplug_work_func [i915]] Connector DP-3 (pin 7) received hotplug event. [ 1.895165] [drm:intel_dp_detect [i915]] [CONNECTOR:72:DP-3] [ 1.895275] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x00200000, pins 0x00000080 [ 1.895312] [drm:intel_hpd_irq_handler [i915]] digital hpd port D - short [ 1.895762] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x00200000, pins 0x00000080 [ 1.895799] [drm:intel_hpd_irq_handler [i915]] digital hpd port D - short [ 1.896239] [drm:intel_dp_aux_xfer [i915]] dp_aux_ch timeout status 0x71450085 [ 1.896293] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x00200000, pins 0x00000080 [ 1.896330] [drm:intel_hpd_irq_handler [i915]] digital hpd port D - short [ 1.896781] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x00200000, pins 0x00000080 [ 1.896817] [drm:intel_hpd_irq_handler [i915]] digital hpd port D - short [ 1.897275] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x00200000, pins 0x00000080 The customer's system in question has a GM45 GPU, which is apparently well known for hotplugging storms. So, workaround this impressively broken hardware by changing the default HPD storm threshold from 5 to 50. Then, make long IRQs count for 10, and short IRQs count for 1. This makes it so that 5 long IRQs will trigger an HPD storm, and on systems with short HPD storm detection 50 short IRQs will trigger an HPD storm. 50 short IRQs amounts to 100ms of constant pulsing, which seems like a good middleground between being too sensitive and not being sensitive enough (which would cause visible stutters in userspace every time a storm occurs). And just to be extra safe: we don't enable this by default on systems with MST support. There's too high of a chance of MST support triggering storm detection, and systems that are new enough to support MST are a lot less likely to have issues with IRQ storms anyway. As a note: this patch was tested using a ThinkPad T450s and a Chamelium to simulate the short IRQ storms. Changes since v1: - Don't use two separate thresholds, just make long IRQs count for 10 each and short IRQs count for 1. This simplifies the code a bit - Ville Syrjälä Changes since v2: - Document @long_hpd in intel_hpd_irq_storm_detect, no functional changes Changes since v4: - Remove !! in long_hpd assignment - Ville Syrjälä - queue_hp = true - Ville Syrjälä Signed-off-by:
Lyude Paul <lyude@redhat.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by:
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Lyude Paul authored
This is rather confusing to look at as-is: dev_priv->display.hpd_irq_setup(dev_priv); in intel_hpd_irq_handler() handles disabling the actual HPD IRQ, while intel_hpd_irq_storm_disable() handles moving the HPD pin state over from MARK_DISABLED to DISABLED along with enabling polling for it. Changes since v3: - Rename i915_hpd_irq_storm_disable() to i915_hpd_irq_storm_switch_to_polling() - Rodrigo Vivi Signed-off-by:
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Lyude Paul authored
Currently in intel_hpd_irq_storm_detect() when we detect that the last recorded hotplug wasn't within the period defined by HPD_STORM_DETECT_DELAY, we make the mistake of resetting the HPD count to 0 without incrementing it. This results in us only enabling storm detection when we go +2 above the threshold, e.g. an HPD threshold of 5 would not trigger a storm until we reach a total of 7 hotplugs. So: rework the code a bit so we reset the HPD count when HPD_STORM_DETECT_DELAY has passed, then increment the count afterwards. Also, clean things up a bit to make it easier to undertand. Signed-off-by:
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Lyude Paul authored
Turns out that if you trigger an HPD storm on a system that has an MST topology connected to it, you'll end up causing the kernel to eventually hit a NULL deref: [ 332.339041] BUG: unable to handle kernel NULL pointer dereference at 00000000000000ec [ 332.340906] PGD 0 P4D 0 [ 332.342750] Oops: 0000 [#1] SMP PTI [ 332.344579] CPU: 2 PID: 25 Comm: kworker/2:0 Kdump: loaded Tainted: G O 4.18.0-rc3short-hpd-storm+ #2 [ 332.346453] Hardware name: LENOVO 20BWS1KY00/20BWS1KY00, BIOS JBET71WW (1.35 ) 09/14/2018 [ 332.348361] Workqueue: events intel_hpd_irq_storm_reenable_work [i915] [ 332.350301] RIP: 0010:intel_hpd_irq_storm_reenable_work.cold.3+0x2f/0x86 [i915] [ 332.352213] Code: 00 00 ba e8 00 00 00 48 c7 c6 c0 aa 5f a0 48 c7 c7 d0 73 62 a0 4c 89 c1 4c 89 04 24 e8 7f f5 af e0 4c 8b 04 24 44 89 f8 29 e8 <41> 39 80 ec 00 00 00 0f 85 43 13 fc ff 41 0f b6 86 b8 04 00 00 41 [ 332.354286] RSP: 0018:ffffc90000147e48 EFLAGS: 00010006 [ 332.356344] RAX: 0000000000000005 RBX: ffff8802c226c9d4 RCX: 0000000000000006 [ 332.358404] RDX: 0000000000000000 RSI: 0000000000000082 RDI: ffff88032dc95570 [ 332.360466] RBP: 0000000000000005 R08: 0000000000000000 R09: ffff88031b3dc840 [ 332.362528] R10: 0000000000000000 R11: 000000031a069602 R12: ffff8802c226ca20 [ 332.364575] R13: ffff8802c2268000 R14: ffff880310661000 R15: 000000000000000a [ 332.366615] FS: 0000000000000000(0000) GS:ffff88032dc80000(0000) knlGS:0000000000000000 [ 332.368658] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 332.370690] CR2: 00000000000000ec CR3: 000000000200a003 CR4: 00000000003606e0 [ 332.372724] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [ 332.374773] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 [ 332.376798] Call Trace: [ 332.378809] process_one_work+0x1a1/0x350 [ 332.380806] worker_thread+0x30/0x380 [ 332.382777] ? wq_update_unbound_numa+0x10/0x10 [ 332.384772] kthread+0x112/0x130 [ 332.386740] ? kthread_create_worker_on_cpu+0x70/0x70 [ 332.388706] ret_from_fork+0x35/0x40 [ 332.390651] Modules linked in: i915(O) vfat fat joydev btusb btrtl btbcm btintel bluetooth ecdh_generic iTCO_wdt wmi_bmof i2c_algo_bit drm_kms_helper intel_rapl syscopyarea sysfillrect x86_pkg_temp_thermal sysimgblt coretemp fb_sys_fops crc32_pclmul drm psmouse pcspkr mei_me mei i2c_i801 lpc_ich mfd_core i2c_core tpm_tis tpm_tis_core thinkpad_acpi wmi tpm rfkill video crc32c_intel serio_raw ehci_pci xhci_pci ehci_hcd xhci_hcd [last unloaded: i915] [ 332.394963] CR2: 00000000000000ec This appears to be due to the fact that with an MST topology, not all intel_connector structs will have ->encoder set. So, fix this by skipping connectors without encoders in intel_hpd_irq_storm_reenable_work(). For those wondering, this bug was found on accident while simulating HPD storms using a Chamelium connected to a ThinkPad T450s (Broadwell). Changes since v1: - Check intel_connector->mst_port instead of intel_connector->encoder Signed-off-by:
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Lyude Paul authored
This hasn't caused any issues yet that I'm aware of, but as Ville Syrjälä pointed out - we need to make sure that intel_connector->mst_port is set before initializing MST connectors, since in theory we could potentially check intel_connector->mst_port in i915_hpd_poll_init_work() after registering the connector but before having written it's value. Signed-off-by:
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Ville Syrjälä authored
Remove the "sizes are 0 based" stuff that is not even true for the scaler. v2: Rebase Signed-off-by:
Rodrigo Vivi <rodrigo.vivi@intel.com>
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Ville Syrjälä authored
No need for the posting reads in the plane update/disable hooks. If we need a posting read for something then a single one at the very end would be sufficient. We have that anyway in the form of eg. scanline/frame counter reads. Signed-off-by:
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Colin Ian King authored
Trivial fix to spelling mistake in DRM_INFO message Signed-off-by:
Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Chris Wilson authored
Exercising the gpu reloc path strenuously revealed an issue where the updated relocations (from MI_STORE_DWORD_IMM) were not being observed upon execution. After some experiments with adding pipecontrols (a lot of pipecontrols (32) as gen4/5 do not have a bit to wait on earlier pipe controls or even the current on), it was discovered that we merely needed to delay the EMIT_INVALIDATE by several flushes. It is important to note that it is the EMIT_INVALIDATE as opposed to the EMIT_FLUSH that needs the delay as opposed to what one might first expect -- that the delay is required for the TLB invalidation to take effect (one presumes to purge any CS buffers) as opposed to a delay after flushing to ensure the writes have landed before triggering invalidation. Testcase: igt/gem_tiled_fence_blits Signed-off-by:
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Kuo-Hsin Yang authored
The i915 driver uses shmemfs to allocate backing storage for gem objects. These shmemfs pages can be pinned (increased ref count) by shmem_read_mapping_page_gfp(). When a lot of pages are pinned, vmscan wastes a lot of time scanning these pinned pages. In some extreme case, all pages in the inactive anon lru are pinned, and only the inactive anon lru is scanned due to inactive_ratio, the system cannot swap and invokes the oom-killer. Mark these pinned pages as unevictable to speed up vmscan. Export pagevec API check_move_unevictable_pages(). This patch was inspired by Chris Wilson's change [1]. [1]: https://patchwork.kernel.org/patch/9768741/ Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Dave Hansen <dave.hansen@intel.com> Signed-off-by:
Kuo-Hsin Yang <vovoy@chromium.org> Acked-by: Michal Hocko <mhocko@suse.com> # mm part Reviewed-by:
Dave Hansen <dave.hansen@intel.com> Acked-by:
Andrew Morton <akpm@linux-foundation.org> Link: https://patchwork.freedesktop.org/patch/msgid/20181106132324.17390-1-chris@chris-wilson.co.ukSigned-off-by:
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- 06 Nov, 2018 4 commits
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Ville Syrjälä authored
We deinit the lpe audio device before we call drm_atomic_helper_shutdown(), which means the platform device may already be gone when it comes time to shut down the crtc. As we don't know when the last reference to the platform device gets dropped by the audio driver we can't assume that the device and its data are still around when turning off the crtc. Mark the platform device as gone as soon as we do the audio deinit. Cc: stable@vger.kernel.org Signed-off-by:
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Chris Wilson authored
As we may have to iterate a few thousand elements to acquire and release the shmemfs backing storage for a GPU object, we need to break up the long loop with cond_resched() to retain a modicum of low latency for other processes. Testcase: igt/benchmarks/gem_syslatency Signed-off-by:
Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181105170640.26905-1-chris@chris-wilson.co.uk
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Uma Shankar authored
Plane input CSC needs to be enabled to convert frambuffers from YUV to RGB. This is needed for bottom 3 planes on ICL, rest of the planes have hardcoded conversion and taken care by the legacy code. This patch defines the co-efficient values for YUV to RGB conversion in BT709 and BT601 formats. It programs the coefficients and enables the plane input csc unit in hardware. This has been verified and tested by Maarten and the change is working as expecpted. v2: Addressed Maarten's and Ville's review comments and added the coefficients in a 2D array instead of independent Macros. v3: Added individual coefficient matrix (9 values) instead of 6 register values as per Maarten's comment. Also addresed a shift issue with B channel coefficient. v4: Added support for Limited Range Color Handling v5: Fixed Matt and Maarten's review comments. v6: Added human readable matrix values for YUV to RGB Conversion along with just the bspec register values, as per Matt's suggestion. v7: Refactored the code, move csc coefficient programming function to intel_sprite.c and made it static as per Ville's review comment. v8: Addressed Ville's review comment. Called the coefficient programming from within the skl_program_plane and used I915_WRITE_FW instead of I915_WRITE. v9: Fixed Ville's review comments. Signed-off-by:
Uma Shankar <uma.shankar@intel.com> Reviewed-by:
Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by:
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Uma Shankar authored
Defined the plane input csc coefficient registers and macros. 6 registers are used to program a total of 9 coefficients, added macros to define each of them for all the planes supporting the feature on pipes. On ICL, bottom 3 planes have this capability. v2: Segregated the register macro definition as separate patch as per Maarten's suggestion. v3: Removed a redundant 3rd Pipe register definition and simplified the equally spaced register definition by adding an offset as per Matt's comment. v4: No Change v5: Renamed the register Macro as per Matt's suggestion. v6: No Change v7: No Change v8: No Change v9: No Change Signed-off-by:
Matt Roper <matthew.d.roper@intel.com> Reviewed-by:
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- 05 Nov, 2018 4 commits
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Ville Syrjälä authored
We're no longer programming any watermarks when we're disabling a pipe. That means ilk_wm_merge() & co. will keep considering the any pipe that is getting disabled as still enabled. Thus we either get no LP1+ watermakrs (ilk-ivb), or we get suboptimal ones (hsw-bdw). This seems to have been broken by commit b6b178a7 ("drm/i915: Calculate ironlake intermediate watermarks correctly, v2."). Before that we apparently had some difference between the intermediate and optimal watermarks and so we would program the optiomal ones. Now intermediate and optimal are identical for disabled pipes and so we don't program either. Fix this by programming the intermediate watermarks even for disabled pipes. We were already doing that for skl+. We'll leave out gmch platforms for now since those do the merging in a different manner and should work as is. We'll want to unify this eventually, but play it safe for now and just put in a FIXME. Cc: stable@vger.kernel.org Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Fixes: b6b178a7 ("drm/i915: Calculate ironlake intermediate watermarks correctly, v2.") Signed-off-by:
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Imre Deak authored
On GEN9 LP (BXT/GLK) DC6 is not supported, so don't print the counter on those platforms. So far we did this on GLK too. While at it warn if we forgot to adjust the printout properly for a new platform. (Rodrigo) Testcase: igt/pm_dc/dc6-dpms Cc: Jyoti Yadav <jyoti.r.yadav@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
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Imre Deak authored
The MG DP mode needs to be configured for Type C static/fixed/legacy HDMI ports too, the same way as it's configured for Type C static/fixed/legacy, fix this. Bspec: 4232, 21735 Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by:
José Roberto de Souza <jose.souza@intel.com> Tested-by:
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Imre Deak authored
The MG PHY clock gating needs to be configured for Type C static/fixed/legacy HDMI ports the same way it's configured for Type C static/fixed/legacy and aternate mode DP ports, fix this. Bspec: 4232, 21735 Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by:
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- 03 Nov, 2018 2 commits
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Anusha Srivatsa authored
DP 1.4 has Forward Error Correction Support(FEC). Add helper function to check if the sink device supports FEC. v2: Separate the helper and the code that uses the helper into two separate patches. (Manasi) v3: - Move the code to drm_dp_helper.c (Manasi) - change the return type, code style changes (Gaurav) - Use drm_dp_dpcd_readb instead of drm_dp_dpcd_read. (Jani) v4: - Avoid aux reads everytime, instead read cached values of dpcd register (jani) - Move helper to drm_dp_helper.h like other dsc helpers.(Anusha) v5: rebased. Change the helper parameter suitably. Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Acked-by: Sean Paul <seanpaul@chromium.org> (For merging through drm-intel) Signed-off-by:
Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by:
Manasi Navare <manasi.d.navare@intel.com> Signed-off-by:
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Anusha Srivatsa authored
Similar to DSC DPCD registers, let us cache FEC_CAPABLE register to avoid using stale values. With this we can avoid aux reads everytime and instead read the cached values. v2: Avoid using memset and array for a single field. (Manasi,Jani) v3: Print FEC CAPABILITY value. (Manasi) Suggested-by:
Jani Nikula <jani.nikula@linux.intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by:
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- 02 Nov, 2018 16 commits
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Chris Wilson authored
Since the flags are being used to operate on a u64 variable, they too need to be marked as such so that the inverses are full width (and not zero extended on 32b kernels and bdw+). Reported-by:
Sergii Romantsov <sergii.romantsov@globallogic.com> Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by:
Michal Wajdeczko <michal.wajdeczko@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181102161232.17742-2-chris@chris-wilson.co.uk
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Anusha Srivatsa authored
The registers DPCSSS,DPSP,DPMLE1 and DPPMS are all at an offset from the base - which is the FLexi IO Adaptor. Lets follow the offset calculation while accessing these registers. v2: - Follow spec for numbering - s/0/1(Lucas) - s/FIA_1/FIA1_BASE (Anusha) v3: - Remove register offset defines. (Jani) - Update comment. (Anusha) v4: rebase. Remove comment.(Lucas) Cc: Jani Nikula <jani.nikula@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by:
Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by:
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Ville Syrjälä authored
Ever since commit 46e831ab ("drm/i915/lpe: Mark LPE audio runtime pm as "no callbacks"") the runtime suspend/resume hooks are no longer used. Inline them into the system suspend hooks. Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Takashi Iwai <tiwai@suse.de> Cc: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Signed-off-by:
Takashi Iwai <tiwai@suse.de>
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Ville Syrjälä authored
Commit 46e831ab ("drm/i915/lpe: Mark LPE audio runtime pm as "no callbacks"") broke runtime PM with lpe audio. We can no longer runtime suspend the GPU since the sysfs power/control for the lpe-audio device no longer exists and the device is considered always active. We can fix this by not marking the device as active. Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Takashi Iwai <tiwai@suse.de> Cc: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Fixes: 46e831ab ("drm/i915/lpe: Mark LPE audio runtime pm as "no callbacks"") Signed-off-by:
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Radhakrishna Sripada authored
Use the newly added "max bpc" connector property to limit pipe bpp. V3: Use drm_connector_state to access the "max bpc" property V4: Initialize the drm property, add suuport to DP(Ville) V5: Use the property in the connector and fix CI failure(Ville) V6: Use the core function to attach max_bpc property, remove the redundant clamping of pipe bpp based on connector info V7: Fix Checkpatch warnings V9: Cleanup connected_sink_max_bpp and fix initial value in DP(Ville) V12: Fix debug message(Ville) V13: Remove the redundant check and simplify the check logic(Stan) V14: Fix the check in connected_sink_max_bpp(Stan) v15 (From Manasi): Add missing break (Stan) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Kishore Kadiyala <kishore.kadiyala@intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by:Radhakrishna Sripada <radhakrishna.sripada@intel.com> Reviewed-by:
Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by:
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Radhakrishna Sripada authored
At times 12bpc HDMI cannot be driven due to faulty cables, dongles level shifters etc. To workaround them we may need to drive the output at a lower bpc. Currently the user space does not have a way to limit the bpc. The default bpc to be programmed is decided by the driver and is run against connector limitations. Creating a new connector property "max bpc" in order to limit the bpc. xrandr can make use of this connector property to make sure that bpc does not exceed the configured value. This property can be used by userspace to set the bpc. V2: Initialize max_bpc to satisfy kms_properties V3: Move the property to drm_connector V4: Split drm and i915 components(Ville) V5: Make the property per connector(Ville) V6: Compare the requested bpc to connector bpc(Daniel) Move the attach_property function to core(Ville) V7: Fix checkpatch warnings V8: Simplify the connector check code(Ville) V9: Const display_info(Ville) V10,V11: Fix CI issues. V12: Add the Kernel documentation(Daniel) V14: Crossreference the function name in the doc(Daniel) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Kishore Kadiyala <kishore.kadiyala@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Cc: Sunpeng Li <sunpeng.li@amd.com> Acked-by:Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by:
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Jani Nikula authored
Signed-off-by:Jani Nikula <jani.nikula@intel.com>
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Jani Nikula authored
Keep the register choosing macros together. No functional changes. Reviewed-by:
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Jani Nikula authored
Try to make it slightly less of an eye sore. No functional changes. Reviewed-by:
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Jani Nikula authored
Minor semantic nit, no functional changes. Reviewed-by:
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Jani Nikula authored
The device info offset arrays for unevenly spaced register offsets is great for widely used registers. However, the palette registers are only used in one function, i9xx_load_luts_internal(), and only for GMCH platforms, wasting device info. Replace palette_offsets with _PICK() in palette register definition. While the use of _PICK() does not check for pipe C existence, neither does the current offset array usage, and leads to bogus address when pipe C is passed to PALETTE() on non-CHV. Using _PICK() at least leads to a sensible register offset, just non-existing on non-CHV. Either way, this shouldn't happen anyway. Remove unused old palette macros while at it. Bloat-o-meter results below for completeness. add/remove: 0/0 grow/shrink: 3/6 up/down: 94/-278 (-184) Function old new delta i9xx_load_luts_internal 394 483 +89 i915_driver_load 5103 5107 +4 g4x_pre_enable_dp 378 379 +1 intel_engines_init_mmio 1117 1116 -1 intel_engine_lookup_user 47 46 -1 hdmi_port_clock_valid 310 309 -1 gen11_irq_handler 707 706 -1 intel_device_info_dump_runtime 329 311 -18 intel_device_info_runtime_init 5166 4910 -256 Total: Before=918650, After=918466, chg -0.02% add/remove: 0/0 grow/shrink: 0/48 up/down: 0/-576 (-576) Data old new delta intel_valleyview_info 200 188 -12 intel_skylake_gt4_info 200 188 -12 intel_skylake_gt3_info 200 188 -12 intel_skylake_gt2_info 200 188 -12 intel_skylake_gt1_info 200 188 -12 intel_sandybridge_m_gt2_info 200 188 -12 intel_sandybridge_m_gt1_info 200 188 -12 intel_sandybridge_d_gt2_info 200 188 -12 intel_sandybridge_d_gt1_info 200 188 -12 intel_pineview_info 200 188 -12 intel_kabylake_gt3_info 200 188 -12 intel_kabylake_gt2_info 200 188 -12 intel_kabylake_gt1_info 200 188 -12 intel_ivybridge_q_info 200 188 -12 intel_ivybridge_m_gt2_info 200 188 -12 intel_ivybridge_m_gt1_info 200 188 -12 intel_ivybridge_d_gt2_info 200 188 -12 intel_ivybridge_d_gt1_info 200 188 -12 intel_ironlake_m_info 200 188 -12 intel_ironlake_d_info 200 188 -12 intel_icelake_11_info 200 188 -12 intel_i965gm_info 200 188 -12 intel_i965g_info 200 188 -12 intel_i945gm_info 200 188 -12 intel_i945g_info 200 188 -12 intel_i915gm_info 200 188 -12 intel_i915g_info 200 188 -12 intel_i865g_info 200 188 -12 intel_i85x_info 200 188 -12 intel_i845g_info 200 188 -12 intel_i830_info 200 188 -12 intel_haswell_gt3_info 200 188 -12 intel_haswell_gt2_info 200 188 -12 intel_haswell_gt1_info 200 188 -12 intel_gm45_info 200 188 -12 intel_geminilake_info 200 188 -12 intel_g45_info 200 188 -12 intel_g33_info 200 188 -12 intel_coffeelake_gt3_info 200 188 -12 intel_coffeelake_gt2_info 200 188 -12 intel_coffeelake_gt1_info 200 188 -12 intel_cherryview_info 200 188 -12 intel_cannonlake_info 200 188 -12 intel_broxton_info 200 188 -12 intel_broadwell_rsvd_info 200 188 -12 intel_broadwell_gt3_info 200 188 -12 intel_broadwell_gt2_info 200 188 -12 intel_broadwell_gt1_info 200 188 -12 Total: Before=195529, After=194953, chg -0.29% Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Jani Nikula authored
Although there's nothing crucial missing, it's been a long time since the last backmerge. Catch up with drm-next. Signed-off-by: -
Dave Airlie authored
Merge tag 'drm-intel-next-fixes-2018-10-25' of git://anongit.freedesktop.org/drm/drm-intel into drm-next - Fix to avoid link retraining workaround on eDP (the other is a comment change) Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181025131836.GA2296@jlahtine-desk.ger.corp.intel.com
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Anusha Srivatsa authored
This patch fixes the naming of the registers: s/PIPE_DSS_CTL/ICL_PIPE_DSS_CTL And also fix the hex values to lower case, to match rest of the definitions. Manasi noticed this with the patch that was merged. v2: fix "Fixes" tag. Fixes: 8b1b558d ("drm/i915/icl: Add DSS_CTL Registers") Suggested-by:
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git://people.freedesktop.org/~agd5f/linuxDave Airlie authored
- Fix flickering at low backlight levels on some systems - Fix some overclocking regressions - Vega20 updates for - GPU recovery fixes - Disable gfxoff on RV as some sbios/fw combinations are not stable yet Signed-off-by:
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Dave Airlie authored
Merge tag 'drm-misc-next-fixes-2018-10-31' of git://anongit.freedesktop.org/drm/drm-misc into drm-next - Properly label Innolux TV123WAM as P120ZDG-BF1 (Doug) - Add optional delay for panels without hpd hooked up (which solves the mystery delay for TI SN65DSI86 bridge) (Doug) - Another 6bpc quirk for BOE panel 0x0771 (Shawn) Cc: Doug Anderson <dianders@chromium.org> Cc: Lee, Shawn C <shawn.c.lee@intel.com> Signed-off-by:
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- 01 Nov, 2018 2 commits
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Imre Deak authored
BIOS can leave the PLL to port mapping enabled, even if the corresponding encoder is disabled. Disable the port mapping in this case. Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
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Imre Deak authored
Most of the AUX_CH_CTL flags are concerned with DP AUX transfer parameters. As opposed to this the flag specifying the thunderbolt vs. non-thunderbolt mode of the port is not related to AUX transfers at all (rather it's repurposed to enable either TBT or non-TBT PHY HW blocks). The programming has to be done before enabling the corresponding AUX power well, so make it part of the power well code. v3: - Use existing enable/disable helpers instead of opencoding. (Jose) - Fix type of is_tc_tbt to remain a bitfield. (Lucas) - Add comment describing the is_tc_tbt power well flag. (Lucas) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108548 Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
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