- 23 Dec, 2019 27 commits
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zhengbin authored
Fixes coccicheck warning: drivers/gpu/drm/radeon/ni.c:2020:2-15: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/radeon/ni.c:2088:2-15: WARNING: Assignment of 0/1 to bool variable Reported-by:
Hulk Robot <hulkci@huawei.com> Signed-off-by:
zhengbin <zhengbin13@huawei.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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zhengbin authored
Fixes coccicheck warning: drivers/gpu/drm/radeon/cik.c:8140:2-15: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/radeon/cik.c:8212:2-15: WARNING: Assignment of 0/1 to bool variable Reported-by:
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zhengbin authored
Fixes coccicheck warning: drivers/gpu/drm/radeon/rv770.c:1706:2-15: WARNING: Assignment of 0/1 to bool variable Reported-by:
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zhengbin authored
Fixes coccicheck warning: drivers/gpu/drm/radeon/evergreen.c:4948:2-15: WARNING: Assignment of 0/1 to bool variable Reported-by:
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zhengbin authored
Fixes coccicheck warning: drivers/gpu/drm/radeon/r600.c:3056:2-15: WARNING: Assignment of 0/1 to bool variable Reported-by:
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zhengbin authored
Fixes coccicheck warning: drivers/gpu/drm/radeon/si.c:6475:2-15: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/radeon/si.c:6542:2-15: WARNING: Assignment of 0/1 to bool variable Reported-by:
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zhengbin authored
Fixes coccicheck warning: drivers/gpu/drm/radeon/r100.c:1826:3-31: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/radeon/r100.c:1828:3-31: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/radeon/r100.c:2390:2-22: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/radeon/r100.c:2395:2-22: WARNING: Assignment of 0/1 to bool variable Reported-by:
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Alex Deucher authored
Add defined peak sclk for navi12 peak profile mode. Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Alex Deucher authored
Fetch the sclk from the pptable if there is no specified sclk for the board. Reviewed-by:
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Guchun Chen authored
Return value should be set when going to error handle tag for error case, this can avoid potential invalid array access by upper caller. Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Frank.Min authored
FB location is already programmed by HV driver for arcutus so remove this part Signed-off-by:
Frank.Min <Frank.Min@amd.com> Reviewed-by:
Emily Deng <Emily.Deng@amd.com> Signed-off-by:
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Frank.Min authored
1. enable xgmi ta initialization for sriov 2. enable xgmi initialization for sriov Signed-off-by:
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Tianci.Yin authored
IP discovery TMR(occupied the top VRAM with size DISCOVERY_TMR_SIZE) has been reserved, and the p2c buffer is in the range of this TMR, so the p2c buffer reservation is unnecessary. Reviewed-by:
Kevin Wang <kevin1.wang@amd.com> Reviewed-by:
Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by:
Tianci.Yin <tianci.yin@amd.com> Signed-off-by:
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Tianci.Yin authored
The method of getting fb_loc changed from parsing VBIOS to taking certain offset from top of VRAM Reviewed-by:
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Ma Feng authored
Fixes coccicheck warning: drivers/gpu/drm/amd/amdgpu/navi10_ih.c:113:5-8: Unneeded variable: "ret". Return "0" on line 182 Reported-by:
Ma Feng <mafeng.ma@huawei.com> Signed-off-by:
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Ma Feng authored
Fixes coccicheck warning: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1036:5-8: Unneeded variable: "ret". Return "0" on line 1079 Reported-by:
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James Zhu authored
Add mmSDMA2-7_EDC_COUNTER to support Arcturus Signed-off-by:
James Zhu <James.Zhu@amd.com> Reviewed-by:
Yong Zhao <Yong.Zhao@amd.com> Signed-off-by:
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James Zhu authored
Add mmCOMPUTE_STATIC_THREAD_MGMT_SE4-7 to support Arcturus Signed-off-by:
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James Zhu authored
Replace ARRAY_SIZE with size variables to support different ASICs. Signed-off-by:
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James Zhu authored
Arcturus has 8 SEs. Add mmCOMPUTE_STATIC_THREAD_MGMT_SE4-7 for EDC GPR _workarounds, Signed-off-by:
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John Clements authored
Devices newer then VEGA10/12 shall have these programming sequences performed by PSP BL Reviewed-by:
John Clements <john.clements@amd.com> Signed-off-by:
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Frank.Min authored
max range of the agp aperture is 48 bits, so enlarge agp_start address into 48bit with all bits set Signed-off-by:
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Jane Jian authored
currently using TMR loading VCN fw MMSCH would fail to init after FLR, just disable ib test for temporarily daily testing, continuing debug with mm team. Signed-off-by:
Jane Jian <Jane.Jian@amd.com> Acked-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
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Le Ma authored
This workaround does not affect other asics because amdgpu only need expose one gfx sched to user for now. Signed-off-by:
Le Ma <le.ma@amd.com> Reviewed-by:
Nirmoy Das <nirmoy.das@amd.com> Signed-off-by:
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Jonathan Kim authored
The DF routines to arm xGMI performance will attempt to re-arm both on performance monitoring start and read on initial failure to arm. Signed-off-by:
Jonathan Kim <Jonathan.Kim@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Jonathan Kim authored
During DF C-State, Perfmon counters outside of range 1D700-1D7FF will encounter SLVERR affecting xGMI performance monitoring. PerfmonCtr[7:4] is being added to avoid SLVERR during read since it falls within this range. PerfmonCtl[7:4] is being added in order to arm PerfmonCtr[7:4]. Since PerfmonCtl[7:4] exists outside of range 1D700-1D7FF, DF routines will be enabled to opportunistically re-arm PerfmonCtl[7:4] on retry after SLVERR. Signed-off-by:
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Luben Tuikov authored
Simplify padding calculations. v2: Comment update and spacing. Signed-off-by:
Luben Tuikov <luben.tuikov@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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- 19 Dec, 2019 4 commits
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Huang Rui authored
Thunk driver would like to know the num_cp_queues data, however this data relied on different asic specific. So it's better to get it from kfd driver. v2: don't update name size. Signed-off-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
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Huang Rui authored
Thunk driver would like to know the num_sdma_queues_per_engine data, however this data relied on different asic specific. So it's better to get it from kfd driver. v2: don't update the name size. Signed-off-by:
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Yintian Tao authored
Under sriov, the disable operation is no allowed. Signed-off-by:
Yintian Tao <yttao@amd.com> Reviewed-by:
Kenneth Feng <kenneth.feng@amd.com> Signed-off-by:
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Jane Jian authored
v1: compared to bare-metal: sriov support psp loading VCN firmware; only one encoding ring would be used in each instance. v2: keep unchange for bare-metal VCN2.5 hw_init, just add a flag with sriov and also remove multiple lines. v3: squash in warning fix Signed-off-by:
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- 18 Dec, 2019 9 commits
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Jane Jian authored
v1: skip gating in serveral called functions by power gating and clock gating v2: from suggestion, skip setting gate in both set function, which is where it being called. Signed-off-by:
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Jane Jian authored
Previously there is no VCN1 type ID in psp gfx interface. Also add VCN ip block type unless the reinit after FLR for sriov would fail. Signed-off-by:
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Jane Jian authored
Use MMSCH V1 to finish Memory Controller programming as well as start MMSCH to do VCN2.5 initialization. Signed-off-by:
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Jane Jian authored
Use MMSCH to do the initialization since MMSCH manages VCN2.5 instances and its world switch. Signed-off-by:
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Guchun Chen authored
Code refactor and no functional change. Fixes: 4cf781c2 ("drm/amdgpu: Added RAS UMC error query support for Arcturus") Signed-off-by:
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Alex Deucher authored
For udelay. This is needed for some platforms. Reviewed-by:
Nicholas Kazlauskas <nicholas.kazluaskas@amd.com> Signed-off-by:
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Alex Deucher authored
To protect access to the metrics table. v2: unlock on error Bug: https://gitlab.freedesktop.org/drm/amd/issues/900Reviewed-by:
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Alex Deucher authored
To protect access to the metrics table. v2: unlock on error Bug: https://gitlab.freedesktop.org/drm/amd/issues/900Reviewed-by:
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Alex Deucher authored
To protect access to the metrics table. v2: unlock on error Bug: https://gitlab.freedesktop.org/drm/amd/issues/900Reviewed-by:
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