- 29 Mar, 2022 7 commits
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Stephen Boyd authored
- Make clk_set_rate_range() re-evaluate the limits each time - Introduce various clk_set_rate_range() tests - Add clk_drop_range() to drop a previously set range - Support for NCO blocks on Apple SoCs * clk-range: clk: Drop the rate range on clk_put() clk: test: Test clk_set_rate_range on orphan mux clk: Initialize orphan req_rate clk: bcm: rpi: Run some clocks at the minimum rate allowed clk: bcm: rpi: Set a default minimum rate clk: bcm: rpi: Add variant structure clk: Add clk_drop_range clk: Always set the rate on clk_set_range_rate clk: Use clamp instead of open-coding our own clk: Always clamp the rounded rate clk: Enforce that disjoints limits are invalid clk: Introduce Kunit Tests for the framework clk: Fix clk_hw_get_clk() when dev is NULL * clk-uniphier: clk: uniphier: Fix fixed-rate initialization * clk-apple: clk: clk-apple-nco: Allow and fix module building MAINTAINERS: Add clk-apple-nco under ARM/APPLE MACHINE clk: clk-apple-nco: Add driver for Apple NCO dt-bindings: clock: Add Apple NCO * clk-qcom: (61 commits) clk: qcom: gcc-msm8994: Fix gpll4 width dt-bindings: clock: fix dt_binding_check error for qcom,gcc-other.yaml clk: qcom: Add display clock controller driver for SM6125 dt-bindings: clock: add QCOM SM6125 display clock bindings clk: qcom: Fix sorting of SDX_GCC_65 in Makefile and Kconfig clk: qcom: gcc: Add emac GDSC support for SM8150 clk: qcom: gcc: sm8150: Fix some identation issues clk: qcom: gcc: Add UFS_CARD and UFS_PHY GDSCs for SM8150 clk: qcom: gcc: Add PCIe0 and PCIe1 GDSC for SM8150 clk: qcom: clk-rcg2: Update the frac table for pixel clock clk: qcom: clk-rcg2: Update logic to calculate D value for RCG clk: qcom: smd: Add missing MSM8998 RPM clocks clk: qcom: smd: Add missing RPM clocks for msm8992/4 dt-bindings: clock: qcom: rpmcc: Add RPM Modem SubSystem (MSS) clocks clk: qcom: gcc-ipq806x: add CryptoEngine resets dt-bindings: reset: add ipq8064 ce5 resets clk: qcom: gcc-ipq806x: add CryptoEngine clocks dt-bindings: clock: add ipq8064 ce5 clk define clk: qcom: gcc-ipq806x: add additional freq for sdc table clk: qcom: clk-rcg: add clk_rcg_floor_ops ops ...
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Stephen Boyd authored
- Audio clks on StarFive JH7100 RISC-V SoC - Terminate arrays with sentinels and make that clearer - Cleanup SPDX tags - Fix typos in comments * clk-starfive: clk: starfive: Add JH7100 audio clock driver clk: starfive: jh7100: Support more clock types clk: starfive: jh7100: Make hw clock implementation reusable dt-bindings: clock: Add starfive,jh7100-audclk bindings dt-bindings: clock: Add JH7100 audio clock definitions clk: starfive: jh7100: Handle audio_div clock properly clk: starfive: jh7100: Don't round divisor up twice * clk-ti: clk: ti: Drop legacy compatibility clocks for dra7 clk: ti: Drop legacy compatibility clocks for am4 clk: ti: Drop legacy compatibility clocks for am3 clk: ti: Update component clocks to use ti_dt_clk_name() clk: ti: Update pll and clockdomain clocks to use ti_dt_clk_name() clk: ti: Add ti_dt_clk_name() helper to use clock-output-names clk: ti: Use clock-output-names for clkctrl clk: ti: Add ti_find_clock_provider() to use clock-output-names clk: ti: Optionally parse IO address from parent clock node clk: ti: Preserve node in ti_dt_clocks_register() clk: ti: Constify clkctrl_name * clk-terminate: clk: actions: Make sentinel elements more obvious clk: clps711x: Terminate clk_div_table with sentinel element clk: hisilicon: Terminate clk_div_table with sentinel element clk: loongson1: Terminate clk_div_table with sentinel element clk: actions: Terminate clk_div_table with sentinel element * clk-cleanup: clk: zynq: Update the parameters to zynq_clk_register_periph_clk clk: zynq: trivial warning fix clk: qcom: sm6125-gcc: fix typos in comments clk: ti: clkctrl: fix typos in comments clk: COMMON_CLK_LAN966X should depend on SOC_LAN966 clk: Use of_device_get_match_data() clk: bcm2835: Remove unused variable clk: tegra: tegra124-emc: Fix missing put_device() call in emc_ensure_emc_driver clk: cleanup comments clk: socfpga: cleanup spdx tags
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Stephen Boyd authored
- Mark mux table as const in clk-mux - Make the all_lists array const * clk-mvebu: clk: mvebu: use time_is_before_eq_jiffies() instead of open coding it * clk-const: clk: Mark clk_core_evict_parent_cache_subtree() 'target' const clk: Mark 'all_lists' as const clk: pistachio: Declare mux table as const u32[] clk: qcom: Declare mux table as const u32[] clk: mmp: Declare mux tables as const u32[] clk: hisilicon: Remove unnecessary cast of mux table to u32 * clk: mux: Declare u32 *table parameter as const clk: nxp: Declare mux table parameter as const u32 * clk: nxp: Remove unused variable * clk-imx: (28 commits) dt-bindings: clock: drop useless consumer example clk: imx: Select MXC_CLK for i.MX93 clock driver clk: imx: remove redundant re-assignment of pll->base MAINTAINERS: clk: imx: add git tree and dt-bindings files clk: imx: pll14xx: Support dynamic rates clk: imx: pll14xx: Add pr_fmt clk: imx: pll14xx: explicitly return lowest rate clk: imx: pll14xx: name variables after usage clk: imx: pll14xx: consolidate rate calculation clk: imx: pll14xx: Use FIELD_GET/FIELD_PREP clk: imx: pll14xx: Drop wrong shifting clk: imx: pll14xx: Use register defines consistently clk: imx8mp: remove SYS PLL 1/2 clock gates clk: imx8mn: remove SYS PLL 1/2 clock gates clk: imx8mm: remove SYS PLL 1/2 clock gates clk: imx: add i.MX93 clk clk: imx: support fracn gppll clk: imx: add i.MX93 composite clk dt-bindings: clock: add i.MX93 clock definition dt-bindings: clock: Add imx93 clock support ... * clk-rockchip: clk: rockchip: re-add rational best approximation algorithm to the fractional divider clk/rockchip: Use of_device_get_match_data() clk: rockchip: Add CLK_SET_RATE_PARENT to the HDMI reference clock on rk3568 clk: rockchip: drop CLK_SET_RATE_PARENT from dclk_vop* on rk3568 clk: rockchip: Add more PLL rates for rk3568
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Stephen Boyd authored
- Kunit tests for clk-gate implementation - Convert Cirrus Logic CS2000P driver to regmap, yamlify DT binding and add support for dynamic mode * clk-xilinx: clk: zynqmp: replace warn_once with pr_debug for failed clock ops * clk-kunit: clk: gate: Add some kunit test suites * clk-cs2000: clk: cs2000-cp: convert driver to regmap clk: cs2000-cp: freeze config during register fiddling clk: cs2000-cp: make clock skip setting configurable clk: cs2000-cp: add support for dynamic mode clk: cs2000-cp: Make aux output function controllable dt-bindings: clock: cs2000-cp: document cirrus,dynamic-mode dt-bindings: clock: cs2000-cp: document cirrus,clock-skip flag dt-bindings: clock: cs2000-cp: document aux-output-source dt-bindings: clock: convert cs2000-cp bindings to yaml * clk-renesas: dt-bindings: clock: renesas: Make example 'clocks' parsable clk: rs9: Add Renesas 9-series PCIe clock generator driver clk: fixed-factor: Introduce devm_clk_hw_register_fixed_factor_index() dt-bindings: clk: rs9: Add Renesas 9-series I2C PCIe clock generator clk: renesas: r8a779f0: Add PFC clock clk: renesas: r8a779f0: Add I2C clocks clk: renesas: r8a779f0: Add WDT clock clk: renesas: r8a779f0: Fix RSW2 clock divider clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC dt-bindings: clock: renesas: Document RZ/V2L SoC dt-bindings: clock: Add R9A07G054 CPG Clock and Reset Definitions clk: renesas: r8a779a0: Add CANFD module clock clk: renesas: r9a07g044: Update multiplier and divider values for PLL2/3 clk: renesas: r8a7799[05]: Add MLP clocks clk: renesas: r8a779f0: Add SYS-DMAC clocks
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Stephen Boyd authored
- Clock configuration on Microchip PolarFire SoCs - Free allocations on probe error in Mediatek clk driver - Modernize Mediatek clk driver by consolidating code * clk-microchip: clk: microchip: Add driver for Microchip PolarFire SoC dt-bindings: clk: microchip: Add Microchip PolarFire host binding * clk-si: clk-si5341: replace snprintf in show functions with sysfs_emit clk: si5341: fix reported clk_rate when output divider is 2 * clk-mtk: (32 commits) clk: mediatek: Warn if clk IDs are duplicated clk: mediatek: mt8195: Implement remove functions clk: mediatek: mt8195: Implement error handling in probe functions clk: mediatek: mt8195: Hook up mtk_clk_simple_remove() clk: mediatek: Unregister clks in mtk_clk_simple_probe() error path clk: mediatek: mtk: Implement error handling in register APIs clk: mediatek: pll: Implement error handling in register API clk: mediatek: mux: Implement error handling in register API clk: mediatek: mux: Reverse check for existing clk to reduce nesting level clk: mediatek: gate: Implement error handling in register API clk: mediatek: cpumux: Implement error handling in register API clk: mediatek: mtk: Clean up included headers clk: mediatek: Add mtk_clk_simple_remove() clk: mediatek: Implement mtk_clk_unregister_composites() API clk: mediatek: Implement mtk_clk_unregister_divider_clks() API clk: mediatek: Implement mtk_clk_unregister_factors() API clk: mediatek: Implement mtk_clk_unregister_fixed_clks() API clk: mediatek: pll: Clean up included headers clk: mediatek: pll: Implement unregister API clk: mediatek: pll: Split definitions into separate header file ... * clk-at91: clk: at91: clk-master: remove dead code clk: at91: sama7g5: fix parents of PDMCs' GCLK clk: at91: sama7g5: Allow MCK1 to be exported and referenced in DT clk: at91: allow setting PMC_AUDIOPINCK clock parents via DT * clk-st: clk: stm32mp1: Add parent_data to ETHRX clock clk: stm32mp1: Split ETHCK_K into separate MUX and GATE clock
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Shubhrajyoti Datta authored
In case there are only one gate or the two_gate is 0 the clk1 clock passed is not used. We are passing 0 which is arm_pll. Pass a invalid clock instead. Signed-off-by:
Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Link: https://lore.kernel.org/r/20220222130903.17235-3-shubhrajyoti.datta@xilinx.comSigned-off-by:
Stephen Boyd <sboyd@kernel.org>
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Shubhrajyoti Datta authored
Fix the below warning WARNING: Missing a blank line after declarations + int enable = !!(fclk_enable & BIT(i - fclk0)); + zynq_clk_register_fclk(i, clk_output_name[i], Signed-off-by:
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- 25 Mar, 2022 7 commits
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Maxime Ripard authored
When clk_put() is called we don't make another clk_set_rate() call to re-evaluate the rate boundaries. This is unlike clk_set_rate_range() that evaluates the rate again each time it is called. However, clk_put() is essentially equivalent to clk_set_rate_range() since after clk_put() completes the consumer's boundaries shouldn't be enforced anymore. Let's add a call to clk_set_rate_range() in clk_put() to make sure those rate boundaries are dropped and the clock provider drivers can react. Also add a few tests to make sure this case is covered. Fixes: c80ac50c ("clk: Always set the rate on clk_set_range_rate") Signed-off-by:
Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20220325161144.1901695-4-maxime@cerno.tech [sboyd@kernel.org: Reword commit text] Signed-off-by:
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Maxime Ripard authored
A bug recently affected the Tegra30 where calling clk_set_rate_range() on a clock would make it change its rate to the minimum. This was due to the clock in question being a mux that was orphan at registration, which lead to the clk_core req_rate being 0, and the clk_set_rate_range() function then calling clk_set_rate() with req_rate, effectively making that clock running at the minimum rate allowed, even though the initial rate was within that range. Make a test suite to create a mux initially orphan, and then make sure that if our clock rate was initially within a given range, then enforcing that range won't affect it. Signed-off-by:
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Maxime Ripard authored
When registering a clock that doesn't have a recalc_rate implementation, and doesn't have its parent registered yet, we initialize the clk_core rate and 'req_rate' fields to 0. The rate field is later updated when the parent is registered in clk_core_reparent_orphans_nolock() using __clk_recalc_rates(), but the 'req_rate' field is never updated. This leads to an issue in clk_set_rate_range() and clk_put(), since those functions will call clk_set_rate() with the content of 'req_rate' to provide drivers with the opportunity to change the rate based on the new boundaries. In this case, we would call clk_set_rate() with a rate of 0, effectively enforcing the minimum allowed for this clock whenever we would call one of those two functions, even though the actual rate might be within range. Let's fix this by setting 'req_rate' in clk_core_reparent_orphans_nolock() with the rate field content just updated by the call to __clk_recalc_rates(). Fixes: 1c8e6004 ("clk: Add rate constraints to clocks") Reported-by:
Dmitry Osipenko <dmitry.osipenko@collabora.com> Tested-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> # T30 Nexus7 Signed-off-by:
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Krzysztof Kozlowski authored
Consumer examples in the bindings of resource providers are trivial, useless and duplication of code. Remove the example code for consumer Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Link: https://lore.kernel.org/r/20220316130858.93455-2-krzysztof.kozlowski@canonical.comAcked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Rob Herring authored
'clocks' in the example is not parsable with the 0 phandle value because the number of #clock-cells is unknown in the previous entry. Solve this by adding the clock provider node. Only 'cpg_clocks' is needed as the examples are built with fixups which can be used to identify phandles. This is in preparation to support schema validation on .dtb files. Signed-off-by:
Geert Uytterhoeven <geert@linux-m68k.org> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Acked-by:
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Konrad Dybcio authored
The gpll4 postdiv is actually a div4, so make sure that Linux is aware of this. This fixes the following error messages: mmc1: Card appears overclocked; req 200000000 Hz, actual 343999999 Hz mmc1: Card appears overclocked; req 400000000 Hz, actual 687999999 Hz Fixes: aec89f78 ("clk: qcom: Add support for msm8994 global clock controller") Signed-off-by:
Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20220319174940.341137-1-konrad.dybcio@somainline.orgTested-by:
Petr Vorel <petr.vorel@gmail.com> Reviewed-by:
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Ansuel Smith authored
qcom,gcc-other Documentation lacks a '|' for the description. This cause dt_binding_check to incorrectly parse "See also:" as a new value. Add the missing '|' to correctly parse the description. Fixes: a03965ed ("dt-bindings: clock: split qcom,gcc.yaml to common and specific schema") Signed-off-by:
Ansuel Smith <ansuelsmth@gmail.com> Link: https://lore.kernel.org/r/20220323194248.26970-1-ansuelsmth@gmail.comReviewed-by:
Krzysztof Kozlowski <krzk@kernel.org> Reported-by:
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- 18 Mar, 2022 2 commits
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Marek Vasut authored
Add driver for Renesas 9-series PCIe clock generators. This driver is designed to support 9FGV/9DBV/9DMV/9FGL/9DML/9QXL/9SQ series I2C PCIe clock generators, currently the only tested and supported chip is 9FGV0241. The driver is capable of configuring per-chip spread spectrum mode and output amplitude, as well as per-output slew rate. Signed-off-by:
Marek Vasut <marex@denx.de> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Stephen Boyd <sboyd@kernel.org> Cc: devicetree@vger.kernel.org Link: https://lore.kernel.org/r/20220226040723.143705-3-marex@denx.de [sboyd@kernel.org: Use non-underscore API for fixed factor] Signed-off-by:
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Marek Vasut authored
Add an API for a fixed factor clk that uses an index for the parent instead of a string name. This allows us to move drivers away from the string based method of describing parents and use the DT/firmware based method instead. Signed-off-by:
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- 15 Mar, 2022 10 commits
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Marek Vasut authored
Add binding for Renesas 9-series PCIe clock generators. This binding is designed to support 9FGV/9DBV/9DMV/9FGL/9DML/9QXL/9SQ series I2C PCIe clock generators, currently the only tested and supported chip is 9FGV0241. Signed-off-by:
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Julia Lawall authored
Various spelling mistakes in comments. Detected with the help of Coccinelle. Signed-off-by:
Julia Lawall <Julia.Lawall@inria.fr> Link: https://lore.kernel.org/r/20220314115354.144023-16-Julia.Lawall@inria.frSigned-off-by:
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Julia Lawall authored
Various spelling mistakes in comments. Detected with the help of Coccinelle. Signed-off-by:
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Abel Vesa authored
Most of the i.MX clock generic API is built by selecting MXC_CLK. Without it, the i.MX93 clock driver will fail to build: aarch64-linux-gnu-ld: drivers/clk/imx/clk-imx93.o: in function `imx93_clocks_probe': clk-imx93.c:(.text+0xa8): undefined reference to `imx_obtain_fixed_clk_hw' So fix this by selecting MXC_CLK for the CLK_IMX93. Fixes: 24defbe1 ("clk: imx: add i.MX93 clk") Signed-off-by:
Abel Vesa <abel.vesa@nxp.com> Reported-by:
kernel test robot <lkp@intel.com> Link: https://lore.kernel.org/r/20220315082446.3120850-1-abel.vesa@nxp.comReviewed-by:
Peng Fan <peng.fan@nxp.com> Signed-off-by:
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Tony Lindgren authored
We no longer have users for the compatibility clocks and we can drop them. These are old duplicate clocks for what we using. Depends-on: 31aa7056 ("ARM: dts: Don't use legacy clock defines for dra7 clkctrl") Depends-on: 9206a3af ("clk: ti: Move dra7 clock devices out of the legacy section") Cc: devicetree@vger.kernel.org Cc: Rob Herring <robh+dt@kernel.org> Signed-off-by:
Tony Lindgren <tony@atomide.com> Link: https://lore.kernel.org/r/20220203085618.16043-4-tony@atomide.comAcked-by:
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Tony Lindgren authored
We no longer have users for the compatibility clocks and we can drop them. These are old duplicate clocks for what we using. Cc: devicetree@vger.kernel.org Cc: Rob Herring <robh+dt@kernel.org> Signed-off-by:
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Tony Lindgren authored
We no longer have users for the compatibility clocks and we can drop them. These are old duplicate clocks for what we using. Cc: devicetree@vger.kernel.org Cc: Rob Herring <robh+dt@kernel.org> Signed-off-by:
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Stephen Boyd authored
We want to get commit 31aa7056 ("ARM: dts: Don't use legacy clock defines for dra7 clkctrl") so merge in the nearest rc.
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Stephen Boyd authored
Merge tag 'qcom-clk-for-5.18' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom Pull Qualcomm clk driver updates from Bjorn Andersson: This introduces support for A7 PLL on SDX65, GPU clock controller for SM6350, display clock controller for SM6125, SM6350 and QCS2290 and multimedia clock controller for MSM8226. The RPMCC drivers get support for SC8280XP and MSM8992, MSM8994 and MSM8998 gains some missing clocks. A new gcc DeviceTree binding is introduced, to allow platform-specific GCC bindings to inherit common properties. The SDM845 camera clock controller binding is converted to YAML. SDM845 camera clock controller, SDM660 GPU clock controller, IPQ8074 global clock controller, IPQ806x global clock controller, SC7180 camera and video clock controllers, MSM8996 globacl clock controller are converted to parent_data and/or parent_hws and cleanups related to this. Test clocks are removed from the SC7180, SDM845 camera clock controller drivers and SDM660 GPU clock controller driver. IPQ806x gains clocks and resets for CryptoEngine and additional frequencies for SDCC and NSS cores. Floor ops are introduced for RCG clocks and used for IPQ8074 SDCC clocks. SM8150 gains EMAC, PCIe and UFS GDSCs. The RCG2 logic for calculating D value is updated to support pixel clock frequencies on newer platforms. * tag 'qcom-clk-for-5.18' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (59 commits) clk: qcom: Add display clock controller driver for SM6125 dt-bindings: clock: add QCOM SM6125 display clock bindings clk: qcom: Fix sorting of SDX_GCC_65 in Makefile and Kconfig clk: qcom: gcc: Add emac GDSC support for SM8150 clk: qcom: gcc: sm8150: Fix some identation issues clk: qcom: gcc: Add UFS_CARD and UFS_PHY GDSCs for SM8150 clk: qcom: gcc: Add PCIe0 and PCIe1 GDSC for SM8150 clk: qcom: clk-rcg2: Update the frac table for pixel clock clk: qcom: clk-rcg2: Update logic to calculate D value for RCG clk: qcom: smd: Add missing MSM8998 RPM clocks clk: qcom: smd: Add missing RPM clocks for msm8992/4 dt-bindings: clock: qcom: rpmcc: Add RPM Modem SubSystem (MSS) clocks clk: qcom: gcc-ipq806x: add CryptoEngine resets dt-bindings: reset: add ipq8064 ce5 resets clk: qcom: gcc-ipq806x: add CryptoEngine clocks dt-bindings: clock: add ipq8064 ce5 clk define clk: qcom: gcc-ipq806x: add additional freq for sdc table clk: qcom: clk-rcg: add clk_rcg_floor_ops ops clk: qcom: gcc-ipq806x: add unusued flag for critical clock clk: qcom: gcc-ipq806x: add additional freq nss cores ...
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Martin Povišer authored
Signed-off-by:
Martin Povišer <povik+lin@cutebit.org> Link: https://lore.kernel.org/r/20220312135722.20770-1-povik+lin@cutebit.orgSigned-off-by:
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- 12 Mar, 2022 14 commits
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Martin Povišer authored
Acked-by:
Sven Peter <sven@svenpeter.dev> Acked-by:
Hector Martin <marcan@marcan.st> Signed-off-by:
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Martin Povišer authored
Add a common clock driver for NCO blocks found on Apple SoCs where they are typically the generators of audio clocks. Signed-off-by:
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Martin Povišer authored
The NCO block found on Apple SoCs is a programmable clock generator performing fractional division of a high frequency input clock. Reviewed-by:
Mark Kettenis <kettenis@openbsd.org> Reviewed-by:
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Daire McNamara authored
Add support for clock configuration on Microchip PolarFire SoC Reviewed-by:
Padmarao Begari <padmarao.begari@microchip.com> Signed-off-by:
Daire McNamara <daire.mcnamara@microchip.com> Co-developed-by:
Conor Dooley <conor.dooley@microchip.com> Signed-off-by:
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Kunihiko Hayashi authored
Fixed-rate clocks in UniPhier don't have any parent clocks, however, initial data "init.flags" isn't initialized, so it might be determined that there is a parent clock for fixed-rate clock. This sets init.flags to zero as initialization. Cc: <stable@vger.kernel.org> Fixes: 734d82f4 ("clk: uniphier: add core support code for UniPhier clock driver") Signed-off-by:
Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/1646808918-30899-1-git-send-email-hayashi.kunihiko@socionext.comSigned-off-by:
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Geert Uytterhoeven authored
The LAN966x Generic Clock Controller is only present on Microchip LAN966x SoCs. Hence add a dependency on SOC_LAN966, to prevent asking the user about this driver when configuring a kernel without LAN966x SoC support. Fixes: 54104ee0 ("clk: lan966x: Add lan966x SoC clock driver") Signed-off-by:
Horatiu Vultur <horatiu.vultur@microchip.com> Signed-off-by:
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Minghao Chi (CGEL ZTE) authored
Use of_device_get_match_data() to simplify the code. Reported-by:
Zeal Robot <zealci@zte.com.cn> Signed-off-by:
Minghao Chi (CGEL ZTE) <chi.minghao@zte.com.cn> Link: https://lore.kernel.org/r/20220303014856.2059307-1-chi.minghao@zte.com.cnAcked-by:
Neil Armstrong <narmstrong@baylibre.com> Signed-off-by:
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Maxime Ripard authored
Since commit 8ca011ef ("clk: bcm-2835: Remove rounding up the dividers"), the rem variable is still set but no longer used. Remove it. Fixes: 8ca011ef ("clk: bcm-2835: Remove rounding up the dividers") Reported-by:
Florian Fainelli <f.fainelli@gmail.com> Signed-off-by:
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Miaoqian Lin authored
The reference taken by 'of_find_device_by_node()' must be released when not needed anymore. Add the corresponding 'put_device()' in the error handling path. Fixes: 2db04f16 ("clk: tegra: Add EMC clock driver") Signed-off-by:
Miaoqian Lin <linmq006@gmail.com> Acked-by:
Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20220112104501.30655-1-linmq006@gmail.comSigned-off-by:
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Maxime Ripard authored
The core clock and M2MC clocks are shared between some devices (Unicam controllers and the HVS, and the HDMI controllers, respectively) that will have various, varying, requirements depending on their current work load. Since those loads can require a fairly high clock rate in extreme conditions (up to ~600MHz), we can end up running those clocks at their maximum frequency even though we no longer require such a high rate. Fortunately, those devices don't require an exact rate but a minimum rate, and all the drivers are using clk_set_min_rate. Thus, we can just rely on the fact that the clk_request minimum (which is the aggregated minimum of all the clock users) is what we want at all times. Signed-off-by:
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Maxime Ripard authored
The M2MC clock provides the state machine clock for both HDMI controllers. However, if no HDMI monitor is plugged in at boot, its clock rate will be left at 0 by the firmware and will make any register access end up in a CPU stall, even though the clock was enabled. We had some code in the HDMI controller to deal with this before, but it makes more sense to have it in the clock driver. Move it there. Signed-off-by:
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Maxime Ripard authored
We only export a bunch of firmware clocks, and some of them require special treatment. This has been do so far using some tests on the clock id in various places, but this is fairly hard to extend and doesn't scale very well. Since we'll need some more cases in the next patches, let's switch to a variant structure that defines the behaviour we need to have for a given clock. Signed-off-by:
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Maxime Ripard authored
In order to reset the range on a clock, we need to call clk_set_rate_range with a minimum of 0 and a maximum of ULONG_MAX. Since it's fairly inconvenient, let's introduce a clk_drop_range() function that will do just this. Suggested-by:
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Maxime Ripard authored
When we change a clock minimum or maximum using clk_set_rate_range(), clk_set_min_rate() or clk_set_max_rate(), the current code will only trigger a new rate change if the rate is outside of the new boundaries. However, a clock driver might want to always keep the clock rate to one of its boundary, for example the minimum to keep the power consumption as low as possible. Since they don't always get called though, clock providers don't have the opportunity to implement this behaviour. Let's trigger a clk_set_rate() on the previous requested rate every time clk_set_rate_range() is called. That way, providers that care about the new boundaries have a chance to adjust the rate, while providers that don't care about those new boundaries will return the same rate than before, which will be ignored by clk_set_rate() and won't result in a new rate change. Suggested-by:
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