1. 06 May, 2024 2 commits
    • Ho-Ren (Jack) Chuang's avatar
      memory tier: create CPUless memory tiers after obtaining HMAT info · cf93be18
      Ho-Ren (Jack) Chuang authored
      The current implementation treats emulated memory devices, such as CXL1.1
      type3 memory, as normal DRAM when they are emulated as normal memory
      (E820_TYPE_RAM).  However, these emulated devices have different
      characteristics than traditional DRAM, making it important to distinguish
      them.  Thus, we modify the tiered memory initialization process to
      introduce a delay specifically for CPUless NUMA nodes.  This delay ensures
      that the memory tier initialization for these nodes is deferred until HMAT
      information is obtained during the boot process.  Finally, demotion tables
      are recalculated at the end.
      
      * late_initcall(memory_tier_late_init);
        Some device drivers may have initialized memory tiers between
        `memory_tier_init()` and `memory_tier_late_init()`, potentially bringing
        online memory nodes and configuring memory tiers.  They should be
        excluded in the late init.
      
      * Handle cases where there is no HMAT when creating memory tiers
        There is a scenario where a CPUless node does not provide HMAT
        information.  If no HMAT is specified, it falls back to using the
        default DRAM tier.
      
      * Introduce another new lock `default_dram_perf_lock` for adist
        calculation In the current implementation, iterating through CPUlist
        nodes requires holding the `memory_tier_lock`.  However,
        `mt_calc_adistance()` will end up trying to acquire the same lock,
        leading to a potential deadlock.  Therefore, we propose introducing a
        standalone `default_dram_perf_lock` to protect `default_dram_perf_*`. 
        This approach not only avoids deadlock but also prevents holding a large
        lock simultaneously.
      
      * Upgrade `set_node_memory_tier` to support additional cases, including
        default DRAM, late CPUless, and hot-plugged initializations.  To cover
        hot-plugged memory nodes, `mt_calc_adistance()` and
        `mt_find_alloc_memory_type()` are moved into `set_node_memory_tier()` to
        handle cases where memtype is not initialized and where HMAT information
        is available.
      
      * Introduce `default_memory_types` for those memory types that are not
        initialized by device drivers.  Because late initialized memory and
        default DRAM memory need to be managed, a default memory type is created
        for storing all memory types that are not initialized by device drivers
        and as a fallback.
      
      Link: https://lkml.kernel.org/r/20240405000707.2670063-3-horenchuang@bytedance.comSigned-off-by: default avatarHo-Ren (Jack) Chuang <horenchuang@bytedance.com>
      Signed-off-by: default avatarHao Xiang <hao.xiang@bytedance.com>
      Reviewed-by: default avatar"Huang, Ying" <ying.huang@intel.com>
      Reviewed-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
      Cc: Alistair Popple <apopple@nvidia.com>
      Cc: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
      Cc: Dan Williams <dan.j.williams@intel.com>
      Cc: Dave Jiang <dave.jiang@intel.com>
      Cc: Gregory Price <gourry.memverge@gmail.com>
      Cc: Michal Hocko <mhocko@suse.com>
      Cc: Ravi Jonnalagadda <ravis.opensrc@micron.com>
      Cc: SeongJae Park <sj@kernel.org>
      Cc: Tejun Heo <tj@kernel.org>
      Cc: Vishal Verma <vishal.l.verma@intel.com>
      Cc: Jonathan Cameron <Jonathan.Cameron@huawie.com>
      Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
      cf93be18
    • Ho-Ren (Jack) Chuang's avatar
      memory tier: dax/kmem: introduce an abstract layer for finding, allocating,... · a72a30af
      Ho-Ren (Jack) Chuang authored
      memory tier: dax/kmem: introduce an abstract layer for finding, allocating, and putting memory types
      
      Patch series "Improved Memory Tier Creation for CPUless NUMA Nodes", v11.
      
      When a memory device, such as CXL1.1 type3 memory, is emulated as normal
      memory (E820_TYPE_RAM), the memory device is indistinguishable from normal
      DRAM in terms of memory tiering with the current implementation.  The
      current memory tiering assigns all detected normal memory nodes to the
      same DRAM tier.  This results in normal memory devices with different
      attributions being unable to be assigned to the correct memory tier,
      leading to the inability to migrate pages between different types of
      memory. 
      https://lore.kernel.org/linux-mm/PH0PR08MB7955E9F08CCB64F23963B5C3A860A@PH0PR08MB7955.namprd08.prod.outlook.com/T/
      
      This patchset automatically resolves the issues.  It delays the
      initialization of memory tiers for CPUless NUMA nodes until they obtain
      HMAT information and after all devices are initialized at boot time,
      eliminating the need for user intervention.  If no HMAT is specified, it
      falls back to using `default_dram_type`.
      
      Example usecase:
      We have CXL memory on the host, and we create VMs with a new system memory
      device backed by host CXL memory.  We inject CXL memory performance
      attributes through QEMU, and the guest now sees memory nodes with
      performance attributes in HMAT.  With this change, we enable the guest
      kernel to construct the correct memory tiering for the memory nodes.
      
      
      This patch (of 2):
      
      Since different memory devices require finding, allocating, and putting
      memory types, these common steps are abstracted in this patch, enhancing
      the scalability and conciseness of the code.
      
      Link: https://lkml.kernel.org/r/20240405000707.2670063-1-horenchuang@bytedance.com
      Link: https://lkml.kernel.org/r/20240405000707.2670063-2-horenchuang@bytedance.comSigned-off-by: default avatarHo-Ren (Jack) Chuang <horenchuang@bytedance.com>
      Reviewed-by: default avatar"Huang, Ying" <ying.huang@intel.com>
      Reviewed-by: default avatarJonathan Cameron <Jonathan.Cameron@huawie.com>
      Cc: Alistair Popple <apopple@nvidia.com>
      Cc: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
      Cc: Dan Williams <dan.j.williams@intel.com>
      Cc: Dave Jiang <dave.jiang@intel.com>
      Cc: Gregory Price <gourry.memverge@gmail.com>
      Cc: Hao Xiang <hao.xiang@bytedance.com>
      Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>
      Cc: Michal Hocko <mhocko@suse.com>
      Cc: Ravi Jonnalagadda <ravis.opensrc@micron.com>
      Cc: SeongJae Park <sj@kernel.org>
      Cc: Tejun Heo <tj@kernel.org>
      Cc: Vishal Verma <vishal.l.verma@intel.com>
      Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
      a72a30af
  2. 26 Apr, 2024 38 commits