- 18 Feb, 2010 10 commits
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Jerome Glisse authored
Get rid of _location and use _start/_end also simplify the computation of vram_start|end & gtt_start|end. For R1XX-R2XX we place VRAM at the same address of PCI aperture, those GPU shouldn't have much memory and seems to behave better when setup that way. For R3XX and newer we place VRAM at 0. For R6XX-R7XX AGP we place VRAM before or after AGP aperture this might limit to limit the VRAM size but it's very unlikely. For IGP we don't change the VRAM placement. Tested on (compiz,quake3,suspend/resume): PCI/PCIE:RV280,R420,RV515,RV570,RV610,RV710 AGP:RV100,RV280,R420,RV350,RV620(RPB*),RV730 IGP:RS480(RPB*),RS690,RS780(RPB*),RS880 RPB: resume previously broken V2 correct commit message to reflect more accurately the bug and move VRAM placement to 0 for most of the GPU to avoid limiting VRAM. Signed-off-by:
Jerome Glisse <jglisse@redhat.com> Signed-off-by:
Dave Airlie <airlied@redhat.com>
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Pauli Nieminen authored
r200 cards have dma engine which can be used to tranfer data between vram and system memory. r300 dma engine registers match r200 dma engine. Enabling dma copy for r200 is simple as hooking r200 asic to already existing function r300_copy_dma. Rename r300_dma_copy to r200_dma_copyto reflect that supports starts from r200 cards. v2: Created a new asic object for r200 cards. Signed-off-by:
Pauli Nieminen <suokkos@gmail.com> Signed-off-by:
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Pauli Nieminen authored
Setting global asic structure to point to different function would cause problem in system where is multiple r300 cards with different bus type. r300_asic_pcie is just copy from r300_asic with gart tlb functions replaced with pcie versions. Signed-off-by:
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Alex Deucher authored
r6xx/r7xx use the rs600 variant. This old one just confuses things. Signed-off-by:
Alex Deucher <alexdeucher@gmail.com> Signed-off-by:
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Alex Deucher authored
r600_ioctl_wait_idle() now handles this. v2: update blit fence counts Signed-off-by:
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Alex Deucher authored
fixes fdo bug 26358 Signed-off-by:
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Rafał Miłecki authored
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Rafał Miłecki authored
Fixes fdo bug #26329 Signed-off-by:
Rafał Miłecki <zajec5@gmail.com> Tested-by:
Tobias Jakobi <liquid.acid@gmx.net> Signed-off-by:
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Rafał Miłecki authored
We should stop audio-state-reading timer before we turn off engine Signed-off-by:
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Alex Deucher authored
drivers/gpu/drm/radeon/r600_cs.c: In function ‘r600_cs_track_check’: drivers/gpu/drm/radeon/r600_cs.c:166: warning: ‘bpe’ may be used uninitialized in this function drivers/gpu/drm/radeon/r600_cs.c:166: note: ‘bpe’ was declared here drivers/gpu/drm/radeon/r600_cs.c: In function ‘r600_cs_parse’: drivers/gpu/drm/radeon/r600_cs.c:938: warning: ‘bpe’ may be used uninitialized in this function drivers/gpu/drm/radeon/r600_cs.c:938: note: ‘bpe’ was declared here Signed-off-by:
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- 15 Feb, 2010 3 commits
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Jerome Glisse authored
Previous code did associate fence to bo before the fence was emited and it also didn't lock protected access to ttm sync_obj member. Both of this flaw leads to possible race between different code path. This patch fix this by associating fence only once the fence is emitted and properly lock protect access to sync_obj member of ttm. Fix: https://bugs.freedesktop.org/show_bug.cgi?id=26438 and likely similar others bugs Signed-off-by:
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Jerome Glisse authored
There is 3 different distinct states for an indirect buffer (IB) : 1- free with no fence 2- free with a fence 3- non free (fence doesn't matter) Previous code mixed case 2 & 3 in a single one leading to possible catastrophique failure. This patch rework the handling and properly separate each case. So when you get ib we set the ib as non free and fence status doesn't matter. Fence become active (ie has a meaning for the ib code) once the ib is scheduled or free. This patch also get rid of the alloc bitmap as it was overkill, we know go through IB pool list like in a ring buffer as the oldest IB is the first one the will be free. Fix : https://bugs.freedesktop.org/show_bug.cgi?id=26438 and likely other bugs. V2 remove the scheduled list, it's useless now, fix free ib scanning Signed-off-by:
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Dave Airlie authored
Suggested by Alex Deucher @ AMD Signed-off-by:
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- 11 Feb, 2010 9 commits
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Jerome Glisse authored
radeon_cs kfree the tracker structure but for r6xx/r7xx we want to kfree it inside the parse function because we share it with the UMS code path. Set tracker to NULL after freeing it will avoid double free. Signed-off-by:
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Dave Airlie authored
this uses a new entrypoint to invalidate gart entries instead of using 0. Changed to rather than pointing to 0 address point empty entry to dummy page. This might help to avoid hard lockup if for some wrong reasons GPU try to access unmapped GART entry. I'm not 100% sure this is going to work, we probably need to allocate a dummy page and point all the GTT entries at it similiar to what AGP does. but we can test this first I suppose. Signed-off-by:
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Dave Airlie authored
stops us trying to treat a OF rom as a PCI rom. Signed-off-by: -
Michel Dänzer authored
It's happened time and time again (most recently with the support for EDID hardcoded in the BIOS ROM) that new code didn't check for rdev->bios being non-NULL before triggering dereferences of it. This would result in an oops/panic on setups with no BIOS ROM. Hopefully this central test will be more robust. Signed-off-by:
Michel Dänzer <daenzer@vmware.com> Signed-off-by:
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Jerome Glisse authored
This patch add cs checker to r600/r700 hw. Command stream checking will rewrite some of the cs value in order to restrict GPU access to BO size. This doesn't break old userspace but just enforce safe value. It should break any things that was using the r600/r700 cs ioctl to do forbidden things (malicious software), though we are not aware of such things. Here is the list of thing we check : - enforcing resource size - enforcing color buffer slice tile max, will restrict cb access - enforcing db buffer slice tile max, will restrict db access We don't check for shader bigger than the BO in which they are supposed to be, such use would lead to GPU lockup and is harmless from security POV, as far as we can tell (note that even checking for this wouldn't prevent someone to write bogus shader that lead to lockup). This patch has received as much testing as humanly possible with old userspace to check that it didn't break such configuration. However not all the applications out there were tested, thus it might broke some odd, rare applications. [airlied: fix rules for cs checker for parallel builds] Signed-off-by:
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Alex Deucher authored
original evergreen patches we against a kernel tree without my radeon i2c algo changes. Signed-off-by:
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Alex Deucher authored
Fix a typo in crtc offset setup that set the crtc instances wrong for all crtcs except the first. Signed-off-by:
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Alex Deucher authored
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Alex Deucher authored
Pre-pcie chips seem to use the reference clock rather than the sclk. Signed-off-by:
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- 08 Feb, 2010 18 commits
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Alex Deucher authored
This adds initial Evergreen KMS support, it doesn't include any acceleration features or interrupt handling yet. Major changes are DCE4 handling for PLLs for the > 2 crtcs. Signed-off-by:
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Alex Deucher authored
This merges ugly whitespace we want to keep for consistency along with the latest upstream changes. Signed-off-by:
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Jerome Glisse authored
This add an utilities function radeon_ib_bogus_add which will save an ib into a list of ib which can then be dumped using debugfs. Once dumped the ib is removed from the list. This should allow to save & capute ib for further debugging. Signed-off-by:
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Rafał Miłecki authored
This already simplifies code significally and makes it maintaible in case of adding memory reclocking plus voltage changing in future. Signed-off-by:
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Dave Airlie authored
For usec delays use udelay instead of scheduling, this should allow reclocking to happen faster. Signed-off-by: -
Alex Deucher authored
we need a constant sclk for i2c prescale. Also, get the current sclk when calculating prescale rather than using the default sclk. Signed-off-by:
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Alex Deucher authored
- only r4xx/r5xx/rs6xx/rs740 have clock gating atom table, so disable it on r6xx. it's already disabled on r7xx - check to make sure the clock_gating hook exists before calling it. This avoids a segfault on asics without that function. - remove unused static power management function. Signed-off-by:
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Rafał Miłecki authored
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Alex Deucher authored
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Alex Deucher authored
not hooked up yet. Signed-off-by:
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Alex Deucher authored
The idea is to flag a power state with a certain type and use that type to decide on what state to select. On r6xx+, we select a state and then transition between clock modes in that state. On pre-r6xx, we transition between states directly. Signed-off-by:
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Rafał Miłecki authored
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Alex Deucher authored
The general idea is to validate the current hw state against the set of power states and select a power state based on that. This patch just pulls the power states from the bios and prints the information. It is not currently hooked up in the actual power management code. Hooking it up will require reworking the the current power state selection code and will be handled in a future patch. Additionally, we'd need to decide on some default lower power states for cards without power tables. v2 - increment state_index after checking for default state v3 - fix typo in pm init on pre-atom cards, handle pre-atom cards without x86 bioses Signed-off-by:
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Alex Deucher authored
Currently unused. Signed-off-by:
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Rafał Miłecki authored
V2: reorganize functions, fix modesetting calls V3: rebase patch, use radeon's workqueue V4: enable on tested chipsets only, request VBLANK IRQs V5: enable PM on older hardware (IRQs, mode_fixup, dpms) V6: use separate dynpm module parameter V7: drop RADEON_ prefix, set minimum mode for dpms off V8: update legacy encoder call, fix order in rs600 IRQ V9: update compute_clocks call in legacy, not only DPMS_OFF Signed-off-by:
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Alex Deucher authored
Set the number of crtcs in rdev at crtc init and use it whenever we need the crtc count rather than recalculating it everytime. Signed-off-by:
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Alex Deucher authored
Only flush the gpu caches before we submit a fence. This leads to a small performance boost when we take the extra gpu cache flushes out of the ddx and mesa. Once this patch is in and the drm version is bumped, we can remove the flushes from the ddx and drm. Also, remove the extra cache flushes from the blit routine. Signed-off-by:
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Dave Airlie authored
Internal locking should be sufficent for all these cases. Signed-off-by:
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