1. 05 Jun, 2014 7 commits
    • Daniel Vetter's avatar
      drm/i915: Extract gen8_gt_irq_reset · d6e3cca3
      Daniel Vetter authored
      Fallout from an intermediate patch revision that I deemed worth saving.
      
      Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
      Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      d6e3cca3
    • Daniel Vetter's avatar
      drm/i915: Improve irq handling after gpu resets · 78ad455f
      Daniel Vetter authored
      Currently we do a full re-init of all interrupts after a gpu hang.
      Which is pretty bad since we don't restore the interrupts we've
      enabled at runtime correctly. Even with that addressed it's rather
      horribly race.
      
      But on g4x and later we only reset the gt and not the entire gpu.
      Which means we only need to reset the GT interrupt bits. Which has the
      nice benefit that vblank waits, pipe CRC interrupts and everything
      else display related just keeps on working.
      
      The downside is that gt interrupt handling (i.e. ring->get/put_irq) is
      still racy. But as long as the gpu hang reliably wakes all waters and
      we have a short time where the refcount drops to 0 we'll recover. So
      not that bad really.
      
      v2: Ville noticed that GTIMR and PMIMR don't get cleared, only the
      subordinate per-ring registers. So let's rip out all the interrupt dancing.
      The FIXME comment is still required though since the ring irq handling
      happens at the per-ring interrupt mask registers, too.
      
      Testcase: igt/kms_flip/vblank-vs-hang
      Testcase: igt/kms_pipe_crc_basic/hang-*
      Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
      Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      78ad455f
    • Daniel Vetter's avatar
      drm/i915: Inline ilk/gen8_irq_reset · 723761b8
      Daniel Vetter authored
      No point in having this indirection.
      Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      723761b8
    • Daniel Vetter's avatar
      drm/i915: Disable gpu reset on i965g/gm · 85ab3998
      Daniel Vetter authored
      Ville figured out that it needs a full display reset since apparently
      a lot more goes down than just the GT. Until that's address it's
      better to just diable gpu reset.
      Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      85ab3998
    • Daniel Vetter's avatar
      drm/i915: Fix up fifo underrun tracking, take N · 2ae2a50c
      Daniel Vetter authored
      So apparently this is tricky.
      
      We need to consider:
      - We start out with all the hw enabling bits disabled, both the
        individual fifo underrun interrupts and the shared display error
        interrupts masked. Otherwise if the bios config is broken we'll blow
        up with a NULL deref in our interrupt handler since the crtc
        structures aren't set up yet at driver load time.
      - On gmch we need to mask fifo underruns on the sw side, so always
        need to set that in sanitize_crtc for those platforms.
      - On other platforms we try to set the sw tracking so that it reflects
        the real state. But since a few platforms have shared bits we must
        _not_ disable fifo underrun reporting. Otherwise we'll never enable
        the shared error interrupt.
      
      This is the state before out patch, but unfortunately this is not good
      enough. But after a suspend resume operation this is broken:
      1. We don't enable the hw interrupts since the same code runs on
      resume as on driver load.
      2. The fifo underrun state adjustments we do in sanitize_crtc doesn't
      fire on resume since (except for hilarious firmware) all pipes are off
      at that point. But they also don't hurt since the subsequent crtc
      enabling due to force_restore will enable fifo underruns.
      
      Which means when we enable fifo underrun reporting we notice that the
      per-crtc state is already correct and short-circuit everthing out. And
      the interrupt doesn't get enabled.
      
      A similar problem would happen if the bios doesn't light up anything
      when the driver loads. Which is exactly what happens when we reload
      the driver since our unload functions disables all outputs.
      
      Now we can't just rip out the short-circuit logic and unconditionally
      update the fifo underrun reporting interrupt masking: We have some
      checks for shared error interrupts to catch issues that happened when
      the shared error interrupt was disabled.
      
      The right fix is to push down this logic so that we can always update
      the hardware state, but only check for missed fifo underruns on a real
      enabled->disabled transition and ignore them when we're already
      disabled.
      
      On platforms with shared error interrupt the pipe CRC interrupts are
      grouped together with the fifo underrun reporting this fixes pipe CRC
      support after suspend and driver reloads.
      
      Testcase: igt/kms_pipe_crc_basic/suspend-*
      Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      2ae2a50c
    • Daniel Vetter's avatar
      drm/i915: Add fifo underrun reporting state to debugfs · cace841c
      Daniel Vetter authored
      On platforms with shared interrupt enable bits (which are shared even
      with the pipe CRC logic) there's some tricky corner cases. Add
      information to make debugging those easier.
      Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      cace841c
    • Rob Clark's avatar
      drm: add drm_fb_helper_restore_fbdev_mode_unlocked() · 5ea1f752
      Rob Clark authored
      All drm_fb_helper_restore_fbdev_mode() call sites, save one, do the same
      locking.  Simplify this into drm_fb_helper_restore_fbdev_mode_unlocked().
      Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
      Reviewed-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
      5ea1f752
  2. 04 Jun, 2014 23 commits
  3. 03 Jun, 2014 1 commit
    • Dave Airlie's avatar
      Merge branch 'drm-next-3.16' of git://people.freedesktop.org/~agd5f/linux into drm-next · 5536141d
      Dave Airlie authored
      Highlights:
      - GPUVM opimtizations
      - HDMI audio cleanups
      - Deep color HDMI support
      - more bug fixes, cleanups
      
      * 'drm-next-3.16' of git://people.freedesktop.org/~agd5f/linux: (29 commits)
        drm/edid: Add quirk for Sony PVM-2541A to get 12 bpc hdmi deep color.
        drm/edid: Parse and handle HDMI deep color modes.
        drm/radeon: Limit hdmi deep color bit depth to 12 bpc.
        drm/radeon: Setup HDMI_CONTROL for hdmi deep color gcp's (v2)
        drm/radeon: fix pll setup for hdmi deep color (v7)
        drm/radeon: use hw cts/n values for deep color
        drm/radeon: only apply hdmi bpc pll flags when encoder mode is hdmi
        drm/radeon/atom: fix dithering on certain panels
        drm/radeon: optimize CIK VM handling v2
        drm/radeon: optimize SI VM handling
        drm/radeon: add define for flags used in R600+ GTT
        drm/radeon: rework page flip handling v3
        drm/radeon: separate vblank and pflip crtc handling
        drm/radeon: split page flip and pending callback
        drm/radeon: remove drm_vblank_get|put from pflip handling
        drm/radeon: remove (pre|post)_page_flip callbacks
        drm/radeon/dp: fix lane/clock setup for dp 1.2 capable devices
        drm/radeon: fix typo in radeon_connector_is_dp12_capable()
        radeon: Remove useless quirk for zx1/FireGL X1 combo introduced with fdo #7770
        vgaswitcheroo: switch the mux to the igp on power down when runpm is enabled
        ...
      5536141d
  4. 02 Jun, 2014 9 commits