- 17 Nov, 2023 40 commits
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Anthony Koo authored
[WHY & HOW] Add new command to disable replay timing resync Acked-by:
Alex Hung <alex.hung@amd.com> Signed-off-by:
Anthony Koo <anthony.koo@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Fangzhi Zuo authored
[WHY & HOW] When dsc is possible, MST mode validation includes: 1. if maximum dsc compression cannot fit into end to end bw, mode pruned 2. if native bw cannot fit into end to end bw, try to enabled dsc to see whether a feasible dsc config can be found 3. if native bw can fit into end to end bw, mode supported Reviewed-by:
Wayne Lin <wayne.lin@amd.com> Acked-by:
Fangzhi Zuo <jerry.zuo@amd.com> Tested-by:
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Krunoslav Kovac authored
[WHY & HOW] PB9 bit 5 was added to signal PQ EOTF in AMD vendor specific infoframe. This change sets it when appropriate. Reviewed-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
Krunoslav Kovac <krunoslav.kovac@amd.com> Tested-by:
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Duncan Ma authored
[WHY] Driver continues running whenever there is is timeout from smu or dmcub. It is difficult to track failure state when dcn, dc or dmcub changes on root failure. [HOW] Add disable_timeout option to halt driver whenever there is a failure in response. Reviewed-by:
Charlene Liu <charlene.liu@amd.com> Acked-by:
Duncan Ma <duncan.ma@amd.com> Tested-by:
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Daniel Miess authored
[WHY & HOW] Enable DCN clock gating for DCN35. Disable DTBCLK gate before link training and re-enable afterwards Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by:
Daniel Miess <daniel.miess@amd.com> Tested-by:
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Wenjing Liu authored
[WHY & HOW] When acquiring an OTG master pipe we should prefer currently enabled OTG master pipes first. If there are no free pipes used as current OTG master pipe then we will try to acquire a currently unused free pipe as new OTG master instead of tearing down current secondary pipes from ODM or MPC combine. Reviewed-by:
Alvin Lee <alvin.lee2@amd.com> Reviewed-by:
Dillon Varone <dillon.varone@amd.com> Acked-by:
Wenjing Liu <wenjing.liu@amd.com> Tested-by:
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Wenjing Liu authored
[WHY & HOW] The current otg master pipe allocation logic is not optimized based current resource context. We should try to acquire a free OTG master not used in cur cts first to avoid unnecessary pipe switch from current state. Acked-by:
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Mounika Adhuri authored
[WHY] Move all resource files to unique folder resource. [HOW] Created resource folder in dc, moved the dcnxx_resource.c and dcnxx_resource.h files into corresponding new folders inside the resource and made appropriate changes for compilation in Makefiles. Reviewed-by:
Martin Leung <martin.leung@amd.com> Acked-by:
Mounika Adhuri <moadhuri@amd.com> Tested-by:
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Hamza Mahfooz authored
For features that are implemented primarily in DMUB (e.g. PSR), it is useful to be able to trace them at a DMUB level from the kernel, especially when debugging issues. So, introduce a debugfs interface that is able to read and set the DMUB trace mask dynamically at runtime and document how to use it. Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
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Yihan Zhu authored
[WHY & HOW] MPC MCM low mem power optimization still causes color distortion on first SCE enablement, only forces light sleep for it. DPP low memory power optimization still needs this bit to save power. Reviewed-by:
Yihan Zhu <yihan.zhu@amd.com> Tested-by:
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Yang Wang authored
correct mca ipid die/socket/addr decode v2: squash in fix from Yang Signed-off-by:
Yang Wang <kevinyang.wang@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Aurabindo Pillai authored
[WHY & HOW] Check whether get_subvp_en() callback exists before calling it. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by:
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Laurent Morichetti authored
The trap handler could be entered with pending VALU exceptions, so clear the exception state before issuing vector instructions. Reviewed-by:
Jay Cornwall <jay.cornwall@amd.com> Acked-by:
Laurent Morichetti <laurent.morichetti@amd.com> Tested-by:
Lancelot Six <lancelot.six@amd.com> Signed-off-by:
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Srinivasan Shanmugam authored
Fixes the below: WARNING: Prefer 'unsigned int' to bare use of 'unsigned' WARNING: Missing a blank line after declarations WARNING: Too many leading tabs - consider code refactoring + if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) { WARNING: Too many leading tabs - consider code refactoring + if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { Cc: Guchun Chen <guchun.chen@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Pan, Xinhui" <Xinhui.Pan@amd.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Acked-by:
Guchun Chen <guchun.chen@amd.com> Reviewed-by:
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Ma Jun authored
smu_v13_0_baco_set_armd3_sequence is not used by other files, so make it as static type. Signed-off-by:
Ma Jun <Jun.Ma2@amd.com> Reviewed-by:
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Ma Jun authored
Use generic functions and remove the duplicate code Signed-off-by:
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Abhinav Singh authored
sparse static analysis tools generate a warning with this message "Using plain integer as NULL pointer". In this case this warning is being shown because we are trying to intialize a pointer to NULL using integer value 0. Signed-off-by:
Abhinav Singh <singhabhinav9051571833@gmail.com> Signed-off-by:
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Sam James authored
GCC 14 introduces a new -Walloc-size included in -Wextra which errors out on various files in drivers/gpu/drm/amd/amdgpu like: ``` amdgpu_amdkfd_gfx_v8.c:241:15: error: allocation of insufficient size ‘4’ for type ‘uint32_t[2]’ {aka ‘unsigned int[2]'} with size ‘8’ [-Werror=alloc-size] ``` This is because each HQD_N_REGS is actually a uint32_t[2]. Move the * 2 to the size argument so GCC sees we're allocating enough. Originally did 'sizeof(uint32_t) * 2' for the size but a friend suggested 'sizeof(**dump)' better communicates the intent. Link: https://lore.kernel.org/all/87wmuwo7i3.fsf@gentoo.org/Signed-off-by:Sam James <sam@gentoo.org> Signed-off-by:
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Ma Jun authored
Fix the return value and drop redundant parameter of get_asic_baco_capability function. Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Signed-off-by:
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Felix Kuehling authored
This will make it possible for amdgpu GEM ioctls to flush TLBs on compute VMs. This removes VMID-based TLB flushing and always uses PASID-based flushing. This still works because it scans the VMID-PASID mapping registers to find the right VMID. It's only slightly less efficient. This is not a production use case. Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
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Felix Kuehling authored
When restoring after an eviction, use amdgpu_vm_handle_moved to update BO VA mappings in KFD VMs that are not managed through the KFD API. This should allow using the render node API to create more flexible memory mappings in KFD VMs. v2: rebase on drm_exec changes (Alex) Signed-off-by:
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Arunpravin Paneer Selvam authored
Developed a new driver which allocates a 64bit memory on each request in sequence order. At the moment, user queue fence memory is the main consumer of this seq64 driver. v2: Worked on review comments from Christian for the following modifications - Move driver name from "semaphore" to "seq64" - Remove unnecessary PT/PD mapping - Move enable_mes check into init/fini functions. v3: Worked on review comments from Christian - drop enable_mes check - use DECLARE_BITMAP for bit array - added kerneldoc for seq64 v4: Worked on review comments from Christian - Rename amdgpu_seq64_get name with amdgpu_seq64_alloc v5: Worked on review comments from Christian - Fix seq64 lockdep warning - move fpriv->seq64_va check into amdgpu_seq64_unmap() - make the function amdgpu_seq64_unmap() return as void. - reserve the buffers as not interruptible. v6: port to drm_exec (Alex) v7: disable for now (Arun) Signed-off-by:Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com> Reviewed-by:
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Alex Deucher authored
We've had misc reports of random IOMMU page faults when this is used. It's just a rarely used optimization anyway, so let's just disable it. It can still be toggled via the module parameter for testing. v2: leave it configurable via module parameter Reviewed-by: Yang Wang <kevinyang.wang@amd.com> (v1) Acked-by:
Mario Limonciello <mario.limonciello@amd.com> Tested-by: Mario Limonciello <mario.limonciello@amd.com> # PHX & Navi33 Signed-off-by:
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Alex Deucher authored
We've had misc reports of random IOMMU page faults when this is used. It's just a rarely used optimization anyway, so let's just disable it. It can still be toggled via the module parameter for testing. v2: leave it configurable via module parameter Reviewed-by: Yang Wang <kevinyang.wang@amd.com> (v1) Acked-by:
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Alex Deucher authored
We've had misc reports of random IOMMU page faults when this is used. It's just a rarely used optimization anyway, so let's just disable it. It can still be toggled via the module parameter for testing. v2: leave it configurable via module parameter Fixes: 67318cb8 ("drm/amdgpu/gmc11: set gart placement GC11") Reviewed-by: Yang Wang <kevinyang.wang@amd.com> (v1) Acked-by:
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Alex Deucher authored
Add a module parameter to control the AGP aperture. The AGP aperture is an aperture in the GPU's internal address space which provides direct non-paged access to the platform address space. This access is non-snooped so only uncached memory can be accessed. Add a knob so that we can toggle this for debugging. Fixes: 67318cb8 ("drm/amdgpu/gmc11: set gart placement GC11") Acked-by:
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Alex Deucher authored
Should be && rather than ||. Fixes: b2e1cbe6 ("drm/amdgpu/gmc11: disable AGP on GC 11.5") Acked-by:
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Nicholas Susanto authored
[WHY] DENTIST hangs when OTG is off and encoder is on. We were not disabling the encoder properly when switching from extended mode to external monitor only. [HOW] Disable the encoder using an existing enable/disable fifo helper instead of enc35_stream_encoder_enable. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by:
Nicholas Susanto <nicholas.susanto@amd.com> Tested-by:
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Lewis Huang authored
[WHY] Flush command sent to DMCUB spends more time for execution on a dGPU than on an APU. This causes cursor lag when using high refresh rate mouses. [HOW] 1. Change the DMCUB mailbox memory location from FB to inbox. 2. Only change windows memory to inbox. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by:
Lewis Huang <lewis.huang@amd.com> Tested-by:
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Shiwu Zhang authored
The port num info is firstly introduced with 20.00.01.13 xgmi ta and make them as part of topology info. Signed-off-by:
Shiwu Zhang <shiwu.zhang@amd.com> Reviewed-by:
Le Ma <le.ma@amd.com> Signed-off-by:
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Duncan Ma authored
[WHY] On s0i3, IPS mask isn't saved and restored. It is reset to zero on exit. If it is cleared unexpectedly, driver will proceed operations while DCN is in IPS2 and cause a hang. [HOW] Negate the bit logic. Default value of zero indicates it is still in IPS2. Driver must poll for the bit to assert. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by:
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Lijo Lazar authored
No need to notify about unload during reset. Also remove the FW version check. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Asad Kamal <asad.kamal@amd.com> Signed-off-by:
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Yang Wang authored
fix ras err_data null pointer issue in amdgpu_ras.c Fixes: 8cc0f566 ("drm/amdgpu: Support multiple error query modes") Signed-off-by:
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Paul Hsieh authored
[WHY] Some eDP panels' ext caps don't set initial values and the value of dpcd_addr (0x317) is random. It means that sometimes the eDP can be OLED, miniLED and etc, and cause incorrect backlight control interface. [HOW] Add remove_sink_ext_caps to remove sink ext caps (HDR, OLED and etc) Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by:
Paul Hsieh <paul.hsieh@amd.com> Tested-by:
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Tianci Yin authored
[WHY] When cursor moves across screen boarder, lag cursor observed, since subvp settings need to sync up with vblank that causes cursor updates being delayed. [HOW] Enable fast plane updates on DCN3.2 to fix it. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by:
Tianci Yin <tianci.yin@amd.com> Tested-by:
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José Pekkarinen authored
The following patch will fix a minor issue where a debug message is referencing an struct that has just being checked whether is null or not. This has been noticed by using coccinelle, in the following output: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c:540:25-29: ERROR: aconnector is NULL but dereferenced. Fixes: 5d72e247 ("drm/amd/display: switch DC over to the new DRM logging macros") Signed-off-by:
José Pekkarinen <jose.pekkarinen@foxhound.fi> Signed-off-by:
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Mario Limonciello authored
When ddc_service_construct() is called, it explicitly checks both the link type and whether there is something on the link which will dictate whether the pin is marked as hw_supported. If the pin isn't set or the link is not set (such as from unloading/reloading amdgpu in an IGT test) then fail the amdgpu_dm_i2c_xfer() call. Cc: stable@vger.kernel.org Fixes: 22676bc5 ("drm/amd/display: Fix dmub soft hang for PSR 1") Link: https://github.com/fwupd/fwupd/issues/6327Signed-off-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Muhammad Ahmed authored
[WHY & HOW] Add some null checks to fix an issue where 8k60 tiled display fails to light up. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by:
Muhammad Ahmed <ahmed.ahmed@amd.com> Tested-by:
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Asad Kamal authored
Fill PCIE error counters & instantaneous bandwidth in gpu metrics v1_4 for smu v_13_0_6 Signed-off-by:
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Asad Kamal authored
Update pmfw metric table to include pcie instantaneous bandwidth & pcie error counters Signed-off-by:
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