- 09 Jun, 2023 19 commits
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Mukul Joshi authored
Use the helper function in TTM to get TTM mem limit and set GTT size to be equal to TTL mem limit. Signed-off-by:
Mukul Joshi <mukul.joshi@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Mukul Joshi authored
Add a helper function to get TTM memory limit. This is needed by KFD to set its own internal memory limits. Signed-off-by:
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Guchun Chen authored
This was left global by accident, the corresponding functions for other hardware types are already static: drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c:1072:6: error: no previous prototype for function 'gfx_v9_4_3_disable_gpa_mode' [-Werror,-Wmissing-prototypes] Fixes: 86301129 ("drm/amdgpu: split gc v9_4_3 functionality from gc v9_0") Reported-by:
kernel test robot <lkp@intel.com> Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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Guchun Chen authored
Instead of the default one, check the right mqd_backup object. Signed-off-by:
Le Ma <le.ma@amd.com> Signed-off-by:
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Guchun Chen authored
This should be a typo when intruducing multi-xx support. Reported-by:
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Tom Rix authored
gcc with W=1 reports drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dmub_srv.c: In function ‘dc_dmub_srv_optimized_init_done’: drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dmub_srv.c:184:26: error: variable ‘dmub’ set but not used [-Werror=unused-but-set-variable] 184 | struct dmub_srv *dmub; | ^~~~ The return status is never set. It looks like a call to dmub_srv_get_fw_boot_status is missing. Fixes: 499e4b1c ("drm/amd/display: add mechanism to skip DCN init") Signed-off-by:Tom Rix <trix@redhat.com> Signed-off-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
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Tom Rix authored
smatch reports drivers/gpu/drm/amd/amdgpu/../display/modules/power/power_helpers.c:119:31: warning: symbol 'custom_backlight_curve0' was not declared. Should it be static? This variable is only used in its defining file, so it should be static Signed-off-by:
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Horatio Zhang authored
The gmc.ecc_irq is enabled by firmware per IFWI setting, and the host driver is not privileged to enable/disable the interrupt. So, it is meaningless to use the amdgpu_irq_put function in gmc_v10_0_hw_fini, which also leads to the call trace. [ 82.340264] Call Trace: [ 82.340265] <TASK> [ 82.340269] gmc_v10_0_hw_fini+0x83/0xa0 [amdgpu] [ 82.340447] gmc_v10_0_suspend+0xe/0x20 [amdgpu] [ 82.340623] amdgpu_device_ip_suspend_phase2+0x127/0x1c0 [amdgpu] [ 82.340789] amdgpu_device_ip_suspend+0x3d/0x80 [amdgpu] [ 82.340955] amdgpu_device_pre_asic_reset+0xdd/0x2b0 [amdgpu] [ 82.341122] amdgpu_device_gpu_recover.cold+0x4dd/0xbb2 [amdgpu] [ 82.341359] amdgpu_debugfs_reset_work+0x4c/0x70 [amdgpu] [ 82.341529] process_one_work+0x21d/0x3f0 [ 82.341535] worker_thread+0x1fa/0x3c0 [ 82.341538] ? process_one_work+0x3f0/0x3f0 [ 82.341540] kthread+0xff/0x130 [ 82.341544] ? kthread_complete_and_exit+0x20/0x20 [ 82.341547] ret_from_fork+0x22/0x30 Signed-off-by:
Horatio Zhang <Hongkun.Zhang@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
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Horatio Zhang authored
The gmc.ecc_irq is enabled by firmware per IFWI setting, and the host driver is not privileged to enable/disable the interrupt. So, it is meaningless to use the amdgpu_irq_put function in gmc_v11_0_hw_fini, which also leads to the call trace. [ 102.980303] Call Trace: [ 102.980303] <TASK> [ 102.980304] gmc_v11_0_hw_fini+0x54/0x90 [amdgpu] [ 102.980357] gmc_v11_0_suspend+0xe/0x20 [amdgpu] [ 102.980409] amdgpu_device_ip_suspend_phase2+0x240/0x460 [amdgpu] [ 102.980459] amdgpu_device_ip_suspend+0x3d/0x80 [amdgpu] [ 102.980520] amdgpu_device_pre_asic_reset+0xd9/0x490 [amdgpu] [ 102.980573] amdgpu_device_gpu_recover.cold+0x548/0xce6 [amdgpu] [ 102.980687] amdgpu_debugfs_reset_work+0x4c/0x70 [amdgpu] [ 102.980740] process_one_work+0x21f/0x3f0 [ 102.980741] worker_thread+0x200/0x3e0 [ 102.980742] ? process_one_work+0x3f0/0x3f0 [ 102.980743] kthread+0xfd/0x130 [ 102.980743] ? kthread_complete_and_exit+0x20/0x20 [ 102.980744] ret_from_fork+0x22/0x30 Signed-off-by:
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Shane Xiao authored
[Why] The selfring doorbell aperture will change when resize FB BAR successfully during gmc sw init, we should reorder the sequence of enabling doorbell selfring aperture. [How] Move enable_doorbell_selfring_aperture from *_common_hw_init to *_common_late_init. This fixes the potential issue that GPU ring its own doorbell when this device is in translated mode when iommu is on. v2: Remove *_enable_doorbell_aperture functions (Christian) v3: Add comments to note that why we need enable doorbell selfring late (Christian) Signed-off-by:Shane Xiao <shane.xiao@amd.com> Signed-off-by:
Aaron Liu <aaron.liu@amd.com> Tested-by:
Xiaomeng Hou <Xiaomeng.Hou@amd.com> Reviewed-by:
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Srinivasan Shanmugam authored
Fix following checkpatch errors in amdgpu_display.c ERROR: spaces required around that '=' (ctx:VxW) ERROR: that open brace { should be on the previous line ERROR: else should follow close brace '}' Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by:Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by:
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Srinivasan Shanmugam authored
if check over DSC passthrough is removed, as this is not for MST use case. It is for DP-HDMI pcon use case. sst pcon is detected as sst not mst. In sst pcon dsc passthrough message will not get below log printed Fixes: 9b035d08 ("drm/amd/display: Check & log if receiver supports MST, DSC & FEC.") Suggested-by:
Fangzhi Zuo <Jerry.Zuo@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
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lyndonli authored
Below call trace and errors are observed when reloading amdgpu driver with the module parameter reset_method=3. It should do a default reset when loading or reloading the driver, regardless of the module parameter reset_method. v2: add comments inside and modify commit messages. [ +2.180243] [drm] psp gfx command ID_LOAD_TOC(0x20) failed and response status is (0x0) [ +0.000011] [drm:psp_hw_start [amdgpu]] *ERROR* Failed to load toc [ +0.000890] [drm:psp_hw_start [amdgpu]] *ERROR* PSP tmr init failed! [ +0.020683] [drm:amdgpu_fill_buffer [amdgpu]] *ERROR* Trying to clear memory with ring turned off. [ +0.000003] RIP: 0010:amdgpu_bo_release_notify+0x1ef/0x210 [amdgpu] [ +0.000004] Call Trace: [ +0.000003] <TASK> [ +0.000008] ttm_bo_release+0x2c4/0x330 [amdttm] [ +0.000026] amdttm_bo_put+0x3c/0x70 [amdttm] [ +0.000020] amdgpu_bo_free_kernel+0xe6/0x140 [amdgpu] [ +0.000728] psp_v11_0_ring_destroy+0x34/0x60 [amdgpu] [ +0.000826] psp_hw_init+0xe7/0x2f0 [amdgpu] [ +0.000813] amdgpu_device_fw_loading+0x1ad/0x2d0 [amdgpu] [ +0.000731] amdgpu_device_init.cold+0x108e/0x2002 [amdgpu] [ +0.001071] ? do_pci_enable_device+0xe1/0x110 [ +0.000011] amdgpu_driver_load_kms+0x1a/0x160 [amdgpu] [ +0.000729] amdgpu_pci_probe+0x179/0x3a0 [amdgpu] Signed-off-by:
lyndonli <Lyndon.Li@amd.com> Signed-off-by:
Yunxiang Li <Yunxiang.Li@amd.com> Reviewed-by:
Feifei Xu <Feifei.Xu@amd.com> Reviewed-by:
Kenneth Feng <kenneth.feng@amd.com> Signed-off-by:
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lyndonli authored
Before this change, sienna_cichlid_get_reset_handler will always return NULL, although the module parameter reset_method is 3 when loading amdgpu driver. Signed-off-by:
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Pierre-Eric Pelloux-Prayer authored
OpenGL EXT_robustness extension expects the driver to stop reporting GUILTY_CONTEXT_RESET when the reset has completed and the GPU is ready to accept submission again. This commit adds a AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS flag, that let the UMD know that the reset is still not finished. Mesa MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22290Reviewed-by:
André Almeida <andrealmeid@igalia.com> Signed-off-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Signed-off-by:
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Christophe JAILLET authored
It is likely p1_min_meta_chunk_bytes was expected here, instead of min_meta_chunk_bytes. Test the correct variable. Fixes: dda4fb85 ("drm/amd/display: DML changes for DCN32/321") Signed-off-by:
Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by:
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Christophe JAILLET authored
It is likely Height was expected here, instead of Width. Test the correct variable. Fixes: 17529ea2 ("drm/amd/display: Optimizations for DML math") Signed-off-by:
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Sukrut Bellary authored
smatch warning - inconsistent handling of buffer object reserve and unreserve. Reviewed-by:
Sukrut Bellary <sukrut.bellary@linux.com> Signed-off-by:
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Tom Rix authored
clang with W=1 reports drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn314/display_rq_dlg_calc_314.c:1003:15: error: variable 'dispclk_delay_subtotal' set but not used [-Werror,-Wunused-but-set-variable] unsigned int dispclk_delay_subtotal; ^ This variable is not used, so remove it. Which made dout unused, so also remove. Signed-off-by:
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- 24 Apr, 2023 21 commits
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Alex Deucher authored
This code was written prior to previous updates to this logic for other chips. The RSC registers are part of SMUIO which is an always on block so there is no need to disable gfxoff. Additionally add the carryover and preemption checks. v2: rebase Reviewed-by:
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Likun Gao authored
Add support for PSP vbflash sysfs interface with MP0 version v13.0.10. Signed-off-by:
Likun Gao <Likun.Gao@amd.com> Reviewed-by:
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Aurabindo Pillai authored
This reverts commit 80c6d680. The orignal commit was intended as a workaround to prevent underflow and flickering when using one normal monitor and the other high refresh rate monitor (> 120Hz). This patch is being reverted in favour of a software solution to enable SubVP+DRR Signed-off-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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Aric Cyr authored
This DC version brings along: - Improvements in the SubVP feature - Keep disable aux-i delay as 0 - Add p-state debugging and improvements - Fix in secure display context creation - add option to use custom backlight caps - Lowering min Z8 residency time - Restore rptr/wptr for DMCUB as workaround - Update FW feature caps struct Acked-by:
Aric Cyr <aric.cyr@amd.com> Signed-off-by:
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Michael Strauss authored
[WHY] Current Aux-I sequence checks for local_sink which isn't populated on MST links [HOW] Leave disable aux-i delay as 0 for MST cases Cc: stable@vger.kernel.org Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by:
George Shen <George.Shen@amd.com> Reviewed-by:
Michael Strauss <michael.strauss@amd.com> Signed-off-by:
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Alvin Lee authored
- We want to disable SubVP if Graphics Error Correction/Correcting Code (GECC) is enabled. - After reading feature caps from DMCUB during init, use the GECC enable/disable info to determine if SubVP can be enabled or not. Tested-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by:
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Alvin Lee authored
[Description] - Add debug option to enable SubVP for high refresh rate displays - For now limit the enabled modes based on a table in debug options - Currently disabled by default Tested-by:
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Alvin Lee authored
- Previously update_clocks was overriding pstate support if it checked that there were no planes - However, P-State support should be determined in validation phase instead - This fixes an issue where a transition from FPO -> no planes expects UCLK MAX, but update_clocks was overriding to set UCLK to min Tested-by:
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Sung Lee authored
[WHY] P-State related issues are fairly common but currently there is no way to debug these issues after the fact. [HOW] Add helpful registers to HW state queries Tested-by:
Sung Lee <sunglee@amd.com> Signed-off-by:
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Gabe Teeger authored
[Why] Flickering and underflow was observed when testing extended blank on dcn314. [What] Vstartup is contrainted by vblank_nom, so adjusting it to include non-adjusted vtotal in its calculation during freesync video means that Vstartup is not changed when vtotal changes. This fixed the flickering + underflow. dc_extended_blank_supported function was removed because extended blank is only relevant to when zstate is supported. The increased vtotal during freesync can be passed to dml regardless of whether extended blank is supported or not, so this function is not needed. Updates were made recently in dml to the calculation of min_dst_y_next_start. Dml input for dcn314 will now always use the newer calculation for min_dst_y_next_start. Dml input for older dcn versions remains untouched. The variable optimized_min_dst_y_next_start is replaced everywhere with min_dst_y_next_start, and the updated dml allows min_dst_y_next_start to increase to an optimized value during freesync video, then return to default when freesync is disengaged. Also removed registry key for controlling extended blank feature. Tested-by:
Gabe Teeger <gabe.teeger@amd.com> Signed-off-by:
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Alan Liu authored
[Why & How] We need to store CRTC information in secure_display_ctx, so postpone the call to amdgpu_dm_crtc_secure_display_create_contexts() until we initialize all CRTCs. Cc: stable@vger.kernel.org Tested-by:
Wayne Lin <Wayne.Lin@amd.com> Acked-by:
Alan Liu <HaoPing.Liu@amd.com> Signed-off-by:
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Leo (Hanghong) Ma authored
[Why] Our QA found visual confirm color is not as expected for Auto Color Management feature test after enable it. [How] Calculate scaler recout data when visual confirm enabled to update the visual confirm bar on the display. Tested-by:
Leo (Hanghong) Ma <hanghong.ma@amd.com> Signed-off-by:
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Aurabindo Pillai authored
OTG_V_TOTAL_MIN/MAX_SEL bits are required to be programmed to 1 if writes to OTG timing registers need to be honoured. This is usually needed only when freesync is active. However, SubVP + DRR requires that we're able to change timing even without freesync being active (but supported). By unconditionally writing this bit to 1, we remove an unnecessary dependency so that DMCUB can change OTG timing whenever it wants. Signed-off-by:
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Josip Pavic authored
[Why & How] Provide option for vendors to specify a custom brightness-to-backlight conversion profile. Tested-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
Josip Pavic <Josip.Pavic@amd.com> Signed-off-by:
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Leo Chen authored
[Why & How] Per HW team request, we're lowering the minimum Z8 residency time to 2000us. This enables Z8 support for additional modes we were previously blocking like 2k>60hz Cc: stable@vger.kernel.org Tested-by:
Leo Chen <sancchen@amd.com> Signed-off-by:
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Alvin Lee authored
Enable SubVP on PSR panels now that we have FW support Tested-by:
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Dmytro Laktyushkin authored
This feature is meant to unblock PSTATE for certain high end display configs on dcn315. This is achieved by allocating CRB to detile buffer based on display requirements to meet pstate latency hiding needs. Tested-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Signed-off-by:
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Alvin Lee authored
- Due to hardware related QoS issues, we need to limit certain SKUs with less memory channels to DPM1 and above. - At DPM0 + workload running, the urgent return latency can exceed 15us (the expected maximum is 4us) which results in underflow Cc: stable@vger.kernel.org Tested-by:
Saaem Rizvi <SyedSaaem.Rizvi@amd.com> Acked-by:
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JinZe.Xu authored
[Why] States may be desync after resume. [How] Sync sw state with hw state. Tested-by:
JinZe.Xu <JinZe.Xu@amd.com> Signed-off-by:
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Alvin Lee authored
Reorder FW feature caps struct variable order to ensure backwards compatability is maintained for older FW Tested-by:
Sung Lee <Sung.Lee@amd.com> Acked-by:
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Alex Hung authored
[Why] When userspace (IGT) inserts EDID with audio data (ELD), EDID is not updated. [How] Implements force function (amdgpu_dm_connector_funcs_force) in amdgpu_dm_connector_funcs to create emulated sink and to handle EDID. Tested-by:
Hersen Wu <hersenxs.wu@amd.com> Acked-by:
Alex Hung <alex.hung@amd.com> Signed-off-by:
Wenchieh Chien <wenchieh.chien@amd.com> Signed-off-by:
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