- 20 Apr, 2022 13 commits
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Ben Walker authored
Document this function to make clear the expected behavior of the 'value' parameter. It was intended to match the behavior of POSIX memset as laid out here: https://lore.kernel.org/dmaengine/YejrA5ZWZ3lTRO%2F1@matsya/Signed-off-by:
Ben Walker <benjamin.walker@intel.com> Link: https://lore.kernel.org/r/20220301182551.883474-2-benjamin.walker@intel.comSigned-off-by:
Vinod Koul <vkoul@kernel.org>
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Dave Jiang authored
Move the calling of request_irq() and other related irq setup code until after the WQ is successfully enabled. This reduces the amount of setup/teardown if the wq is not configured correctly and cannot be enabled. Signed-off-by:
Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/164642777730.179702.1880317757087484299.stgit@djiang5-desk3.ch.intel.comSigned-off-by:
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Jiapeng Chong authored
Eliminate the follow versioncheck warning: ./drivers/dma/tegra186-gpc-dma.c: 21 linux/version.h not needed. Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Signed-off-by:
Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Link: https://lore.kernel.org/r/20220413083842.69845-1-jiapeng.chong@linux.alibaba.comSigned-off-by:
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Dave Jiang authored
Looks like I forgot to add DMA_INTERRUPT cap setting to the idxd driver and dmatest is still working regardless of this mistake. Add an explicit check of DMA_INTERRUPT capability for dmatest to make sure the DMA device being used actually supports interrupt before the test is launched and also that the driver is programmed correctly. Signed-off-by:
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Haowen Bai authored
This fixes the following sparse warnings: drivers/dma/mediatek/mtk-hsdma.c:604:26: warning: Using plain integer as NULL pointer Signed-off-by:
Haowen Bai <baihaowen@meizu.com> Link: https://lore.kernel.org/r/1649750340-30777-1-git-send-email-baihaowen@meizu.comSigned-off-by:
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Haowen Bai authored
Unneeded variable: "retval". Return "NULL" , so we have to make code clear. better way, drop the function. Signed-off-by:
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Dave Jiang authored
Load the max_xfer_size and max_batch_size values from the values read from registers to the shadow variables. This will allow the read-only device to display the correct values for the sysfs attributes. Signed-off-by:
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Dave Jiang authored
Even though idxd driver has always supported interrupt, it never actually set the DMA_INTERRUPT cap bit. Rectify this mistake so the interrupt capability is advertised. Reported-by:
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Aidan MacDonald authored
Set the maximum segment size, since the hardware can do transfers larger than the default 64 KiB returned by dma_get_max_seg_size(). The maximum segment size is limited by the 24-bit transfer count field in DMA descriptors. The number of bytes is equal to the transfer count times the transfer size unit, which is selected by the driver based on the DMA buffer address and length of the transfer. The size unit can be as small as 1 byte, so set the maximum segment size to 2^24-1 bytes to ensure the transfer count will not overflow regardless of the size unit selected by the driver. Signed-off-by:
Aidan MacDonald <aidanmacdonald.0x0@gmail.com> Link: https://lore.kernel.org/r/20220411153618.49876-1-aidanmacdonald.0x0@gmail.comSigned-off-by:
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Ilya Novikov authored
If the DMA_PREP_INTERRUPT flag is not provided, run in polled mode, which significantly improves IOPS: more than twice on chunks < 4K. Signed-off-by:
Ilya Novikov <i.m.novikov@yadro.com> Link: https://lore.kernel.org/r/20220413113733.59041-1-i.m.novikov@yadro.comSigned-off-by:
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Vinod Koul authored
Document the compatible for GPI DMA controller on SC7280 SoC Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220414064216.1182177-1-vkoul@kernel.orgSigned-off-by:
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Yunbo Yu authored
It is unnecessary to call spin_lock_bh() if you are already in a tasklet. Signed-off-by:
Yunbo Yu <yuyunbo519@gmail.com> Reviewed-by:
Logan Gunthorpe <logang@deltatee.com> Link: https://lore.kernel.org/r/20220418142021.1241558-1-yuyunbo519@gmail.comSigned-off-by:
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Radhey Shyam Pandey authored
MCDMA IP provides up to 16 multiple channels of data movement each on MM2S and S2MM paths. Inline with implementation, in the binding add description for the channel ID start index and mention that it's fixed irrespective of the MCDMA IP configuration(number of read/write channels). Signed-off-by:
Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Acked-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/1649939061-6675-1-git-send-email-radhey.shyam.pandey@xilinx.comSigned-off-by:
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- 13 Apr, 2022 4 commits
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Bjorn Andersson authored
The Qualcomm SM8350 platform does, like the SM8450, provide a set of GPI controllers with an ee-offset of 0x10000. Add this to the driver. Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220412212959.2385085-1-bjorn.andersson@linaro.orgSigned-off-by:
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Vinod Koul authored
Controller on newer SoCs like SM8450 have registers at at offset. Add ee_offset to driver_data and add this compatible for the driver. Signed-off-by:
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Vinod Koul authored
Add the compatible for newer qcom socs with gpi dma i.e qcom sm8350 and sm8450. Signed-off-by:
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Vinod Koul authored
Newer platforms seem to have strict requirement for TRE flags which causes transaction to timeout. This was resolved to missing chain and link flag for duplex spi transaction. So add these two flags. Signed-off-by:
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- 11 Apr, 2022 15 commits
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Christophe JAILLET authored
According to lib/idr.c, The IDA handles its own locking. It is safe to call any of the IDA functions without synchronisation in your code. so the 'chan_mutex' mutex can just be removed. It is here only to protect some ida_alloc()/ida_free() calls. Signed-off-by:
Christophe JAILLET <christophe.jaillet@wanadoo.fr> Link: https://lore.kernel.org/r/7180452c1d77b039e27b6f9418e0e7d9dd33c431.1644140845.git.christophe.jaillet@wanadoo.frSigned-off-by:
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Dave Jiang authored
Add additional structure definitions for Intel In-memory Analytics Accelerator (IAA/IAX). See specification (1) for more details. 1: https://cdrdv2.intel.com/v1/dl/getContent/721858Signed-off-by:
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Akhil R authored
Adding GPC DMA controller driver for Tegra. The driver supports dma transfers between memory to memory, IO peripheral to memory and memory to IO peripheral. Co-developed-by:
Pavan Kunapuli <pkunapuli@nvidia.com> Signed-off-by:
Rajesh Gumasta <rgumasta@nvidia.com> Signed-off-by:
Akhil R <akhilrajeev@nvidia.com> Reviewed-by:
Jon Hunter <jonathanh@nvidia.com> Reviewed-by:
Dmitry Osipenko <digetx@gmail.com> Acked-by:
Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20220225132044.14478-3-akhilrajeev@nvidia.comSigned-off-by:
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Akhil R authored
Add DT binding document for Nvidia Tegra GPCDMA controller. Signed-off-by:
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Olivier Dautricourt authored
This email should now be used to contact me. Signed-off-by:
Olivier Dautricourt <olivier.dautricourt@orolia.com> Acked-by:
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Olivier Dautricourt authored
This email should now be used to contact me. Signed-off-by:
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Dave Jiang authored
Add string processing with strim() in order to remove trailing white spaces that may be input by user for the wq->name. Signed-off-by:
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Paul Kocialkowski authored
The current documentation for the residue reported in a cyclic transfer case mentions that the reported residue should be relative to the current period only. However the definition of DMA_RESIDUE_GRANULARITY_SEGMENT specifies that the residue should be updated after each period for a cyclic transfer, which is in direct contradiction. Moreover the pcm_dmaengine common code uses the residue relative to the whole cyclic buffer size, not one period. Correct the residue-related documentation to reflect this. Signed-off-by:
Paul Kocialkowski <paul.kocialkowski@bootlin.com> Link: https://lore.kernel.org/r/20220331134114.703782-1-paul.kocialkowski@bootlin.comSigned-off-by:
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Amelie Delaunay authored
STM32_MDMA_CCR bit[8] is used to enable Secure Mode (SM). If this bit is set, it means that all the channel registers are write-protected. So the channel is not available for Linux use. Add stm32_mdma_filter_fn() callback filter and give it to __dma_request_chan (instead of dma_get_any_slave_channel()), to exclude the channel if it is marked Secure. Signed-off-by:
Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20220330103645.99969-1-amelie.delaunay@foss.st.comSigned-off-by:
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Christophe Leroy authored
powerpc's asm/prom.h brings some headers that it doesn't need itself. In order to clean it up, first add missing headers in users of asm/prom.h Signed-off-by:
Christophe Leroy <christophe.leroy@csgroup.eu> Link: https://lore.kernel.org/r/f98acba303489bdf003e7256460696225b00702e.1648833428.git.christophe.leroy@csgroup.euSigned-off-by:
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jianchunfu authored
Remove the second 'to' which is repeated. Signed-off-by:
jianchunfu <jianchunfu@cmss.chinamobile.com> Link: https://lore.kernel.org/r/20220403123120.7794-1-jianchunfu@cmss.chinamobile.comSigned-off-by:
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Dave Jiang authored
The driver currently programs the system pasid to the WQ preemptively when system pasid is enabled. Given that a dwq will reprogram the pasid and possibly a different pasid, the programming is not necessary. The pasid_en bit can be set for swq as it does not need pasid programming but needs the pasid_en bit. Remove system pasid programming on device config write. Add pasid programming for kernel wq type on wq driver enable. The char dev driver already reprograms the dwq on ->open() call so there's no change. Signed-off-by:
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Lad Prabhakar authored
platform_get_resource(pdev, IORESOURCE_IRQ, ..) relies on static allocation of IRQ resources in DT core code, this causes an issue when using hierarchical interrupt domains using "interrupts" property in the node as this bypasses the hierarchical setup and messes up the irq chaining. In preparation for removal of static setup of IRQ resource from DT core code use platform_get_irq(). Signed-off-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by:
Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20220404155557.27316-4-prabhakar.mahadev-lad.rj@bp.renesas.comSigned-off-by:
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Lad Prabhakar authored
platform_get_resource(pdev, IORESOURCE_IRQ, ..) relies on static allocation of IRQ resources in DT core code, this causes an issue when using hierarchical interrupt domains using "interrupts" property in the node as this bypasses the hierarchical setup and messes up the irq chaining. In preparation for removal of static setup of IRQ resource from DT core code use platform_get_irq(). Signed-off-by:
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Lad Prabhakar authored
platform_get_resource(pdev, IORESOURCE_IRQ, ..) relies on static allocation of IRQ resources in DT core code, this causes an issue when using hierarchical interrupt domains using "interrupts" property in the node as this bypasses the hierarchical setup and messes up the irq chaining. In preparation for removal of static setup of IRQ resource from DT core code use platform_get_irq_optional(). There are no non-DT users for this driver so interrupt range (irq_res->start-irq_res->end) is no longer required and with DT we will be sure it will be a single IRQ resource for each index. Signed-off-by:
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- 08 Apr, 2022 3 commits
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Lad Prabhakar authored
The DMAC block is identical on Renesas RZ/G2L, RZ/G2UL and RZ/V2L SoC's, so instead of adding dependency for each SoC's add dependency on ARCH_RZG2L. The ARCH_RZG2L config option is already selected by ARCH_R9A07G043, ARCH_R9A07G044 and ARCH_R9A07G054. Signed-off-by:
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Zong Li authored
It currently assumes that there are always four channels, it would cause the error if there is actually less than four channels. Change that by getting number of channel from device tree. For backwards-compatibility, it uses the default value (i.e. 4) when there is no 'dma-channels' information in dts. Signed-off-by:
Zong Li <zong.li@sifive.com> Acked-by:
Palmer Dabbelt <palmer@rivosinc.com> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com> Link: https://lore.kernel.org/r/f08a95b6582a51712c5b2c3cb859136d07bfa8b9.1648461096.git.zong.li@sifive.comSigned-off-by:
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Zong Li authored
Add dma-channels property, then we can determine how many channels there by device tree, rather than statically defining it in PDMA driver. In addition, we also modify the compatible for PDMA versioning scheme. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Reviewed-by:
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- 03 Apr, 2022 5 commits
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Linus Torvalds authored
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git://git.kernel.org/pub/scm/linux/kernel/git/rostedt/linux-traceLinus Torvalds authored
Pull more tracing updates from Steven Rostedt: - Rename the staging files to give them some meaning. Just stage1,stag2,etc, does not show what they are for - Check for NULL from allocation in bootconfig - Hold event mutex for dyn_event call in user events - Mark user events to broken (to work on the API) - Remove eBPF updates from user events - Remove user events from uapi header to keep it from being installed. - Move ftrace_graph_is_dead() into inline as it is called from hot paths and also convert it into a static branch. * tag 'trace-v5.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/rostedt/linux-trace: tracing: Move user_events.h temporarily out of include/uapi ftrace: Make ftrace_graph_is_dead() a static branch tracing: Set user_events to BROKEN tracing/user_events: Remove eBPF interfaces tracing/user_events: Hold event_mutex during dyn_event_add proc: bootconfig: Add null pointer check tracing: Rename the staging files for trace_events
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git://git.kernel.org/pub/scm/linux/kernel/git/clk/linuxLinus Torvalds authored
Pull clk fix from Stephen Boyd: "A single revert to fix a boot regression seen when clk_put() started dropping rate range requests. It's best to keep various systems booting so we'll kick this out and try again next time" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: Revert "clk: Drop the rate range on clk_put()"
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git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipLinus Torvalds authored
Pull x86 fixes from Thomas Gleixner: "A set of x86 fixes and updates: - Make the prctl() for enabling dynamic XSTATE components correct so it adds the newly requested feature to the permission bitmap instead of overwriting it. Add a selftest which validates that. - Unroll string MMIO for encrypted SEV guests as the hypervisor cannot emulate it. - Handle supervisor states correctly in the FPU/XSTATE code so it takes the feature set of the fpstate buffer into account. The feature sets can differ between host and guest buffers. Guest buffers do not contain supervisor states. So far this was not an issue, but with enabling PASID it needs to be handled in the buffer offset calculation and in the permission bitmaps. - Avoid a gazillion of repeated CPUID invocations in by caching the values early in the FPU/XSTATE code. - Enable CONFIG_WERROR in x86 defconfig. - Make the X86 defconfigs more useful by adapting them to Y2022 reality" * tag 'x86-urgent-2022-04-03' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/fpu/xstate: Consolidate size calculations x86/fpu/xstate: Handle supervisor states in XSTATE permissions x86/fpu/xsave: Handle compacted offsets correctly with supervisor states x86/fpu: Cache xfeature flags from CPUID x86/fpu/xsave: Initialize offset/size cache early x86/fpu: Remove unused supervisor only offsets x86/fpu: Remove redundant XCOMP_BV initialization x86/sev: Unroll string mmio with CC_ATTR_GUEST_UNROLL_STRING_IO x86/config: Make the x86 defconfigs a bit more usable x86/defconfig: Enable WERROR selftests/x86/amx: Update the ARCH_REQ_XCOMP_PERM test x86/fpu/xstate: Fix the ARCH_REQ_XCOMP_PERM implementation -
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipLinus Torvalds authored
Pull RT signal fix from Thomas Gleixner: "Revert the RT related signal changes. They need to be reworked and generalized" * tag 'core-urgent-2022-04-03' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: Revert "signal, x86: Delay calling signals in atomic on RT enabled kernels"
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