Device tree bindings for ARM PL353 static memory controller

PL353 Static Memory Controller is a bus where you can connect two kinds
of memory interfaces: NAND and memory mapped interfaces (such as SRAM or NOR).

Required properties:
- compatible		: Should be "arm,pl353-smc-r2p1", "arm,primecell".
- reg			: Controller registers map and length.
- clock-names		: List of input clock names - "memclk", "apb_pclk"
			  (See clock bindings for details).
- clocks		: Clock phandles (see clock bindings for details).
- address-cells		: Must be 2.
- size-cells		: Must be 1.
- ranges		: Memory bus areas for interacting with the devices.
			  Encodes CS to memory region association.

The child device node represents the controller connected to the SMC
bus. Only one between: NAND controller, NOR controller and SRAM controller
is allowed in a single system.

for NAND partition information please refer the below file
Documentation/devicetree/bindings/mtd/partition.txt

Example:
	smcc: memory-controller@e000e000
			compatible = "arm,pl353-smc-r2p1", "arm,primecell";
			clock-names = "memclk", "apb_pclk";
			clocks = <&clkc 11>, <&clkc 44>;
			reg = <0xe000e000 0x1000>;
			#address-cells = <2>;
			#size-cells = <1>;
			ranges = <0x0 0x0 0xe1000000 0x1000000 //Nand CS Region
				  0x1 0x0 0xe2000000 0x2000000 //SRAM/NOR CS Region
				  0x2 0x0 0xe4000000 0x2000000>; //SRAM/NOR CS Region
			nand_0: flash@e1000000 {
				compatible = "arm,pl353-nand-r2p1"
				reg = <0 0 0x1000000>;
				(...)
			};
			nor0: flash@e2000000 {
				compatible = "cfi-flash";
				reg = <1 0 0x2000000>;
			};
			nor1: flash@e4000000 {
				compatible = "cfi-flash";
				reg = <2 0 0x2000000>;
			};
	};