• Chris Wilson's avatar
    drm/i915: Don't set a MBZ bit in gen2/3 MI_FLUSH · 46f0f8d1
    Chris Wilson authored
    On gen2 MI_EXE_FLUSH is actually an AGP flush bit and on gen3 marked as
    reserved.  On both it is documented as being must-be-zero. So obey the
    documentation, and separate the gen2 flush into its own little routine
    and share with gen3.
    
    This means that we can rename the existing render_ring_flush() to
    reflect the generation from which it first applies and remove the code
    for handling earlier generations from it.
    
    v2: Applies to gen3 as well
    v3: Make it compile and improve the commit message.
    Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
    Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
    46f0f8d1
intel_ringbuffer.c 37.2 KB