• Rodrigo Vivi's avatar
    drm/i915: Save latest known sink CRC to compensate delayed counter reset. · 621d4c76
    Rodrigo Vivi authored
    By Vesa DP 1.2 Spec TEST_CRC_COUNT should be
    "reset to 0 when TEST_SINK bit 0 = 0."
    
    However for some strange reason when PSR is enabled in
    certain platforms this is not true. At least not immediatelly.
    
    So we face cases like this:
    
    first get_sink_crc operation:
    	     count: 0, crc: 000000000000
    	     count: 1, crc: c101c101c101
    returned expected crc: c101c101c101
    
    secont get_sink_crc operation:
    	     count: 1, crc: c101c101c101
    	     count: 0, crc: 000000000000
    	     count: 1, crc: 0000c1010000
    should return expected crc: 0000c1010000
    
    But also the reset to 0 should be faster resulting into:
    
    get_sink_crc operation:
    	     count: 1, crc: c101c101c101
    	     count: 1, crc: 0000c1010000
    should return expected crc: 0000c1010000
    
    So in order to know that the second one is valid one
    we need to compare the pair (count, crc) with latest (count, crc).
    
    If the pair changed you have your valid CRC.
    Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
    Reviewed-by: default avatarRafael Antognolli <rafael.antognolli@intel.com>
    Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
    621d4c76
intel_dp.c 169 KB