• Jan Glauber's avatar
    arm64: perf: Enable PMCR long cycle counter bit · 7175f059
    Jan Glauber authored
    With the long cycle counter bit (LC) disabled the cycle counter is not
    working on ThunderX SOC (ThunderX only implements Aarch64).
    Also, according to documentation LC == 0 is deprecated.
    
    To keep the code simple the patch does not introduce 64 bit wide counter
    functions. Instead writing the cycle counter always sets the upper
    32 bits so overflow interrupts are generated as before.
    
    Original patch from Andrew Pinksi <Andrew.Pinksi@caviumnetworks.com>
    Signed-off-by: default avatarJan Glauber <jglauber@cavium.com>
    Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
    7175f059
perf_event.c 31.2 KB