• Ben Widawsky's avatar
    drm/i915/bdw: Render ring flushing · a5f3d68e
    Ben Widawsky authored
    PIPE_CONTROL added the high address dword. I'm not sure how the
    simulator let me get away with this. I've explicitly left out all the
    workarounds from Gen7 because in the minimal digging that I did, most
    don't seem necessary, and the simulator doesn't complain without them
    
    Note that BLT and BSD ring commands had already been updated previously.
    Just render/pipe_control should have been broken.
    
    v2: Squash in a fixup from Ville to follow the recent IVB PIPE_CONTROL
    updates: "BDW uses the IVB PIPE_CONTROL style for specifying GTT vs.
    PPGTT for the PIPE_CONTROL QW/DW write."
    
    v3: Rebase on top of Chris' cleanup to have an explicit ring->scratch
    buffer object instead of an opaque ring->private where everyone stores
    the same stuff inside.
    Reported-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
    Reviewed-by: Ben Widawsky <ben@bwidawsk.net> (for the fixup)
    Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
    Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1)
    Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
    a5f3d68e
intel_ringbuffer.c 57.6 KB