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Commit 00d79e9d authored by Hans J. Koch's avatar Hans J. Koch
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arm: Remove mach-tcc8k directory 

The Telechips ARM architecture is being removed. This patch
deletes the arch/arm/mach-tcc8k/ folder.

Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Harry Sievers <hsievers@csselectronic.com>
Signed-off-by: default avatarHans J. Koch <hjk@hansjkoch.de>
parent 273b5e51
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arch/arm/mach-tcc8k/Kconfig deleted 100644 → 0
View file @ 273b5e51
if ARCH_TCC8K
comment "TCC8000 systems:"
config MACH_TCC8000_SDK
bool "Telechips TCC8000-SDK development kit"
default y
help
Support for the Telechips TCC8000-SDK board.
endif
arch/arm/mach-tcc8k/Makefile deleted 100644 → 0
View file @ 273b5e51
#
# Makefile for TCC8K boards and common files.
#
# Common support
obj-y += clock.o irq.o time.o io.o devices.o
# Board specific support
obj-$(CONFIG_MACH_TCC8000_SDK) += board-tcc8000-sdk.o
arch/arm/mach-tcc8k/Makefile.boot deleted 100644 → 0
View file @ 273b5e51
zreladdr-y += 0x20008000
params_phys-y := 0x20000100
initrd_phys-y := 0x20800000
arch/arm/mach-tcc8k/board-tcc8000-sdk.c deleted 100644 → 0
View file @ 273b5e51
/*
* Copyright (C) 2009 Hans J. Koch <hjk@linutronix.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <mach/clock.h>
#include <mach/tcc-nand.h>
#include <mach/tcc8k-regs.h>
#include "common.h"
#define XI_FREQUENCY 12000000
#define XTI_FREQUENCY 32768
#ifdef CONFIG_MTD_NAND_TCC
/* NAND */
static struct tcc_nand_platform_data tcc8k_sdk_nand_data = {
.width = 1,
.hw_ecc = 0,
};
#endif
static void __init tcc8k_init(void)
{
#ifdef CONFIG_MTD_NAND_TCC
tcc_nand_device.dev.platform_data = &tcc8k_sdk_nand_data;
platform_device_register(&tcc_nand_device);
#endif
}
static void __init tcc8k_init_timer(void)
{
tcc_clocks_init(XI_FREQUENCY, XTI_FREQUENCY);
}
static struct sys_timer tcc8k_timer = {
.init = tcc8k_init_timer,
};
static void __init tcc8k_map_io(void)
{
tcc8k_map_common_io();
/* set PLL0 clock to 96MHz, adapt UART0 divisor */
__raw_writel(0x00026003, CKC_BASE + PLL0CFG_OFFS);
__raw_writel(0x10000001, CKC_BASE + ACLKUART0_OFFS);
/* set PLL1 clock to 192MHz */
__raw_writel(0x00016003, CKC_BASE + PLL1CFG_OFFS);
/* set PLL2 clock to 48MHz */
__raw_writel(0x00036003, CKC_BASE + PLL2CFG_OFFS);
/* with CPU freq higher than 150 MHz, need extra DTCM wait */
__raw_writel(0x00000001, SCFG_BASE + DTCMWAIT_OFFS);
/* PLL locking time as specified */
udelay(300);
}
MACHINE_START(TCC8000_SDK, "Telechips TCC8000-SDK Demo Board")
.atag_offset = 0x100,
.map_io = tcc8k_map_io,
.init_irq = tcc8k_init_irq,
.init_machine = tcc8k_init,
.timer = &tcc8k_timer,
MACHINE_END
arch/arm/mach-tcc8k/clock.c deleted 100644 → 0
View file @ 273b5e51
/*
* Lowlevel clock handling for Telechips TCC8xxx SoCs
*
* Copyright (C) 2010 by Hans J. Koch <hjk@linutronix.de>
*
* Licensed under the terms of the GPL v2
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/clkdev.h>
#include <mach/clock.h>
#include <mach/irqs.h>
#include <mach/tcc8k-regs.h>
#include "common.h"
#define BCLKCTR0 (CKC_BASE + BCLKCTR0_OFFS)
#define BCLKCTR1 (CKC_BASE + BCLKCTR1_OFFS)
#define ACLKREF (CKC_BASE + ACLKREF_OFFS)
#define ACLKUART0 (CKC_BASE + ACLKUART0_OFFS)
#define ACLKUART1 (CKC_BASE + ACLKUART1_OFFS)
#define ACLKUART2 (CKC_BASE + ACLKUART2_OFFS)
#define ACLKUART3 (CKC_BASE + ACLKUART3_OFFS)
#define ACLKUART4 (CKC_BASE + ACLKUART4_OFFS)
#define ACLKI2C (CKC_BASE + ACLKI2C_OFFS)
#define ACLKADC (CKC_BASE + ACLKADC_OFFS)
#define ACLKUSBH (CKC_BASE + ACLKUSBH_OFFS)
#define ACLKLCD (CKC_BASE + ACLKLCD_OFFS)
#define ACLKSDH0 (CKC_BASE + ACLKSDH0_OFFS)
#define ACLKSDH1 (CKC_BASE + ACLKSDH1_OFFS)
#define ACLKSPI0 (CKC_BASE + ACLKSPI0_OFFS)
#define ACLKSPI1 (CKC_BASE + ACLKSPI1_OFFS)
#define ACLKSPDIF (CKC_BASE + ACLKSPDIF_OFFS)
#define ACLKC3DEC (CKC_BASE + ACLKC3DEC_OFFS)
#define ACLKCAN0 (CKC_BASE + ACLKCAN0_OFFS)
#define ACLKCAN1 (CKC_BASE + ACLKCAN1_OFFS)
#define ACLKGSB0 (CKC_BASE + ACLKGSB0_OFFS)
#define ACLKGSB1 (CKC_BASE + ACLKGSB1_OFFS)
#define ACLKGSB2 (CKC_BASE + ACLKGSB2_OFFS)
#define ACLKGSB3 (CKC_BASE + ACLKGSB3_OFFS)
#define ACLKTCT (CKC_BASE + ACLKTCT_OFFS)
#define ACLKTCX (CKC_BASE + ACLKTCX_OFFS)
#define ACLKTCZ (CKC_BASE + ACLKTCZ_OFFS)
#define ACLK_MAX_DIV (0xfff + 1)
/* Crystal frequencies */
static unsigned long xi_rate, xti_rate;
static void __iomem *pll_cfg_addr(int pll)
{
switch (pll) {
case 0: return (CKC_BASE + PLL0CFG_OFFS);
case 1: return (CKC_BASE + PLL1CFG_OFFS);
case 2: return (CKC_BASE + PLL2CFG_OFFS);
default:
BUG();
}
}
static int pll_enable(int pll, int enable)
{
u32 reg;
void __iomem *addr = pll_cfg_addr(pll);
reg = __raw_readl(addr);
if (enable)
reg &= ~PLLxCFG_PD;
else
reg |= PLLxCFG_PD;
__raw_writel(reg, addr);
return 0;
}
static int xi_enable(int enable)
{
u32 reg;
reg = __raw_readl(CKC_BASE + CLKCTRL_OFFS);
if (enable)
reg |= CLKCTRL_XE;
else
reg &= ~CLKCTRL_XE;
__raw_writel(reg, CKC_BASE + CLKCTRL_OFFS);
return 0;
}
static int root_clk_enable(enum root_clks src)
{
switch (src) {
case CLK_SRC_PLL0: return pll_enable(0, 1);
case CLK_SRC_PLL1: return pll_enable(1, 1);
case CLK_SRC_PLL2: return pll_enable(2, 1);
case CLK_SRC_XI: return xi_enable(1);
default:
BUG();
}
return 0;
}
static int root_clk_disable(enum root_clks src)
{
switch (src) {
case CLK_SRC_PLL0: return pll_enable(0, 0);
case CLK_SRC_PLL1: return pll_enable(1, 0);
case CLK_SRC_PLL2: return pll_enable(2, 0);
case CLK_SRC_XI: return xi_enable(0);
default:
BUG();
}
return 0;
}
static int enable_clk(struct clk *clk)
{
u32 reg;
if (clk->root_id != CLK_SRC_NOROOT)
return root_clk_enable(clk->root_id);
if (clk->aclkreg) {
reg = __raw_readl(clk->aclkreg);
reg |= ACLK_EN;
__raw_writel(reg, clk->aclkreg);
}
if (clk->bclkctr) {
reg = __raw_readl(clk->bclkctr);
reg |= 1 << clk->bclk_shift;
__raw_writel(reg, clk->bclkctr);
}
return 0;
}
static void disable_clk(struct clk *clk)
{
u32 reg;
if (clk->root_id != CLK_SRC_NOROOT) {
root_clk_disable(clk->root_id);
return;
}
if (clk->bclkctr) {
reg = __raw_readl(clk->bclkctr);
reg &= ~(1 << clk->bclk_shift);
__raw_writel(reg, clk->bclkctr);
}
if (clk->aclkreg) {
reg = __raw_readl(clk->aclkreg);
reg &= ~ACLK_EN;
__raw_writel(reg, clk->aclkreg);
}
}
static unsigned long get_rate_pll(int pll)
{
u32 reg;
unsigned long s, m, p;
void __iomem *addr = pll_cfg_addr(pll);
reg = __raw_readl(addr);
s = (reg >> 16) & 0x07;
m = (reg >> 8) & 0xff;
p = reg & 0x3f;
return (m * xi_rate) / (p * (1 << s));
}
static unsigned long get_rate_pll_div(int pll)
{
u32 reg;
unsigned long div = 0;
void __iomem *addr;
switch (pll) {
case 0:
addr = CKC_BASE + CLKDIVC0_OFFS;
reg = __raw_readl(addr);
if (reg & CLKDIVC0_P0E)
div = (reg >> 24) & 0x3f;
break;
case 1:
addr = CKC_BASE + CLKDIVC0_OFFS;
reg = __raw_readl(addr);
if (reg & CLKDIVC0_P1E)
div = (reg >> 16) & 0x3f;
break;
case 2:
addr = CKC_BASE + CLKDIVC1_OFFS;
reg = __raw_readl(addr);
if (reg & CLKDIVC1_P2E)
div = reg & 0x3f;
break;
}
return get_rate_pll(pll) / (div + 1);
}
static unsigned long get_rate_xi_div(void)
{
unsigned long div = 0;
u32 reg = __raw_readl(CKC_BASE + CLKDIVC0_OFFS);
if (reg & CLKDIVC0_XE)
div = (reg >> 8) & 0x3f;
return xi_rate / (div + 1);
}
static unsigned long get_rate_xti_div(void)
{
unsigned long div = 0;
u32 reg = __raw_readl(CKC_BASE + CLKDIVC0_OFFS);
if (reg & CLKDIVC0_XTE)
div = reg & 0x3f;
return xti_rate / (div + 1);
}
static unsigned long root_clk_get_rate(enum root_clks src)
{
switch (src) {
case CLK_SRC_PLL0: return get_rate_pll(0);
case CLK_SRC_PLL1: return get_rate_pll(1);
case CLK_SRC_PLL2: return get_rate_pll(2);
case CLK_SRC_PLL0DIV: return get_rate_pll_div(0);
case CLK_SRC_PLL1DIV: return get_rate_pll_div(1);
case CLK_SRC_PLL2DIV: return get_rate_pll_div(2);
case CLK_SRC_XI: return xi_rate;
case CLK_SRC_XTI: return xti_rate;
case CLK_SRC_XIDIV: return get_rate_xi_div();
case CLK_SRC_XTIDIV: return get_rate_xti_div();
default: return 0;
}
}
static unsigned long aclk_get_rate(struct clk *clk)
{
u32 reg;
unsigned long div;
unsigned int src;
reg = __raw_readl(clk->aclkreg);
div = reg & 0x0fff;
src = (reg >> ACLK_SEL_SHIFT) & CLK_SRC_MASK;
return root_clk_get_rate(src) / (div + 1);
}
static unsigned long aclk_best_div(struct clk *clk, unsigned long rate)
{
unsigned long div, src, freq, r1, r2;
if (!rate)
return ACLK_MAX_DIV;
src = __raw_readl(clk->aclkreg) >> ACLK_SEL_SHIFT;
src &= CLK_SRC_MASK;
freq = root_clk_get_rate(src);
div = freq / rate;
if (!div)
return 1;
if (div >= ACLK_MAX_DIV)
return ACLK_MAX_DIV;
r1 = freq / div;
r2 = freq / (div + 1);
if ((rate - r2) < (r1 - rate))
return div + 1;
return div;
}
static unsigned long aclk_round_rate(struct clk *clk, unsigned long rate)
{
unsigned int src;
src = __raw_readl(clk->aclkreg) >> ACLK_SEL_SHIFT;
src &= CLK_SRC_MASK;
return root_clk_get_rate(src) / aclk_best_div(clk, rate);
}
static int aclk_set_rate(struct clk *clk, unsigned long rate)
{
u32 reg;
reg = __raw_readl(clk->aclkreg) & ~ACLK_DIV_MASK;
reg |= aclk_best_div(clk, rate) - 1;
__raw_writel(reg, clk->aclkreg);
return 0;
}
static unsigned long get_rate_sys(struct clk *clk)
{
unsigned int src;
src = __raw_readl(CKC_BASE + CLKCTRL_OFFS) & CLK_SRC_MASK;
return root_clk_get_rate(src);
}
static unsigned long get_rate_bus(struct clk *clk)
{
unsigned int reg, sdiv, bdiv, rate;
reg = __raw_readl(CKC_BASE + CLKCTRL_OFFS);
rate = get_rate_sys(clk);
sdiv = (reg >> 20) & 3;
if (sdiv)
rate /= sdiv + 1;
bdiv = (reg >> 4) & 0xff;
if (bdiv)
rate /= bdiv + 1;
return rate;
}
static unsigned long get_rate_cpu(struct clk *clk)
{
unsigned int reg, div, fsys, fbus;
fbus = get_rate_bus(clk);
reg = __raw_readl(CKC_BASE + CLKCTRL_OFFS);
if (reg & (1 << 29))
return fbus;
fsys = get_rate_sys(clk);
div = (reg >> 16) & 0x0f;
return fbus + ((fsys - fbus) * (div + 1)) / 16;
}
static unsigned long get_rate_root(struct clk *clk)
{
return root_clk_get_rate(clk->root_id);
}
static int aclk_set_parent(struct clk *clock, struct clk *parent)
{
u32 reg;
if (clock->parent == parent)
return 0;
clock->parent = parent;
if (!parent)
return 0;
if (parent->root_id == CLK_SRC_NOROOT)
return 0;
reg = __raw_readl(clock->aclkreg);
reg &= ~ACLK_SEL_MASK;
reg |= (parent->root_id << ACLK_SEL_SHIFT) & ACLK_SEL_MASK;
__raw_writel(reg, clock->aclkreg);
return 0;
}
#define DEFINE_ROOT_CLOCK(name, ri, p) \
static struct clk name = { \
.root_id = ri, \
.get_rate = get_rate_root, \
.enable = enable_clk, \
.disable = disable_clk, \
.parent = p, \
};
#define DEFINE_SPECIAL_CLOCK(name, gr, p) \
static struct clk name = { \
.root_id = CLK_SRC_NOROOT, \
.get_rate = gr, \
.parent = p, \
};
#define DEFINE_ACLOCK(name, bc, bs, ar) \
static struct clk name = { \
.root_id = CLK_SRC_NOROOT, \
.bclkctr = bc, \
.bclk_shift = bs, \
.aclkreg = ar, \
.get_rate = aclk_get_rate, \
.set_rate = aclk_set_rate, \
.round_rate = aclk_round_rate, \
.enable = enable_clk, \
.disable = disable_clk, \
.set_parent = aclk_set_parent, \
};
#define DEFINE_BCLOCK(name, bc, bs, gr, p) \
static struct clk name = { \
.root_id = CLK_SRC_NOROOT, \
.bclkctr = bc, \
.bclk_shift = bs, \
.get_rate = gr, \
.enable = enable_clk, \
.disable = disable_clk, \
.parent = p, \
};
DEFINE_ROOT_CLOCK(xi, CLK_SRC_XI, NULL)
DEFINE_ROOT_CLOCK(xti, CLK_SRC_XTI, NULL)
DEFINE_ROOT_CLOCK(xidiv, CLK_SRC_XIDIV, &xi)
DEFINE_ROOT_CLOCK(xtidiv, CLK_SRC_XTIDIV, &xti)
DEFINE_ROOT_CLOCK(pll0, CLK_SRC_PLL0, &xi)
DEFINE_ROOT_CLOCK(pll1, CLK_SRC_PLL1, &xi)
DEFINE_ROOT_CLOCK(pll2, CLK_SRC_PLL2, &xi)
DEFINE_ROOT_CLOCK(pll0div, CLK_SRC_PLL0DIV, &pll0)
DEFINE_ROOT_CLOCK(pll1div, CLK_SRC_PLL1DIV, &pll1)
DEFINE_ROOT_CLOCK(pll2div, CLK_SRC_PLL2DIV, &pll2)
/* The following 3 clocks are special and are initialized explicitly later */
DEFINE_SPECIAL_CLOCK(sys, get_rate_sys, NULL)
DEFINE_SPECIAL_CLOCK(bus, get_rate_bus, &sys)
DEFINE_SPECIAL_CLOCK(cpu, get_rate_cpu, &sys)
DEFINE_ACLOCK(tct, NULL, 0, ACLKTCT)
DEFINE_ACLOCK(tcx, NULL, 0, ACLKTCX)
DEFINE_ACLOCK(tcz, NULL, 0, ACLKTCZ)
DEFINE_ACLOCK(ref, NULL, 0, ACLKREF)
DEFINE_ACLOCK(uart0, BCLKCTR0, 5, ACLKUART0)
DEFINE_ACLOCK(uart1, BCLKCTR0, 23, ACLKUART1)
DEFINE_ACLOCK(uart2, BCLKCTR0, 6, ACLKUART2)
DEFINE_ACLOCK(uart3, BCLKCTR0, 8, ACLKUART3)
DEFINE_ACLOCK(uart4, BCLKCTR1, 6, ACLKUART4)
DEFINE_ACLOCK(i2c, BCLKCTR0, 7, ACLKI2C)
DEFINE_ACLOCK(adc, BCLKCTR0, 10, ACLKADC)
DEFINE_ACLOCK(usbh0, BCLKCTR0, 11, ACLKUSBH)
DEFINE_ACLOCK(lcd, BCLKCTR0, 13, ACLKLCD)
DEFINE_ACLOCK(sd0, BCLKCTR0, 17, ACLKSDH0)
DEFINE_ACLOCK(sd1, BCLKCTR1, 5, ACLKSDH1)
DEFINE_ACLOCK(spi0, BCLKCTR0, 24, ACLKSPI0)
DEFINE_ACLOCK(spi1, BCLKCTR0, 30, ACLKSPI1)
DEFINE_ACLOCK(spdif, BCLKCTR1, 2, ACLKSPDIF)
DEFINE_ACLOCK(c3dec, BCLKCTR1, 9, ACLKC3DEC)
DEFINE_ACLOCK(can0, BCLKCTR1, 10, ACLKCAN0)
DEFINE_ACLOCK(can1, BCLKCTR1, 11, ACLKCAN1)
DEFINE_ACLOCK(gsb0, BCLKCTR1, 13, ACLKGSB0)
DEFINE_ACLOCK(gsb1, BCLKCTR1, 14, ACLKGSB1)
DEFINE_ACLOCK(gsb2, BCLKCTR1, 15, ACLKGSB2)
DEFINE_ACLOCK(gsb3, BCLKCTR1, 16, ACLKGSB3)
DEFINE_ACLOCK(usbh1, BCLKCTR1, 20, ACLKUSBH)
DEFINE_BCLOCK(dai0, BCLKCTR0, 0, NULL, NULL)
DEFINE_BCLOCK(pic, BCLKCTR0, 1, NULL, NULL)
DEFINE_BCLOCK(tc, BCLKCTR0, 2, NULL, NULL)
DEFINE_BCLOCK(gpio, BCLKCTR0, 3, NULL, NULL)
DEFINE_BCLOCK(usbd, BCLKCTR0, 4, NULL, NULL)
DEFINE_BCLOCK(ecc, BCLKCTR0, 9, NULL, NULL)
DEFINE_BCLOCK(gdma0, BCLKCTR0, 12, NULL, NULL)
DEFINE_BCLOCK(rtc, BCLKCTR0, 15, NULL, NULL)
DEFINE_BCLOCK(nfc, BCLKCTR0, 16, NULL, NULL)
DEFINE_BCLOCK(g2d, BCLKCTR0, 18, NULL, NULL)
DEFINE_BCLOCK(gdma1, BCLKCTR0, 22, NULL, NULL)
DEFINE_BCLOCK(mscl, BCLKCTR0, 25, NULL, NULL)
DEFINE_BCLOCK(bdma, BCLKCTR1, 0, NULL, NULL)
DEFINE_BCLOCK(adma0, BCLKCTR1, 1, NULL, NULL)
DEFINE_BCLOCK(scfg, BCLKCTR1, 3, NULL, NULL)
DEFINE_BCLOCK(cid, BCLKCTR1, 4, NULL, NULL)
DEFINE_BCLOCK(dai1, BCLKCTR1, 7, NULL, NULL)
DEFINE_BCLOCK(adma1, BCLKCTR1, 8, NULL, NULL)
DEFINE_BCLOCK(gps, BCLKCTR1, 12, NULL, NULL)
DEFINE_BCLOCK(gdma2, BCLKCTR1, 17, NULL, NULL)
DEFINE_BCLOCK(gdma3, BCLKCTR1, 18, NULL, NULL)
DEFINE_BCLOCK(ddrc, BCLKCTR1, 19, NULL, NULL)
#define _REGISTER_CLOCK(d, n, c) \
{ \
.dev_id = d, \
.con_id = n, \
.clk = &c, \
},
static struct clk_lookup lookups[] = {
_REGISTER_CLOCK(NULL, "bus", bus)
_REGISTER_CLOCK(NULL, "cpu", cpu)
_REGISTER_CLOCK(NULL, "tct", tct)
_REGISTER_CLOCK(NULL, "tcx", tcx)
_REGISTER_CLOCK(NULL, "tcz", tcz)
_REGISTER_CLOCK(NULL, "ref", ref)
_REGISTER_CLOCK(NULL, "dai0", dai0)
_REGISTER_CLOCK(NULL, "pic", pic)
_REGISTER_CLOCK(NULL, "tc", tc)
_REGISTER_CLOCK(NULL, "gpio", gpio)
_REGISTER_CLOCK(NULL, "usbd", usbd)
_REGISTER_CLOCK("tcc-uart.0", NULL, uart0)
_REGISTER_CLOCK("tcc-uart.2", NULL, uart2)
_REGISTER_CLOCK("tcc-i2c", NULL, i2c)
_REGISTER_CLOCK("tcc-uart.3", NULL, uart3)
_REGISTER_CLOCK(NULL, "ecc", ecc)
_REGISTER_CLOCK(NULL, "adc", adc)
_REGISTER_CLOCK("tcc-usbh.0", "usb", usbh0)
_REGISTER_CLOCK(NULL, "gdma0", gdma0)
_REGISTER_CLOCK(NULL, "lcd", lcd)
_REGISTER_CLOCK(NULL, "rtc", rtc)
_REGISTER_CLOCK(NULL, "nfc", nfc)
_REGISTER_CLOCK("tcc-mmc.0", NULL, sd0)
_REGISTER_CLOCK(NULL, "g2d", g2d)
_REGISTER_CLOCK(NULL, "gdma1", gdma1)
_REGISTER_CLOCK("tcc-uart.1", NULL, uart1)
_REGISTER_CLOCK("tcc-spi.0", NULL, spi0)
_REGISTER_CLOCK(NULL, "mscl", mscl)
_REGISTER_CLOCK("tcc-spi.1", NULL, spi1)
_REGISTER_CLOCK(NULL, "bdma", bdma)
_REGISTER_CLOCK(NULL, "adma0", adma0)
_REGISTER_CLOCK(NULL, "spdif", spdif)
_REGISTER_CLOCK(NULL, "scfg", scfg)
_REGISTER_CLOCK(NULL, "cid", cid)
_REGISTER_CLOCK("tcc-mmc.1", NULL, sd1)
_REGISTER_CLOCK("tcc-uart.4", NULL, uart4)
_REGISTER_CLOCK(NULL, "dai1", dai1)
_REGISTER_CLOCK(NULL, "adma1", adma1)
_REGISTER_CLOCK(NULL, "c3dec", c3dec)
_REGISTER_CLOCK("tcc-can.0", NULL, can0)
_REGISTER_CLOCK("tcc-can.1", NULL, can1)
_REGISTER_CLOCK(NULL, "gps", gps)
_REGISTER_CLOCK("tcc-gsb.0", NULL, gsb0)
_REGISTER_CLOCK("tcc-gsb.1", NULL, gsb1)
_REGISTER_CLOCK("tcc-gsb.2", NULL, gsb2)
_REGISTER_CLOCK("tcc-gsb.3", NULL, gsb3)
_REGISTER_CLOCK(NULL, "gdma2", gdma2)
_REGISTER_CLOCK(NULL, "gdma3", gdma3)
_REGISTER_CLOCK(NULL, "ddrc", ddrc)
_REGISTER_CLOCK("tcc-usbh.1", "usb", usbh1)
};
static struct clk *root_clk_by_index(enum root_clks src)
{
switch (src) {
case CLK_SRC_PLL0: return &pll0;
case CLK_SRC_PLL1: return &pll1;
case CLK_SRC_PLL2: return &pll2;
case CLK_SRC_PLL0DIV: return &pll0div;
case CLK_SRC_PLL1DIV: return &pll1div;
case CLK_SRC_PLL2DIV: return &pll2div;
case CLK_SRC_XI: return &xi;
case CLK_SRC_XTI: return &xti;
case CLK_SRC_XIDIV: return &xidiv;
case CLK_SRC_XTIDIV: return &xtidiv;
default: return NULL;
}
}
static void find_aclk_parent(struct clk *clk)
{
unsigned int src;
struct clk *clock;
if (!clk->aclkreg)
return;
src = __raw_readl(clk->aclkreg) >> ACLK_SEL_SHIFT;
src &= CLK_SRC_MASK;
clock = root_clk_by_index(src);
if (!clock)
return;
clk->parent = clock;
clk->set_parent = aclk_set_parent;
}
void __init tcc_clocks_init(unsigned long xi_freq, unsigned long xti_freq)
{
int i;
xi_rate = xi_freq;
xti_rate = xti_freq;
/* fixup parents and add the clock */
for (i = 0; i < ARRAY_SIZE(lookups); i++) {
find_aclk_parent(lookups[i].clk);
clkdev_add(&lookups[i]);
}
tcc8k_timer_init(&tcz, (void __iomem *)TIMER_BASE, INT_TC32);
}
arch/arm/mach-tcc8k/common.h deleted 100644 → 0
View file @ 273b5e51
#ifndef MACH_TCC8K_COMMON_H
#define MACH_TCC8K_COMMON_H
#include <linux/platform_device.h>
extern struct platform_device tcc_nand_device;
struct clk;
extern void tcc_clocks_init(unsigned long xi_freq, unsigned long xti_freq);
extern void tcc8k_timer_init(struct clk *clock, void __iomem *base, int irq);
extern void tcc8k_init_irq(void);
extern void tcc8k_map_common_io(void);
#endif
arch/arm/mach-tcc8k/devices.c deleted 100644 → 0
View file @ 273b5e51
/*
* linux/arch/arm/mach-tcc8k/devices.c
*
* Copyright (C) Telechips, Inc.
* Copyright (C) 2009 Hans J. Koch <hjk@linutronix.de>
*
* Licensed under the terms of GPL v2.
*
*/
#include <linux/dma-mapping.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <asm/mach/map.h>
#include <mach/tcc8k-regs.h>
#include <mach/irqs.h>
#include "common.h"
static u64 tcc8k_dmamask = DMA_BIT_MASK(32);
#ifdef CONFIG_MTD_NAND_TCC
/* NAND controller */
static struct resource tcc_nand_resources[] = {
{
.start = (resource_size_t)NFC_BASE,
.end = (resource_size_t)NFC_BASE + 0x7f,
.flags = IORESOURCE_MEM,
}, {
.start = INT_NFC,
.end = INT_NFC,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device tcc_nand_device = {
.name = "tcc_nand",
.id = 0,
.num_resources = ARRAY_SIZE(tcc_nand_resources),
.resource = tcc_nand_resources,
};
#endif
#ifdef CONFIG_MMC_TCC8K
/* MMC controller */
static struct resource tcc8k_mmc0_resource[] = {
{
.start = INT_SD0,
.end = INT_SD0,
.flags = IORESOURCE_IRQ,
},
};
static struct resource tcc8k_mmc1_resource[] = {
{
.start = INT_SD1,
.end = INT_SD1,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device tcc8k_mmc0_device = {
.name = "tcc-mmc",
.id = 0,
.num_resources = ARRAY_SIZE(tcc8k_mmc0_resource),
.resource = tcc8k_mmc0_resource,
.dev = {
.dma_mask = &tcc8k_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
}
};
struct platform_device tcc8k_mmc1_device = {
.name = "tcc-mmc",
.id = 1,
.num_resources = ARRAY_SIZE(tcc8k_mmc1_resource),
.resource = tcc8k_mmc1_resource,
.dev = {
.dma_mask = &tcc8k_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
}
};
static inline void tcc8k_init_mmc(void)
{
u32 reg = __raw_readl(GPIOPS_BASE + GPIOPS_FS1_OFFS);
reg |= GPIOPS_FS1_SDH0_BITS | GPIOPS_FS1_SDH1_BITS;
__raw_writel(reg, GPIOPS_BASE + GPIOPS_FS1_OFFS);
platform_device_register(&tcc8k_mmc0_device);
platform_device_register(&tcc8k_mmc1_device);
}
#else
static inline void tcc8k_init_mmc(void) { }
#endif
#ifdef CONFIG_USB_OHCI_HCD
static int tcc8k_ohci_init(struct device *dev)
{
u32 reg;
/* Use GPIO PK19 as VBUS control output */
reg = __raw_readl(GPIOPK_BASE + GPIOPK_FS0_OFFS);
reg &= ~(1 << 19);
__raw_writel(reg, GPIOPK_BASE + GPIOPK_FS0_OFFS);
reg = __raw_readl(GPIOPK_BASE + GPIOPK_FS1_OFFS);
reg &= ~(1 << 19);
__raw_writel(reg, GPIOPK_BASE + GPIOPK_FS1_OFFS);
reg = __raw_readl(GPIOPK_BASE + GPIOPK_DOE_OFFS);
reg |= (1 << 19);
__raw_writel(reg, GPIOPK_BASE + GPIOPK_DOE_OFFS);
/* Turn on VBUS */
reg = __raw_readl(GPIOPK_BASE + GPIOPK_DAT_OFFS);
reg |= (1 << 19);
__raw_writel(reg, GPIOPK_BASE + GPIOPK_DAT_OFFS);
return 0;
}
static struct resource tcc8k_ohci0_resources[] = {
[0] = {
.start = (resource_size_t)USBH0_BASE,
.end = (resource_size_t)USBH0_BASE + 0x5c,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = INT_USBH0,
.end = INT_USBH0,
.flags = IORESOURCE_IRQ,
}
};
static struct resource tcc8k_ohci1_resources[] = {
[0] = {
.start = (resource_size_t)USBH1_BASE,
.end = (resource_size_t)USBH1_BASE + 0x5c,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = INT_USBH1,
.end = INT_USBH1,
.flags = IORESOURCE_IRQ,
}
};
static struct tccohci_platform_data tcc8k_ohci0_platform_data = {
.controller = 0,
.port_mode = PMM_PERPORT_MODE,
.init = tcc8k_ohci_init,
};
static struct tccohci_platform_data tcc8k_ohci1_platform_data = {
.controller = 1,
.port_mode = PMM_PERPORT_MODE,
.init = tcc8k_ohci_init,
};
static struct platform_device ohci0_device = {
.name = "tcc-ohci",
.id = 0,
.dev = {
.dma_mask = &tcc8k_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &tcc8k_ohci0_platform_data,
},
.num_resources = ARRAY_SIZE(tcc8k_ohci0_resources),
.resource = tcc8k_ohci0_resources,
};
static struct platform_device ohci1_device = {
.name = "tcc-ohci",
.id = 1,
.dev = {
.dma_mask = &tcc8k_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &tcc8k_ohci1_platform_data,
},
.num_resources = ARRAY_SIZE(tcc8k_ohci1_resources),
.resource = tcc8k_ohci1_resources,
};
static void __init tcc8k_init_usbhost(void)
{
platform_device_register(&ohci0_device);
platform_device_register(&ohci1_device);
}
#else
static void __init tcc8k_init_usbhost(void) { }
#endif
/* USB device controller*/
#ifdef CONFIG_USB_GADGET_TCC8K
static struct resource udc_resources[] = {
[0] = {
.start = INT_USBD,
.end = INT_USBD,
.flags = IORESOURCE_IRQ,
},
[1] = {
.start = INT_UDMA,
.end = INT_UDMA,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device tcc8k_udc_device = {
.name = "tcc-udc",
.id = 0,
.resource = udc_resources,
.num_resources = ARRAY_SIZE(udc_resources),
.dev = {
.dma_mask = &tcc8k_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
static void __init tcc8k_init_usb_gadget(void)
{
platform_device_register(&tcc8k_udc_device);
}
#else
static void __init tcc8k_init_usb_gadget(void) { }
#endif /* CONFIG_USB_GADGET_TCC83X */
static int __init tcc8k_init_devices(void)
{
tcc8k_init_mmc();
tcc8k_init_usbhost();
tcc8k_init_usb_gadget();
return 0;
}
arch_initcall(tcc8k_init_devices);
arch/arm/mach-tcc8k/io.c deleted 100644 → 0
View file @ 273b5e51
/*
* linux/arch/arm/mach-tcc8k/io.c
*
* (C) 2009 Hans J. Koch <hjk@linutronix.de>
*
* derived from TCC83xx io.c
* Copyright (C) Telechips, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <asm/mach/map.h>
#include <mach/tcc8k-regs.h>
/*
* The machine specific code may provide the extra mapping besides the
* default mapping provided here.
*/
static struct map_desc tcc8k_io_desc[] __initdata = {
{
.virtual = (unsigned long)CS1_BASE_VIRT,
.pfn = __phys_to_pfn(CS1_BASE),
.length = CS1_SIZE,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)AHB_PERI_BASE_VIRT,
.pfn = __phys_to_pfn(AHB_PERI_BASE),
.length = AHB_PERI_SIZE,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)APB0_PERI_BASE_VIRT,
.pfn = __phys_to_pfn(APB0_PERI_BASE),
.length = APB0_PERI_SIZE,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)APB1_PERI_BASE_VIRT,
.pfn = __phys_to_pfn(APB1_PERI_BASE),
.length = APB1_PERI_SIZE,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)EXT_MEM_CTRL_BASE_VIRT,
.pfn = __phys_to_pfn(EXT_MEM_CTRL_BASE),
.length = EXT_MEM_CTRL_SIZE,
.type = MT_DEVICE,
},
};
/*
* Maps common IO regions for tcc8k.
*
*/
void __init tcc8k_map_common_io(void)
{
iotable_init(tcc8k_io_desc, ARRAY_SIZE(tcc8k_io_desc));
}
arch/arm/mach-tcc8k/irq.c deleted 100644 → 0
View file @ 273b5e51
/*
* Copyright (C) Telechips, Inc.
* Copyright (C) 2009-2010 Hans J. Koch <hjk@linutronix.de>
*
* Licensed under the terms of the GNU GPL version 2.
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <asm/irq.h>
#include <asm/mach/irq.h>
#include <mach/tcc8k-regs.h>
#include <mach/irqs.h>
#include "common.h"
/* Disable IRQ */
static void tcc8000_mask_ack_irq0(struct irq_data *d)
{
PIC0_IEN &= ~(1 << d->irq);
PIC0_CREQ |= (1 << d->irq);
}
static void tcc8000_mask_ack_irq1(struct irq_data *d)
{
PIC1_IEN &= ~(1 << (d->irq - 32));
PIC1_CREQ |= (1 << (d->irq - 32));
}
static void tcc8000_mask_irq0(struct irq_data *d)
{
PIC0_IEN &= ~(1 << d->irq);
}
static void tcc8000_mask_irq1(struct irq_data *d)
{
PIC1_IEN &= ~(1 << (d->irq - 32));
}
static void tcc8000_ack_irq0(struct irq_data *d)
{
PIC0_CREQ |= (1 << d->irq);
}
static void tcc8000_ack_irq1(struct irq_data *d)
{
PIC1_CREQ |= (1 << (d->irq - 32));
}
/* Enable IRQ */
static void tcc8000_unmask_irq0(struct irq_data *d)
{
PIC0_IEN |= (1 << d->irq);
PIC0_INTOEN |= (1 << d->irq);
}
static void tcc8000_unmask_irq1(struct irq_data *d)
{
PIC1_IEN |= (1 << (d->irq - 32));
PIC1_INTOEN |= (1 << (d->irq - 32));
}
static struct irq_chip tcc8000_irq_chip0 = {
.name = "tcc_irq0",
.irq_mask = tcc8000_mask_irq0,
.irq_ack = tcc8000_ack_irq0,
.irq_mask_ack = tcc8000_mask_ack_irq0,
.irq_unmask = tcc8000_unmask_irq0,
};
static struct irq_chip tcc8000_irq_chip1 = {
.name = "tcc_irq1",
.irq_mask = tcc8000_mask_irq1,
.irq_ack = tcc8000_ack_irq1,
.irq_mask_ack = tcc8000_mask_ack_irq1,
.irq_unmask = tcc8000_unmask_irq1,
};
void __init tcc8k_init_irq(void)
{
int irqno;
/* Mask and clear all interrupts */
PIC0_IEN = 0x00000000;
PIC0_CREQ = 0xffffffff;
PIC1_IEN = 0x00000000;
PIC1_CREQ = 0xffffffff;
PIC0_MEN0 = 0x00000003;
PIC1_MEN1 = 0x00000003;
PIC1_MEN = 0x00000003;
/* let all IRQs be level triggered */
PIC0_TMODE = 0xffffffff;
PIC1_TMODE = 0xffffffff;
/* all IRQs are IRQs (not FIQs) */
PIC0_IRQSEL = 0xffffffff;
PIC1_IRQSEL = 0xffffffff;
for (irqno = 0; irqno < NR_IRQS; irqno++) {
if (irqno < 32)
irq_set_chip(irqno, &tcc8000_irq_chip0);
else
irq_set_chip(irqno, &tcc8000_irq_chip1);
irq_set_handler(irqno, handle_level_irq);
set_irq_flags(irqno, IRQF_VALID);
}
}
arch/arm/mach-tcc8k/time.c deleted 100644 → 0
View file @ 273b5e51
/*
* TCC8000 system timer setup
*
* (C) 2009 Hans J. Koch <hjk@linutronix.de>
*
* Licensed under the terms of the GPL version 2.
*
*/
#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <asm/mach/time.h>
#include <mach/tcc8k-regs.h>
#include <mach/irqs.h>
#include "common.h"
static void __iomem *timer_base;
static int tcc_set_next_event(unsigned long evt,
struct clock_event_device *unused)
{
unsigned long reg = __raw_readl(timer_base + TC32MCNT_OFFS);
__raw_writel(reg + evt, timer_base + TC32CMP0_OFFS);
return 0;
}
static void tcc_set_mode(enum clock_event_mode mode,
struct clock_event_device *evt)
{
unsigned long tc32irq;
switch (mode) {
case CLOCK_EVT_MODE_ONESHOT:
tc32irq = __raw_readl(timer_base + TC32IRQ_OFFS);
tc32irq |= TC32IRQ_IRQEN0;
__raw_writel(tc32irq, timer_base + TC32IRQ_OFFS);
break;
case CLOCK_EVT_MODE_SHUTDOWN:
case CLOCK_EVT_MODE_UNUSED:
tc32irq = __raw_readl(timer_base + TC32IRQ_OFFS);
tc32irq &= ~TC32IRQ_IRQEN0;
__raw_writel(tc32irq, timer_base + TC32IRQ_OFFS);
break;
case CLOCK_EVT_MODE_PERIODIC:
case CLOCK_EVT_MODE_RESUME:
break;
}
}
static irqreturn_t tcc8k_timer_interrupt(int irq, void *dev_id)
{
struct clock_event_device *evt = dev_id;
/* Acknowledge TC32 interrupt by reading TC32IRQ */
__raw_readl(timer_base + TC32IRQ_OFFS);
evt->event_handler(evt);
return IRQ_HANDLED;
}
static struct clock_event_device clockevent_tcc = {
.name = "tcc_timer1",
.features = CLOCK_EVT_FEAT_ONESHOT,
.shift = 32,
.set_mode = tcc_set_mode,
.set_next_event = tcc_set_next_event,
.rating = 200,
};
static struct irqaction tcc8k_timer_irq = {
.name = "TC32_timer",
.flags = IRQF_DISABLED | IRQF_TIMER,
.handler = tcc8k_timer_interrupt,
.dev_id = &clockevent_tcc,
};
static int __init tcc_clockevent_init(struct clk *clock)
{
unsigned int c = clk_get_rate(clock);
clocksource_mmio_init(timer_base + TC32MCNT_OFFS, "tcc_tc32", c,
200, 32, clocksource_mmio_readl_up);
clockevent_tcc.mult = div_sc(c, NSEC_PER_SEC,
clockevent_tcc.shift);
clockevent_tcc.max_delta_ns =
clockevent_delta2ns(0xfffffffe, &clockevent_tcc);
clockevent_tcc.min_delta_ns =
clockevent_delta2ns(0xff, &clockevent_tcc);
clockevent_tcc.cpumask = cpumask_of(0);
clockevents_register_device(&clockevent_tcc);
return 0;
}
void __init tcc8k_timer_init(struct clk *clock, void __iomem *base, int irq)
{
u32 reg;
timer_base = base;
tcc8k_timer_irq.irq = irq;
/* Enable clocks */
clk_enable(clock);
/* Initialize 32-bit timer */
reg = __raw_readl(timer_base + TC32EN_OFFS);
reg &= ~TC32EN_ENABLE; /* Disable timer */
__raw_writel(reg, timer_base + TC32EN_OFFS);
/* Free running timer, counting from 0 to 0xffffffff */
__raw_writel(0, timer_base + TC32EN_OFFS);
__raw_writel(0, timer_base + TC32LDV_OFFS);
reg = __raw_readl(timer_base + TC32IRQ_OFFS);
reg |= TC32IRQ_IRQEN0; /* irq at match with CMP0 */
__raw_writel(reg, timer_base + TC32IRQ_OFFS);
__raw_writel(TC32EN_ENABLE, timer_base + TC32EN_OFFS);
tcc_clockevent_init(clock);
setup_irq(irq, &tcc8k_timer_irq);
}
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