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Commit 010da09e authored by Olof Johansson's avatar Olof Johansson
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Merge tag 'hisi-arm64-dt-for-4.13-v2' of git://github.com/hisilicon/linux-hisi into next/dt64 

ARM64: DT: Hisilicon SoC DT updates for 4.13

- Add and update Hi3660-Hikey960 board, Hi3660 PCIe RC, Hi6421v530 MFD and
  Hi3660 MMC binding
- Add and refine devices support for Hi3660-Hikey 960 including clock, reset,
  I2C, GPIO, UART, Bluetooth, RTC, Power Key, LED, SPI, timer, PMIC, regulator,
  sd/sdio and WiFi
- Add k3-dma and i2s/hdmi audio support based on audio-card-graph method for
  Hikey board

* tag 'hisi-arm64-dt-for-4.13-v2' of git://github.com/hisilicon/linux-hisi: (21 commits)
  arm64: dts: hi6220: Add k3-dma and i2s/hdmi audio support
  arm64: dts: hi3660-hikey960: add nodes for WiFi
  arm64: dts: hi3660: add sd/sdio device nodes
  dt-bindings: mmc: dw_mmc-k3: add document of hi3660 mmc
  arm64: dts: hikey960: add device node for pmic and regulators
  dt-bindings: mfd: hi6421: Add hi6421v530 compatible string
  arm64: dts: hisi: add kirin pcie node
  dt-bindings: PCI: hisi: Add document for PCIe of Kirin SoCs
  arm64: dts: hi3660: add sp804 timer node
  arm64: dts: hi3660: add spi device nodes
  arm64: dts: hikey960: add LED nodes
  arm64: dts: hi3660: add power key dts node
  arm64: dts: hi3660: Add pl031 rtc node
  arm64: dts: hikey960: add WL1837 Bluetooth device node
  arm64: dts: hi3660: Add uarts nodes
  arm64: dts: hi3660: add gpio dtsi file for Hisilicon Hi3660 SOC
  arm64: dts: Add I2C nodes for Hi3660
  arm64: dts: hi3660: add resources for clock and reset
  arm64: dts: hikey960: pinctrl: add more pinmux and pinconfig
  arm64: dts: hisilicon: update compatible string for hikey960
  ...
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 2003c78b 0cf6a8e2
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Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
View file @ 010da09e
...@@ -4,6 +4,10 @@ Hi3660 SoC ...@@ -4,6 +4,10 @@ Hi3660 SoC
Required root node properties: Required root node properties:
- compatible = "hisilicon,hi3660"; - compatible = "hisilicon,hi3660";
HiKey960 Board
Required root node properties:
- compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660";
Hi3798cv200 SoC Hi3798cv200 SoC
Required root node properties: Required root node properties:
- compatible = "hisilicon,hi3798cv200"; - compatible = "hisilicon,hi3798cv200";
......
Documentation/devicetree/bindings/mfd/hi6421.txt
View file @ 010da09e
* HI6421 Multi-Functional Device (MFD), by HiSilicon Ltd. * HI6421 Multi-Functional Device (MFD), by HiSilicon Ltd.
Required parent device properties: Required parent device properties:
- compatible : contains "hisilicon,hi6421-pmic"; - compatible : One of the following chip-specific strings:
"hisilicon,hi6421-pmic";
"hisilicon,hi6421v530-pmic";
- reg : register range space of hi6421; - reg : register range space of hi6421;
Supported Hi6421 sub-devices include: Supported Hi6421 sub-devices include:
......
Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt
View file @ 010da09e
...@@ -12,6 +12,7 @@ extensions to the Synopsys Designware Mobile Storage Host Controller. ...@@ -12,6 +12,7 @@ extensions to the Synopsys Designware Mobile Storage Host Controller.
Required Properties: Required Properties:
* compatible: should be one of the following. * compatible: should be one of the following.
- "hisilicon,hi3660-dw-mshc": for controllers with hi3660 specific extensions.
- "hisilicon,hi4511-dw-mshc": for controllers with hi4511 specific extensions. - "hisilicon,hi4511-dw-mshc": for controllers with hi4511 specific extensions.
- "hisilicon,hi6220-dw-mshc": for controllers with hi6220 specific extensions. - "hisilicon,hi6220-dw-mshc": for controllers with hi6220 specific extensions.
......
Documentation/devicetree/bindings/pci/kirin-pcie.txt 0 → 100644
View file @ 010da09e
HiSilicon Kirin SoCs PCIe host DT description
Kirin PCIe host controller is based on Designware PCI core.
It shares common functions with PCIe Designware core driver
and inherits common properties defined in
Documentation/devicetree/bindings/pci/designware-pci.txt.
Additional properties are described here:
Required properties
- compatible:
"hisilicon,kirin960-pcie" for PCIe of Kirin960 SoC
- reg: Should contain rc_dbi, apb, phy, config registers location and length.
- reg-names: Must include the following entries:
"dbi": controller configuration registers;
"apb": apb Ctrl register defined by Kirin;
"phy": apb PHY register defined by Kirin;
"config": PCIe configuration space registers.
- reset-gpios: The gpio to generate PCIe perst assert and deassert signal.
Optional properties:
Example based on kirin960:
pcie@f4000000 {
compatible = "hisilicon,kirin-pcie";
reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>,
<0x0 0xf3f20000 0x0 0x40000>, <0x0 0xF4000000 0 0x2000>;
reg-names = "dbi","apb","phy", "config";
bus-range = <0x0 0x1>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges = <0x02000000 0x0 0x00000000 0x0 0xf5000000 0x0 0x2000000>;
num-lanes = <1>;
#interrupt-cells = <1>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <0x0 0 0 1 &gic 0 0 0 282 4>,
<0x0 0 0 2 &gic 0 0 0 283 4>,
<0x0 0 0 3 &gic 0 0 0 284 4>,
<0x0 0 0 4 &gic 0 0 0 285 4>;
clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
<&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
<&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
<&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
<&crg_ctrl HI3660_ACLK_GATE_PCIE>;
clock-names = "pcie_phy_ref", "pcie_aux",
"pcie_apb_phy", "pcie_apb_sys", "pcie_aclk";
reset-gpios = <&gpio11 1 0 >;
};
arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
View file @ 010da09e
...@@ -9,17 +9,28 @@ ...@@ -9,17 +9,28 @@
#include "hi3660.dtsi" #include "hi3660.dtsi"
#include "hikey960-pinctrl.dtsi" #include "hikey960-pinctrl.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ { / {
model = "HiKey960"; model = "HiKey960";
compatible = "hisilicon,hi3660"; compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660";
aliases { aliases {
serial5 = &uart5; /* console UART */ mshc1 = &dwmmc1;
mshc2 = &dwmmc2;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
serial5 = &uart5;
serial6 = &uart6;
}; };
chosen { chosen {
stdout-path = "serial5:115200n8"; stdout-path = "serial6:115200n8";
}; };
memory@0 { memory@0 {
...@@ -27,8 +38,206 @@ memory@0 { ...@@ -27,8 +38,206 @@ memory@0 {
/* rewrite this at bootloader */ /* rewrite this at bootloader */
reg = <0x0 0x0 0x0 0x0>; reg = <0x0 0x0 0x0 0x0>;
}; };
keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pwr_key_pmx_func &pwr_key_cfg_func>;
power {
wakeup-source;
gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
label = "GPIO Power";
linux,code = <KEY_POWER>;
};
};
leds {
compatible = "gpio-leds";
user_led1 {
label = "user_led1";
/* gpio_150_user_led1 */
gpios = <&gpio18 6 0>;
linux,default-trigger = "heartbeat";
};
user_led2 {
label = "user_led2";
/* gpio_151_user_led2 */
gpios = <&gpio18 7 0>;
linux,default-trigger = "mmc0";
};
user_led3 {
label = "user_led3";
/* gpio_189_user_led3 */
gpios = <&gpio23 5 0>;
default-state = "off";
};
user_led4 {
label = "user_led4";
/* gpio_190_user_led4 */
gpios = <&gpio23 6 0>;
linux,default-trigger = "cpu0";
};
wlan_active_led {
label = "wifi_active";
/* gpio_205_wifi_active */
gpios = <&gpio25 5 0>;
linux,default-trigger = "phy0tx";
default-state = "off";
};
bt_active_led {
label = "bt_active";
gpios = <&gpio25 7 0>;
/* gpio_207_user_led1 */
linux,default-trigger = "hci0-power";
default-state = "off";
};
};
pmic: pmic@fff34000 {
compatible = "hisilicon,hi6421v530-pmic";
reg = <0x0 0xfff34000 0x0 0x1000>;
interrupt-controller;
#interrupt-cells = <2>;
regulators {
ldo3: LDO3 { /* HDMI */
regulator-name = "VOUT3_1V85";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2200000>;
regulator-enable-ramp-delay = <120>;
};
ldo9: LDO9 { /* SDCARD I/O */
regulator-name = "VOUT9_1V8_2V95";
regulator-min-microvolt = <1750000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <240>;
};
ldo11: LDO11 { /* Low Speed Connector */
regulator-name = "VOUT11_1V8_2V95";
regulator-min-microvolt = <1750000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <240>;
};
ldo15: LDO15 { /* UFS VCC */
regulator-name = "VOUT15_3V0";
regulator-min-microvolt = <1750000>;
regulator-max-microvolt = <3000000>;
regulator-boot-on;
regulator-always-on;
regulator-enable-ramp-delay = <120>;
};
ldo16: LDO16 { /* SD VDD */
regulator-name = "VOUT16_2V95";
regulator-min-microvolt = <1750000>;
regulator-max-microvolt = <3000000>;
regulator-enable-ramp-delay = <360>;
};
};
};
wlan_en: wlan-en-1-8v {
compatible = "regulator-fixed";
regulator-name = "wlan-en-regulator";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
/* GPIO_051_WIFI_EN */
gpio = <&gpio6 3 0>;
/* WLAN card specific delay */
startup-delay-us = <70000>;
enable-active-high;
};
};
&i2c0 {
/* On Low speed expansion */
label = "LS-I2C0";
status = "okay";
};
&i2c1 {
status = "okay";
adv7533: adv7533@39 {
status = "ok";
compatible = "adi,adv7533";
reg = <0x39>;
};
};
&i2c7 {
/* On Low speed expansion */
label = "LS-I2C1";
status = "okay";
};
&uart3 {
/* On Low speed expansion */
label = "LS-UART0";
status = "okay";
};
&uart4 {
status = "okay";
bluetooth {
compatible = "ti,wl1837-st";
enable-gpios = <&gpio15 6 GPIO_ACTIVE_HIGH>;
max-speed = <921600>;
};
}; };
&uart5 { &uart6 {
/* On Low speed expansion */
label = "LS-UART1";
status = "okay"; status = "okay";
}; };
&spi2 {
/* On Low speed expansion */
label = "LS-SPI0";
status = "okay";
};
&spi3 {
/* On High speed expansion */
label = "HS-SPI1";
status = "okay";
};
&dwmmc1 {
vmmc-supply = <&ldo16>;
vqmmc-supply = <&ldo9>;
status = "okay";
};
&dwmmc2 { /* WIFI */
broken-cd;
/* WL_EN */
vmmc-supply = <&wlan_en>;
ti,non-removable;
non-removable;
#address-cells = <0x1>;
#size-cells = <0x0>;
status = "ok";
wlcore: wlcore@2 {
compatible = "ti,wl1837";
reg = <2>; /* sdio func num */
/* WL_IRQ, GPIO_179_WL_WAKEUP_AP */
interrupt-parent = <&gpio22>;
interrupts = <3 IRQ_TYPE_EDGE_RISING>;
};
};
arch/arm64/boot/dts/hisilicon/hi3660.dtsi
View file @ 010da09e
...@@ -5,6 +5,7 @@ ...@@ -5,6 +5,7 @@
*/ */
#include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/hi3660-clock.h>
/ { / {
compatible = "hisilicon,hi3660"; compatible = "hisilicon,hi3660";
...@@ -141,19 +142,710 @@ soc { ...@@ -141,19 +142,710 @@ soc {
#size-cells = <2>; #size-cells = <2>;
ranges; ranges;
fixed_uart5: fixed_19_2M { crg_ctrl: crg_ctrl@fff35000 {
compatible = "fixed-clock"; compatible = "hisilicon,hi3660-crgctrl", "syscon";
#clock-cells = <0>; reg = <0x0 0xfff35000 0x0 0x1000>;
clock-frequency = <19200000>; #clock-cells = <1>;
clock-output-names = "fixed:uart5";
}; };
uart5: uart@fdf05000 { crg_rst: crg_rst_controller {
compatible = "hisilicon,hi3660-reset";
#reset-cells = <2>;
hisi,rst-syscon = <&crg_ctrl>;
};
pctrl: pctrl@e8a09000 {
compatible = "hisilicon,hi3660-pctrl", "syscon";
reg = <0x0 0xe8a09000 0x0 0x2000>;
#clock-cells = <1>;
};
pmuctrl: crg_ctrl@fff34000 {
compatible = "hisilicon,hi3660-pmuctrl", "syscon";
reg = <0x0 0xfff34000 0x0 0x1000>;
#clock-cells = <1>;
};
sctrl: sctrl@fff0a000 {
compatible = "hisilicon,hi3660-sctrl", "syscon";
reg = <0x0 0xfff0a000 0x0 0x1000>;
#clock-cells = <1>;
};
iomcu: iomcu@ffd7e000 {
compatible = "hisilicon,hi3660-iomcu", "syscon";
reg = <0x0 0xffd7e000 0x0 0x1000>;
#clock-cells = <1>;
};
iomcu_rst: reset {
compatible = "hisilicon,hi3660-reset";
hisi,rst-syscon = <&iomcu>;
#reset-cells = <2>;
};
dual_timer0: timer@fff14000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x0 0xfff14000 0x0 0x1000>;
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg_ctrl HI3660_OSC32K>,
<&crg_ctrl HI3660_OSC32K>,
<&crg_ctrl HI3660_OSC32K>;
clock-names = "timer1", "timer2", "apb_pclk";
};
i2c0: i2c@ffd71000 {
compatible = "snps,designware-i2c";
reg = <0x0 0xffd71000 0x0 0x1000>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <400000>;
clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>;
resets = <&iomcu_rst 0x20 3>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
status = "disabled";
};
i2c1: i2c@ffd72000 {
compatible = "snps,designware-i2c";
reg = <0x0 0xffd72000 0x0 0x1000>;
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <400000>;
clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>;
resets = <&iomcu_rst 0x20 4>;
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
status = "disabled";
};
i2c3: i2c@fdf0c000 {
compatible = "snps,designware-i2c";
reg = <0x0 0xfdf0c000 0x0 0x1000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <400000>;
clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>;
resets = <&crg_rst 0x78 7>;
pinctrl-names = "default";
pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>;
status = "disabled";
};
i2c7: i2c@fdf0b000 {
compatible = "snps,designware-i2c";
reg = <0x0 0xfdf0b000 0x0 0x1000>;
interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <400000>;
clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>;
resets = <&crg_rst 0x60 14>;
pinctrl-names = "default";
pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>;
status = "disabled";
};
uart0: serial@fdf02000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xfdf02000 0x0 0x1000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>,
<&crg_ctrl HI3660_PCLK>;
clock-names = "uartclk", "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>;
status = "disabled";
};
uart1: serial@fdf00000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xfdf00000 0x0 0x1000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>,
<&crg_ctrl HI3660_CLK_GATE_UART1>;
clock-names = "uartclk", "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>;
status = "disabled";
};
uart2: serial@fdf03000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xfdf03000 0x0 0x1000>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>,
<&crg_ctrl HI3660_PCLK>;
clock-names = "uartclk", "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
status = "disabled";
};
uart3: serial@ffd74000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xffd74000 0x0 0x1000>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg_ctrl HI3660_FACTOR_UART3>,
<&crg_ctrl HI3660_PCLK>;
clock-names = "uartclk", "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
status = "disabled";
};
uart4: serial@fdf01000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xfdf01000 0x0 0x1000>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>,
<&crg_ctrl HI3660_CLK_GATE_UART4>;
clock-names = "uartclk", "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
status = "disabled";
};
uart5: serial@fdf05000 {
compatible = "arm,pl011", "arm,primecell"; compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xfdf05000 0x0 0x1000>; reg = <0x0 0xfdf05000 0x0 0x1000>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&fixed_uart5 &fixed_uart5>; clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>,
<&crg_ctrl HI3660_CLK_GATE_UART5>;
clock-names = "uartclk", "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&uart5_pmx_func &uart5_cfg_func>;
status = "disabled";
};
uart6: serial@fff32000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xfff32000 0x0 0x1000>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg_ctrl HI3660_CLK_UART6>,
<&crg_ctrl HI3660_PCLK>;
clock-names = "uartclk", "apb_pclk"; clock-names = "uartclk", "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>;
status = "disabled";
};
rtc0: rtc@fff04000 {
compatible = "arm,pl031", "arm,primecell";
reg = <0x0 0Xfff04000 0x0 0x1000>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg_ctrl HI3660_PCLK>;
clock-names = "apb_pclk";
};
gpio0: gpio@e8a0b000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0 0xe8a0b000 0 0x1000>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 1 0 7>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3660_PCLK_GPIO0>;
clock-names = "apb_pclk";
};
gpio1: gpio@e8a0c000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0 0xe8a0c000 0 0x1000>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 1 7 7>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3660_PCLK_GPIO1>;
clock-names = "apb_pclk";
};
gpio2: gpio@e8a0d000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0 0xe8a0d000 0 0x1000>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 14 8>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3660_PCLK_GPIO2>;
clock-names = "apb_pclk";
};
gpio3: gpio@e8a0e000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0 0xe8a0e000 0 0x1000>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 22 8>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3660_PCLK_GPIO3>;
clock-names = "apb_pclk";
};
gpio4: gpio@e8a0f000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0 0xe8a0f000 0 0x1000>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 30 8>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3660_PCLK_GPIO4>;
clock-names = "apb_pclk";
};
gpio5: gpio@e8a10000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0 0xe8a10000 0 0x1000>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 38 8>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3660_PCLK_GPIO5>;
clock-names = "apb_pclk";
};
gpio6: gpio@e8a11000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0 0xe8a11000 0 0x1000>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 46 8>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3660_PCLK_GPIO6>;
clock-names = "apb_pclk";
};
gpio7: gpio@e8a12000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0 0xe8a12000 0 0x1000>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 54 8>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3660_PCLK_GPIO7>;
clock-names = "apb_pclk";
};
gpio8: gpio@e8a13000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0 0xe8a13000 0 0x1000>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 62 8>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3660_PCLK_GPIO8>;
clock-names = "apb_pclk";
};
gpio9: gpio@e8a14000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0 0xe8a14000 0 0x1000>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 70 8>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3660_PCLK_GPIO9>;
clock-names = "apb_pclk";
};
gpio10: gpio@e8a15000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0 0xe8a15000 0 0x1000>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 78 8>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3660_PCLK_GPIO10>;
clock-names = "apb_pclk";
};
gpio11: gpio@e8a16000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0 0xe8a16000 0 0x1000>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 86 8>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3660_PCLK_GPIO11>;
clock-names = "apb_pclk";
};
gpio12: gpio@e8a17000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0 0xe8a17000 0 0x1000>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3660_PCLK_GPIO12>;
clock-names = "apb_pclk";
};
gpio13: gpio@e8a18000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0 0xe8a18000 0 0x1000>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 102 8>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3660_PCLK_GPIO13>;
clock-names = "apb_pclk";
};
gpio14: gpio@e8a19000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0 0xe8a19000 0 0x1000>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 110 8>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3660_PCLK_GPIO14>;
clock-names = "apb_pclk";
};
gpio15: gpio@e8a1a000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0 0xe8a1a000 0 0x1000>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 118 6>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3660_PCLK_GPIO15>;
clock-names = "apb_pclk";
};
gpio16: gpio@e8a1b000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0 0xe8a1b000 0 0x1000>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3660_PCLK_GPIO16>;
clock-names = "apb_pclk";
};
gpio17: gpio@e8a1c000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0 0xe8a1c000 0 0x1000>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3660_PCLK_GPIO17>;
clock-names = "apb_pclk";
};
gpio18: gpio@ff3b4000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0 0xff3b4000 0 0x1000>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx2 0 0 8>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3660_PCLK_GPIO18>;
clock-names = "apb_pclk";
};
gpio19: gpio@ff3b5000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0 0xff3b5000 0 0x1000>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx2 0 8 4>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3660_PCLK_GPIO19>;
clock-names = "apb_pclk";
};
gpio20: gpio@e8a1f000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0 0xe8a1f000 0 0x1000>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx1 0 0 6>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3660_PCLK_GPIO20>;
clock-names = "apb_pclk";
};
gpio21: gpio@e8a20000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0 0xe8a20000 0 0x1000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&pmx3 0 0 6>;
clocks = <&crg_ctrl HI3660_PCLK_GPIO21>;
clock-names = "apb_pclk";
};
gpio22: gpio@fff0b000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0 0xfff0b000 0 0x1000>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
/* GPIO176 */
gpio-ranges = <&pmx4 2 0 6>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&sctrl HI3660_PCLK_AO_GPIO0>;
clock-names = "apb_pclk";
};
gpio23: gpio@fff0c000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0 0xfff0c000 0 0x1000>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
/* GPIO184 */
gpio-ranges = <&pmx4 0 6 7>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&sctrl HI3660_PCLK_AO_GPIO1>;
clock-names = "apb_pclk";
};
gpio24: gpio@fff0d000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0 0xfff0d000 0 0x1000>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
/* GPIO192 */
gpio-ranges = <&pmx4 0 13 8>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&sctrl HI3660_PCLK_AO_GPIO2>;
clock-names = "apb_pclk";
};
gpio25: gpio@fff0e000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0 0xfff0e000 0 0x1000>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
/* GPIO200 */
gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&sctrl HI3660_PCLK_AO_GPIO3>;
clock-names = "apb_pclk";
};
gpio26: gpio@fff0f000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0 0xfff0f000 0 0x1000>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
/* GPIO208 */
gpio-ranges = <&pmx4 0 28 8>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&sctrl HI3660_PCLK_AO_GPIO4>;
clock-names = "apb_pclk";
};
gpio27: gpio@fff10000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0 0xfff10000 0 0x1000>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
/* GPIO216 */
gpio-ranges = <&pmx4 0 36 6>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&sctrl HI3660_PCLK_AO_GPIO5>;
clock-names = "apb_pclk";
};
gpio28: gpio@fff1d000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0 0xfff1d000 0 0x1000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&sctrl HI3660_PCLK_AO_GPIO6>;
clock-names = "apb_pclk";
};
spi2: spi@ffd68000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x0 0xffd68000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>;
clock-names = "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&spi2_pmx_func>;
num-cs = <1>;
cs-gpios = <&gpio27 2 0>;
status = "disabled";
};
spi3: spi@ff3b3000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x0 0xff3b3000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>;
clock-names = "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&spi3_pmx_func>;
num-cs = <1>;
cs-gpios = <&gpio18 5 0>;
status = "disabled";
};
pcie@f4000000 {
compatible = "hisilicon,kirin960-pcie";
reg = <0x0 0xf4000000 0x0 0x1000>,
<0x0 0xff3fe000 0x0 0x1000>,
<0x0 0xf3f20000 0x0 0x40000>,
<0x0 0xf5000000 0x0 0x2000>;
reg-names = "dbi", "apb", "phy", "config";
bus-range = <0x0 0x1>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges = <0x02000000 0x0 0x00000000
0x0 0xf6000000
0x0 0x02000000>;
num-lanes = <1>;
#interrupt-cells = <1>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <0x0 0 0 1
&gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
<0x0 0 0 2
&gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
<0x0 0 0 3
&gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
<0x0 0 0 4
&gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
<&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
<&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
<&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
<&crg_ctrl HI3660_ACLK_GATE_PCIE>;
clock-names = "pcie_phy_ref", "pcie_aux",
"pcie_apb_phy", "pcie_apb_sys",
"pcie_aclk";
reset-gpios = <&gpio11 1 0 >;
};
/* SD */
dwmmc1: dwmmc1@ff37f000 {
#address-cells = <1>;
#size-cells = <0>;
cd-inverted;
compatible = "hisilicon,hi3660-dw-mshc";
num-slots = <1>;
bus-width = <0x4>;
disable-wp;
cap-sd-highspeed;
supports-highspeed;
card-detect-delay = <200>;
reg = <0x0 0xff37f000 0x0 0x1000>;
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg_ctrl HI3660_CLK_GATE_SD>,
<&crg_ctrl HI3660_HCLK_GATE_SD>;
clock-names = "ciu", "biu";
clock-frequency = <3200000>;
resets = <&crg_rst 0x94 18>;
cd-gpios = <&gpio25 3 0>;
hisilicon,peripheral-syscon = <&sctrl>;
pinctrl-names = "default";
pinctrl-0 = <&sd_pmx_func
&sd_clk_cfg_func
&sd_cfg_func>;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
status = "disabled";
slot@0 {
reg = <0x0>;
bus-width = <4>;
disable-wp;
};
};
/* SDIO */
dwmmc2: dwmmc2@ff3ff000 {
compatible = "hisilicon,hi3660-dw-mshc";
reg = <0x0 0xff3ff000 0x0 0x1000>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
num-slots = <1>;
clocks = <&crg_ctrl HI3660_CLK_GATE_SDIO0>,
<&crg_ctrl HI3660_HCLK_GATE_SDIO0>;
clock-names = "ciu", "biu";
resets = <&crg_rst 0x94 20>;
card-detect-delay = <200>;
supports-highspeed;
keep-power-in-suspend;
pinctrl-names = "default";
pinctrl-0 = <&sdio_pmx_func
&sdio_clk_cfg_func
&sdio_cfg_func>;
status = "disabled"; status = "disabled";
}; };
}; };
......
arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
View file @ 010da09e
...@@ -466,6 +466,11 @@ optee { ...@@ -466,6 +466,11 @@ optee {
method = "smc"; method = "smc";
}; };
}; };
sound_card {
compatible = "audio-graph-card";
dais = <&i2s0_port0>;
};
}; };
&uart2 { &uart2 {
...@@ -506,10 +511,33 @@ adv7533: adv7533@39 { ...@@ -506,10 +511,33 @@ adv7533: adv7533@39 {
interrupts = <1 2>; interrupts = <1 2>;
pd-gpio = <&gpio0 4 0>; pd-gpio = <&gpio0 4 0>;
adi,dsi-lanes = <4>; adi,dsi-lanes = <4>;
#sound-dai-cells = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
adv7533_in: endpoint {
remote-endpoint = <&dsi_out0>;
};
};
port@2 {
reg = <2>;
codec_endpoint: endpoint {
remote-endpoint = <&i2s0_cpu_endpoint>;
};
};
};
};
};
port { &i2s0 {
adv7533_in: endpoint {
remote-endpoint = <&dsi_out0>; ports {
i2s0_port0: port@0 {
i2s0_cpu_endpoint: endpoint {
remote-endpoint = <&codec_endpoint>;
dai-format = "i2s";
}; };
}; };
}; };
......
arch/arm64/boot/dts/hisilicon/hi6220.dtsi
View file @ 010da09e
...@@ -332,6 +332,19 @@ uart4: uart@f7114000 { ...@@ -332,6 +332,19 @@ uart4: uart@f7114000 {
status = "disabled"; status = "disabled";
}; };
dma0: dma@f7370000 {
compatible = "hisilicon,k3-dma-1.0";
reg = <0x0 0xf7370000 0x0 0x1000>;
#dma-cells = <1>;
dma-channels = <15>;
dma-requests = <32>;
interrupts = <0 84 4>;
clocks = <&sys_ctrl HI6220_EDMAC_ACLK>;
dma-no-cci;
dma-type = "hi6220_dma";
status = "ok";
};
dual_timer0: timer@f8008000 { dual_timer0: timer@f8008000 {
compatible = "arm,sp804", "arm,primecell"; compatible = "arm,sp804", "arm,primecell";
reg = <0x0 0xf8008000 0x0 0x1000>; reg = <0x0 0xf8008000 0x0 0x1000>;
...@@ -805,6 +818,19 @@ tsensor: tsensor@0,f7030700 { ...@@ -805,6 +818,19 @@ tsensor: tsensor@0,f7030700 {
#thermal-sensor-cells = <1>; #thermal-sensor-cells = <1>;
}; };
i2s0: i2s@f7118000{
compatible = "hisilicon,hi6210-i2s";
reg = <0x0 0xf7118000 0x0 0x8000>; /* i2s unit */
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* 155 "DigACodec_intr"-32 */
clocks = <&sys_ctrl HI6220_DACODEC_PCLK>,
<&sys_ctrl HI6220_BBPPLL0_DIV>;
clock-names = "dacodec", "i2s-base";
dmas = <&dma0 15 &dma0 14>;
dma-names = "rx", "tx";
hisilicon,sysctrl-syscon = <&sys_ctrl>;
#sound-dai-cells = <1>;
};
thermal-zones { thermal-zones {
cls0: cls0 { cls0: cls0 {
......
arch/arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi
View file @ 010da09e
...@@ -24,6 +24,27 @@ pmx0: pinmux@e896c000 { ...@@ -24,6 +24,27 @@ pmx0: pinmux@e896c000 {
&range 0 7 0 &range 0 7 0
&range 8 116 0>; &range 8 116 0>;
pmu_pmx_func: pmu_pmx_func {
pinctrl-single,pins = <
0x008 MUX_M1 /* PMU1_SSI */
0x00c MUX_M1 /* PMU2_SSI */
0x010 MUX_M1 /* PMU_CLKOUT */
0x100 MUX_M1 /* PMU_HKADC_SSI */
>;
};
csi0_pwd_n_pmx_func: csi0_pwd_n_pmx_func {
pinctrl-single,pins = <
0x044 MUX_M0 /* CSI0_PWD_N */
>;
};
csi1_pwd_n_pmx_func: csi1_pwd_n_pmx_func {
pinctrl-single,pins = <
0x04c MUX_M0 /* CSI1_PWD_N */
>;
};
isp0_pmx_func: isp0_pmx_func { isp0_pmx_func: isp0_pmx_func {
pinctrl-single,pins = < pinctrl-single,pins = <
0x058 MUX_M1 /* ISP_CLK0 */ 0x058 MUX_M1 /* ISP_CLK0 */
...@@ -40,6 +61,12 @@ isp1_pmx_func: isp1_pmx_func { ...@@ -40,6 +61,12 @@ isp1_pmx_func: isp1_pmx_func {
>; >;
}; };
pwr_key_pmx_func: pwr_key_pmx_func {
pinctrl-single,pins = <
0x080 MUX_M0 /* GPIO_034 */
>;
};
i2c3_pmx_func: i2c3_pmx_func { i2c3_pmx_func: i2c3_pmx_func {
pinctrl-single,pins = < pinctrl-single,pins = <
0x02c MUX_M1 /* I2C3_SCL */ 0x02c MUX_M1 /* I2C3_SCL */
...@@ -67,21 +94,10 @@ usbhub5734_pmx_func: usbhub5734_pmx_func { ...@@ -67,21 +94,10 @@ usbhub5734_pmx_func: usbhub5734_pmx_func {
>; >;
}; };
spi1_pmx_func: spi1_pmx_func {
pinctrl-single,pins = <
0x034 MUX_M1 /* SPI1_CLK */
0x038 MUX_M1 /* SPI1_DI */
0x03c MUX_M1 /* SPI1_DO */
0x040 MUX_M1 /* SPI1_CS_N */
>;
};
uart0_pmx_func: uart0_pmx_func { uart0_pmx_func: uart0_pmx_func {
pinctrl-single,pins = < pinctrl-single,pins = <
0x0cc MUX_M2 /* UART0_RXD */ 0x0cc MUX_M2 /* UART0_RXD */
0x0d0 MUX_M2 /* UART0_TXD */ 0x0d0 MUX_M2 /* UART0_TXD */
0x0d4 MUX_M2 /* UART0_RXD_M */
0x0d8 MUX_M2 /* UART0_TXD_M */
>; >;
}; };
...@@ -138,6 +154,18 @@ uart6_pmx_func: uart6_pmx_func { ...@@ -138,6 +154,18 @@ uart6_pmx_func: uart6_pmx_func {
0x0d8 MUX_M1 /* UART6_TXD */ 0x0d8 MUX_M1 /* UART6_TXD */
>; >;
}; };
cam0_rst_pmx_func: cam0_rst_pmx_func {
pinctrl-single,pins = <
0x0c8 MUX_M0 /* CAM0_RST */
>;
};
cam1_rst_pmx_func: cam1_rst_pmx_func {
pinctrl-single,pins = <
0x124 MUX_M0 /* CAM1_RST */
>;
};
}; };
/* [IOMG_MMC0_000, IOMG_MMC0_005] */ /* [IOMG_MMC0_000, IOMG_MMC0_005] */
...@@ -174,6 +202,13 @@ pmx2: pinmux@ff3b6000 { ...@@ -174,6 +202,13 @@ pmx2: pinmux@ff3b6000 {
/* pin base, nr pins & gpio function */ /* pin base, nr pins & gpio function */
pinctrl-single,gpio-range = <&range 0 12 0>; pinctrl-single,gpio-range = <&range 0 12 0>;
ufs_pmx_func: ufs_pmx_func {
pinctrl-single,pins = <
0x000 MUX_M1 /* UFS_REF_CLK */
0x004 MUX_M1 /* UFS_RST_N */
>;
};
spi3_pmx_func: spi3_pmx_func { spi3_pmx_func: spi3_pmx_func {
pinctrl-single,pins = < pinctrl-single,pins = <
0x008 MUX_M1 /* SPI3_CLK */ 0x008 MUX_M1 /* SPI3_CLK */
...@@ -248,17 +283,17 @@ i2c1_pmx_func: i2c1_pmx_func { ...@@ -248,17 +283,17 @@ i2c1_pmx_func: i2c1_pmx_func {
>; >;
}; };
i2c2_pmx_func: i2c2_pmx_func { i2c7_pmx_func: i2c7_pmx_func {
pinctrl-single,pins = < pinctrl-single,pins = <
0x024 MUX_M1 /* I2C2_SCL */ 0x024 MUX_M3 /* I2C7_SCL */
0x028 MUX_M1 /* I2C2_SDA */ 0x028 MUX_M3 /* I2C7_SDA */
>; >;
}; };
i2c7_pmx_func: i2c7_pmx_func { pcie_pmx_func: pcie_pmx_func {
pinctrl-single,pins = < pinctrl-single,pins = <
0x024 MUX_M3 /* I2C7_SCL */ 0x084 MUX_M1 /* PCIE_CLKREQ_N */
0x028 MUX_M3 /* I2C7_SDA */ 0x088 MUX_M1 /* PCIE_WAKE_N */
>; >;
}; };
...@@ -271,15 +306,6 @@ spi2_pmx_func: spi2_pmx_func { ...@@ -271,15 +306,6 @@ spi2_pmx_func: spi2_pmx_func {
>; >;
}; };
spi4_pmx_func: spi4_pmx_func {
pinctrl-single,pins = <
0x08c MUX_M4 /* SPI4_CLK */
0x090 MUX_M4 /* SPI4_DI */
0x094 MUX_M4 /* SPI4_DO */
0x098 MUX_M4 /* SPI4_CS0_N */
>;
};
i2s0_pmx_func: i2s0_pmx_func { i2s0_pmx_func: i2s0_pmx_func {
pinctrl-single,pins = < pinctrl-single,pins = <
0x034 MUX_M1 /* I2S0_DI */ 0x034 MUX_M1 /* I2S0_DI */
...@@ -290,17 +316,18 @@ i2s0_pmx_func: i2s0_pmx_func { ...@@ -290,17 +316,18 @@ i2s0_pmx_func: i2s0_pmx_func {
}; };
}; };
pmx5: pinmux@ff3fd800 { pmx5: pinmux@e896c800 {
compatible = "pinconf-single"; compatible = "pinconf-single";
reg = <0x0 0xff3fd800 0x0 0x18>; reg = <0x0 0xe896c800 0x0 0x200>;
#pinctrl-cells = <1>; #pinctrl-cells = <1>;
#address-cells = <1>; pinctrl-single,register-width = <0x20>;
#size-cells = <1>;
pinctrl-single,register-width = <32>;
sdio_clk_cfg_func: sdio_clk_cfg_func { pmu_cfg_func: pmu_cfg_func {
pinctrl-single,pins = < pinctrl-single,pins = <
0x000 0x0 /* SDIO_CLK */ 0x010 0x0 /* PMU1_SSI */
0x014 0x0 /* PMU2_SSI */
0x018 0x0 /* PMU_CLKOUT */
0x10c 0x0 /* PMU_HKADC_SSI */
>; >;
pinctrl-single,bias-pulldown = < pinctrl-single,bias-pulldown = <
PULL_DIS PULL_DIS
...@@ -315,18 +342,35 @@ PULL_DIS ...@@ -315,18 +342,35 @@ PULL_DIS
PULL_UP PULL_UP
>; >;
pinctrl-single,drive-strength = < pinctrl-single,drive-strength = <
DRIVE6_32MA DRIVE7_06MA DRIVE6_MASK
DRIVE6_MASK
>; >;
}; };
sdio_cfg_func: sdio_cfg_func { i2c3_cfg_func: i2c3_cfg_func {
pinctrl-single,pins = < pinctrl-single,pins = <
0x004 0x0 /* SDIO_CMD */ 0x038 0x0 /* I2C3_SCL */
0x008 0x0 /* SDIO_DATA0 */ 0x03c 0x0 /* I2C3_SDA */
0x00c 0x0 /* SDIO_DATA1 */ >;
0x010 0x0 /* SDIO_DATA2 */ pinctrl-single,bias-pulldown = <
0x014 0x0 /* SDIO_DATA3 */ PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_DIS
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE7_02MA DRIVE6_MASK
>;
};
csi0_pwd_n_cfg_func: csi0_pwd_n_cfg_func {
pinctrl-single,pins = <
0x050 0x0 /* CSI0_PWD_N */
>; >;
pinctrl-single,bias-pulldown = < pinctrl-single,bias-pulldown = <
PULL_DIS PULL_DIS
...@@ -335,29 +379,64 @@ PULL_DIS ...@@ -335,29 +379,64 @@ PULL_DIS
PULL_DOWN PULL_DOWN
>; >;
pinctrl-single,bias-pullup = < pinctrl-single,bias-pullup = <
PULL_DIS
PULL_UP
PULL_DIS
PULL_UP PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE7_04MA DRIVE6_MASK
>;
};
csi1_pwd_n_cfg_func: csi1_pwd_n_cfg_func {
pinctrl-single,pins = <
0x058 0x0 /* CSI1_PWD_N */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_DIS
PULL_UP PULL_UP
PULL_DIS PULL_DIS
PULL_UP PULL_UP
>; >;
pinctrl-single,drive-strength = < pinctrl-single,drive-strength = <
DRIVE6_19MA DRIVE7_04MA DRIVE6_MASK
DRIVE6_MASK
>; >;
}; };
};
pmx6: pinmux@ff37e800 { isp0_cfg_func: isp0_cfg_func {
compatible = "pinconf-single"; pinctrl-single,pins = <
reg = <0x0 0xff37e800 0x0 0x18>; 0x064 0x0 /* ISP_CLK0 */
#pinctrl-cells = <1>; 0x070 0x0 /* ISP_SCL0 */
#address-cells = <1>; 0x074 0x0 /* ISP_SDA0 */
#size-cells = <1>; >;
pinctrl-single,register-width = <32>; pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_DIS
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE7_04MA DRIVE6_MASK>;
};
sd_clk_cfg_func: sd_clk_cfg_func { isp1_cfg_func: isp1_cfg_func {
pinctrl-single,pins = < pinctrl-single,pins = <
0x000 0x0 /* SD_CLK */ 0x068 0x0 /* ISP_CLK1 */
0x078 0x0 /* ISP_SCL1 */
0x07c 0x0 /* ISP_SDA1 */
>; >;
pinctrl-single,bias-pulldown = < pinctrl-single,bias-pulldown = <
PULL_DIS PULL_DIS
...@@ -372,18 +451,37 @@ PULL_DIS ...@@ -372,18 +451,37 @@ PULL_DIS
PULL_UP PULL_UP
>; >;
pinctrl-single,drive-strength = < pinctrl-single,drive-strength = <
DRIVE6_32MA DRIVE7_04MA DRIVE6_MASK
DRIVE6_MASK
>; >;
}; };
sd_cfg_func: sd_cfg_func { pwr_key_cfg_func: pwr_key_cfg_func {
pinctrl-single,pins = < pinctrl-single,pins = <
0x004 0x0 /* SD_CMD */ 0x08c 0x0 /* GPIO_034 */
0x008 0x0 /* SD_DATA0 */ >;
0x00c 0x0 /* SD_DATA1 */ pinctrl-single,bias-pulldown = <
0x010 0x0 /* SD_DATA2 */ PULL_DIS
0x014 0x0 /* SD_DATA3 */ PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_DIS
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE7_02MA DRIVE6_MASK
>;
};
uart1_cfg_func: uart1_cfg_func {
pinctrl-single,pins = <
0x0b4 0x0 /* UART1_RXD */
0x0b8 0x0 /* UART1_TXD */
0x0bc 0x0 /* UART1_CTS_N */
0x0c0 0x0 /* UART1_RTS_N */
>; >;
pinctrl-single,bias-pulldown = < pinctrl-single,bias-pulldown = <
PULL_DIS PULL_DIS
...@@ -392,14 +490,568 @@ PULL_DIS ...@@ -392,14 +490,568 @@ PULL_DIS
PULL_DOWN PULL_DOWN
>; >;
pinctrl-single,bias-pullup = < pinctrl-single,bias-pullup = <
PULL_DIS
PULL_UP
PULL_DIS
PULL_UP PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE7_02MA DRIVE6_MASK
>;
};
uart2_cfg_func: uart2_cfg_func {
pinctrl-single,pins = <
0x0c8 0x0 /* UART2_CTS_N */
0x0cc 0x0 /* UART2_RTS_N */
0x0d0 0x0 /* UART2_TXD */
0x0d4 0x0 /* UART2_RXD */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_DIS
PULL_UP PULL_UP
PULL_DIS PULL_DIS
PULL_UP PULL_UP
>; >;
pinctrl-single,drive-strength = < pinctrl-single,drive-strength = <
DRIVE6_19MA DRIVE7_02MA DRIVE6_MASK
DRIVE6_MASK >;
};
uart5_cfg_func: uart5_cfg_func {
pinctrl-single,pins = <
0x0c8 0x0 /* UART5_RXD */
0x0cc 0x0 /* UART5_TXD */
0x0d0 0x0 /* UART5_CTS_N */
0x0d4 0x0 /* UART5_RTS_N */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_DIS
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE7_02MA DRIVE6_MASK
>;
};
cam0_rst_cfg_func: cam0_rst_cfg_func {
pinctrl-single,pins = <
0x0d4 0x0 /* CAM0_RST */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_DIS
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE7_04MA DRIVE6_MASK
>;
};
uart0_cfg_func: uart0_cfg_func {
pinctrl-single,pins = <
0x0d8 0x0 /* UART0_RXD */
0x0dc 0x0 /* UART0_TXD */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_DIS
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE7_02MA DRIVE6_MASK
>;
};
uart6_cfg_func: uart6_cfg_func {
pinctrl-single,pins = <
0x0d8 0x0 /* UART6_CTS_N */
0x0dc 0x0 /* UART6_RTS_N */
0x0e0 0x0 /* UART6_RXD */
0x0e4 0x0 /* UART6_TXD */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_DIS
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE7_02MA DRIVE6_MASK
>;
};
uart3_cfg_func: uart3_cfg_func {
pinctrl-single,pins = <
0x0e8 0x0 /* UART3_CTS_N */
0x0ec 0x0 /* UART3_RTS_N */
0x0f0 0x0 /* UART3_RXD */
0x0f4 0x0 /* UART3_TXD */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_DIS
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE7_02MA DRIVE6_MASK
>;
};
uart4_cfg_func: uart4_cfg_func {
pinctrl-single,pins = <
0x0f8 0x0 /* UART4_CTS_N */
0x0fc 0x0 /* UART4_RTS_N */
0x100 0x0 /* UART4_RXD */
0x104 0x0 /* UART4_TXD */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_DIS
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE7_02MA DRIVE6_MASK
>;
};
cam1_rst_cfg_func: cam1_rst_cfg_func {
pinctrl-single,pins = <
0x130 0x0 /* CAM1_RST */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_DIS
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE7_04MA DRIVE6_MASK
>;
};
};
pmx6: pinmux@ff3b6800 {
compatible = "pinconf-single";
reg = <0x0 0xff3b6800 0x0 0x18>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <0x20>;
ufs_cfg_func: ufs_cfg_func {
pinctrl-single,pins = <
0x000 0x0 /* UFS_REF_CLK */
0x004 0x0 /* UFS_RST_N */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_DIS
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE7_08MA DRIVE6_MASK
>;
};
spi3_cfg_func: spi3_cfg_func {
pinctrl-single,pins = <
0x008 0x0 /* SPI3_CLK */
0x0 /* SPI3_DI */
0x010 0x0 /* SPI3_DO */
0x014 0x0 /* SPI3_CS0_N */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_DIS
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE7_02MA DRIVE6_MASK
>;
};
};
pmx7: pinmux@ff3fd800 {
compatible = "pinconf-single";
reg = <0x0 0xff3fd800 0x0 0x18>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <0x20>;
sdio_clk_cfg_func: sdio_clk_cfg_func {
pinctrl-single,pins = <
0x000 0x0 /* SDIO_CLK */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_DIS
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE6_32MA DRIVE6_MASK
>;
};
sdio_cfg_func: sdio_cfg_func {
pinctrl-single,pins = <
0x004 0x0 /* SDIO_CMD */
0x008 0x0 /* SDIO_DATA0 */
0x00c 0x0 /* SDIO_DATA1 */
0x010 0x0 /* SDIO_DATA2 */
0x014 0x0 /* SDIO_DATA3 */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_UP
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE6_19MA DRIVE6_MASK
>;
};
};
pmx8: pinmux@ff37e800 {
compatible = "pinconf-single";
reg = <0x0 0xff37e800 0x0 0x18>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <0x20>;
sd_clk_cfg_func: sd_clk_cfg_func {
pinctrl-single,pins = <
0x000 0x0 /* SD_CLK */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_DIS
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE6_32MA
DRIVE6_MASK
>;
};
sd_cfg_func: sd_cfg_func {
pinctrl-single,pins = <
0x004 0x0 /* SD_CMD */
0x008 0x0 /* SD_DATA0 */
0x00c 0x0 /* SD_DATA1 */
0x010 0x0 /* SD_DATA2 */
0x014 0x0 /* SD_DATA3 */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_UP
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE6_19MA
DRIVE6_MASK
>;
};
};
pmx9: pinmux@fff11800 {
compatible = "pinconf-single";
reg = <0x0 0xfff11800 0x0 0xbc>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <0x20>;
i2c0_cfg_func: i2c0_cfg_func {
pinctrl-single,pins = <
0x01c 0x0 /* I2C0_SCL */
0x020 0x0 /* I2C0_SDA */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_UP
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE7_02MA DRIVE6_MASK
>;
};
i2c1_cfg_func: i2c1_cfg_func {
pinctrl-single,pins = <
0x024 0x0 /* I2C1_SCL */
0x028 0x0 /* I2C1_SDA */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_UP
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE7_02MA DRIVE6_MASK
>;
};
i2c7_cfg_func: i2c7_cfg_func {
pinctrl-single,pins = <
0x02c 0x0 /* I2C7_SCL */
0x030 0x0 /* I2C7_SDA */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_UP
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE7_02MA DRIVE6_MASK
>;
};
slimbus_cfg_func: slimbus_cfg_func {
pinctrl-single,pins = <
0x034 0x0 /* SLIMBUS_CLK */
0x038 0x0 /* SLIMBUS_DATA */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_UP
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE7_02MA DRIVE6_MASK
>;
};
i2s0_cfg_func: i2s0_cfg_func {
pinctrl-single,pins = <
0x040 0x0 /* I2S0_DI */
0x044 0x0 /* I2S0_DO */
0x048 0x0 /* I2S0_XCLK */
0x04c 0x0 /* I2S0_XFS */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_UP
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE7_02MA DRIVE6_MASK
>;
};
i2s2_cfg_func: i2s2_cfg_func {
pinctrl-single,pins = <
0x050 0x0 /* I2S2_DI */
0x054 0x0 /* I2S2_DO */
0x058 0x0 /* I2S2_XCLK */
0x05c 0x0 /* I2S2_XFS */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_UP
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE7_02MA DRIVE6_MASK
>;
};
pcie_cfg_func: pcie_cfg_func {
pinctrl-single,pins = <
0x094 0x0 /* PCIE_CLKREQ_N */
0x098 0x0 /* PCIE_WAKE_N */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_UP
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE7_02MA DRIVE6_MASK
>;
};
spi2_cfg_func: spi2_cfg_func {
pinctrl-single,pins = <
0x09c 0x0 /* SPI2_CLK */
0x0a0 0x0 /* SPI2_DI */
0x0a4 0x0 /* SPI2_DO */
0x0a8 0x0 /* SPI2_CS0_N */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_UP
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE7_02MA DRIVE6_MASK
>;
};
usb_cfg_func: usb_cfg_func {
pinctrl-single,pins = <
0x0ac 0x0 /* GPIO_219 */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_UP
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE7_02MA DRIVE6_MASK
>; >;
}; };
}; };
......
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