Commit 035f7ff2 authored by Emmanuel Grumbach's avatar Emmanuel Grumbach Committed by Wey-Yi Guy

iwlwifi: transport holds its pointer to the config

Instead of using the shared area that we be killed.
Remove the pointer to config from shared since it is not
used any more.
Signed-off-by: default avatarEmmanuel Grumbach <emmanuel.grumbach@intel.com>
Signed-off-by: default avatarWey-Yi Guy <wey-yi.w.guy@intel.com>
parent 68f360dc
...@@ -890,8 +890,6 @@ struct iwl_drv *iwl_drv_start(struct iwl_shared *shrd, ...@@ -890,8 +890,6 @@ struct iwl_drv *iwl_drv_start(struct iwl_shared *shrd,
struct iwl_drv *drv; struct iwl_drv *drv;
int ret; int ret;
shrd->cfg = cfg;
drv = kzalloc(sizeof(*drv), GFP_KERNEL); drv = kzalloc(sizeof(*drv), GFP_KERNEL);
if (!drv) { if (!drv) {
dev_printk(KERN_ERR, trans->dev, "Couldn't allocate iwl_drv"); dev_printk(KERN_ERR, trans->dev, "Couldn't allocate iwl_drv");
......
...@@ -433,7 +433,7 @@ static int iwl_init_otp_access(struct iwl_trans *trans) ...@@ -433,7 +433,7 @@ static int iwl_init_otp_access(struct iwl_trans *trans)
* CSR auto clock gate disable bit - * CSR auto clock gate disable bit -
* this is only applicable for HW with OTP shadow RAM * this is only applicable for HW with OTP shadow RAM
*/ */
if (cfg(trans)->base_params->shadow_ram_support) if (trans->cfg->base_params->shadow_ram_support)
iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
CSR_RESET_LINK_PWR_MGMT_DISABLED); CSR_RESET_LINK_PWR_MGMT_DISABLED);
} }
...@@ -554,7 +554,7 @@ static int iwl_find_otp_image(struct iwl_trans *trans, ...@@ -554,7 +554,7 @@ static int iwl_find_otp_image(struct iwl_trans *trans,
} }
/* more in the link list, continue */ /* more in the link list, continue */
usedblocks++; usedblocks++;
} while (usedblocks <= cfg(trans)->base_params->max_ll_items); } while (usedblocks <= trans->cfg->base_params->max_ll_items);
/* OTP has no valid blocks */ /* OTP has no valid blocks */
IWL_DEBUG_EEPROM(trans, "OTP has no valid blocks\n"); IWL_DEBUG_EEPROM(trans, "OTP has no valid blocks\n");
......
...@@ -281,7 +281,7 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) ...@@ -281,7 +281,7 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
goto out_free_bus; goto out_free_bus;
} }
iwl_trans = iwl_trans_pcie_alloc(shrd, pdev, ent); iwl_trans = iwl_trans_pcie_alloc(shrd, pdev, ent, cfg);
if (iwl_trans == NULL) { if (iwl_trans == NULL) {
err = -ENOMEM; err = -ENOMEM;
goto out_free_bus; goto out_free_bus;
......
...@@ -150,16 +150,13 @@ struct iwl_mod_params { ...@@ -150,16 +150,13 @@ struct iwl_mod_params {
/** /**
* struct iwl_shared - shared fields for all the layers of the driver * struct iwl_shared - shared fields for all the layers of the driver
* *
* @cfg: see struct iwl_cfg
* @trans: pointer to the transport layer data * @trans: pointer to the transport layer data
*/ */
struct iwl_shared { struct iwl_shared {
const struct iwl_cfg *cfg;
struct iwl_trans *trans; struct iwl_trans *trans;
}; };
/*Whatever _m is (iwl_trans, iwl_priv, these macros will work */ /*Whatever _m is (iwl_trans, iwl_priv, these macros will work */
#define cfg(_m) ((_m)->shrd->cfg)
#define trans(_m) ((_m)->shrd->trans) #define trans(_m) ((_m)->shrd->trans)
static inline bool iwl_have_debug_level(u32 level) static inline bool iwl_have_debug_level(u32 level)
......
...@@ -140,7 +140,7 @@ void iwl_rx_queue_update_write_ptr(struct iwl_trans *trans, ...@@ -140,7 +140,7 @@ void iwl_rx_queue_update_write_ptr(struct iwl_trans *trans,
if (q->need_update == 0) if (q->need_update == 0)
goto exit_unlock; goto exit_unlock;
if (cfg(trans)->base_params->shadow_reg_enable) { if (trans->cfg->base_params->shadow_reg_enable) {
/* shadow register enabled */ /* shadow register enabled */
/* Device expects a multiple of 8 */ /* Device expects a multiple of 8 */
q->write_actual = (q->write & ~0x7); q->write_actual = (q->write & ~0x7);
...@@ -543,7 +543,7 @@ static void iwl_rx_handle(struct iwl_trans *trans) ...@@ -543,7 +543,7 @@ static void iwl_rx_handle(struct iwl_trans *trans)
static void iwl_irq_handle_error(struct iwl_trans *trans) static void iwl_irq_handle_error(struct iwl_trans *trans)
{ {
/* W/A for WiFi/WiMAX coex and WiMAX own the RF */ /* W/A for WiFi/WiMAX coex and WiMAX own the RF */
if (cfg(trans)->internal_wimax_coex && if (trans->cfg->internal_wimax_coex &&
(!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) & (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) &
APMS_CLK_VAL_MRB_FUNC_MODE) || APMS_CLK_VAL_MRB_FUNC_MODE) ||
(iwl_read_prph(trans, APMG_PS_CTRL_REG) & (iwl_read_prph(trans, APMG_PS_CTRL_REG) &
...@@ -680,7 +680,7 @@ void iwl_irq_tasklet(struct iwl_trans *trans) ...@@ -680,7 +680,7 @@ void iwl_irq_tasklet(struct iwl_trans *trans)
if (inta & CSR_INT_BIT_WAKEUP) { if (inta & CSR_INT_BIT_WAKEUP) {
IWL_DEBUG_ISR(trans, "Wakeup interrupt\n"); IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
iwl_rx_queue_update_write_ptr(trans, &trans_pcie->rxq); iwl_rx_queue_update_write_ptr(trans, &trans_pcie->rxq);
for (i = 0; i < cfg(trans)->base_params->num_of_queues; i++) for (i = 0; i < trans->cfg->base_params->num_of_queues; i++)
iwl_txq_update_write_ptr(trans, iwl_txq_update_write_ptr(trans,
&trans_pcie->txq[i]); &trans_pcie->txq[i]);
......
...@@ -99,7 +99,7 @@ void iwl_txq_update_write_ptr(struct iwl_trans *trans, struct iwl_tx_queue *txq) ...@@ -99,7 +99,7 @@ void iwl_txq_update_write_ptr(struct iwl_trans *trans, struct iwl_tx_queue *txq)
if (txq->need_update == 0) if (txq->need_update == 0)
return; return;
if (cfg(trans)->base_params->shadow_reg_enable) { if (trans->cfg->base_params->shadow_reg_enable) {
/* shadow register enabled */ /* shadow register enabled */
iwl_write32(trans, HBUS_TARG_WRPTR, iwl_write32(trans, HBUS_TARG_WRPTR,
txq->q.write_ptr | (txq_id << 8)); txq->q.write_ptr | (txq_id << 8));
......
...@@ -79,7 +79,7 @@ ...@@ -79,7 +79,7 @@
#define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo)))) #define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo))))
#define SCD_QUEUECHAIN_SEL_ALL(trans, trans_pcie) \ #define SCD_QUEUECHAIN_SEL_ALL(trans, trans_pcie) \
(((1<<cfg(trans)->base_params->num_of_queues) - 1) &\ (((1<<trans->cfg->base_params->num_of_queues) - 1) &\
(~(1<<(trans_pcie)->cmd_queue))) (~(1<<(trans_pcie)->cmd_queue)))
static int iwl_trans_rx_alloc(struct iwl_trans *trans) static int iwl_trans_rx_alloc(struct iwl_trans *trans)
...@@ -522,7 +522,7 @@ static void iwl_trans_pcie_tx_free(struct iwl_trans *trans) ...@@ -522,7 +522,7 @@ static void iwl_trans_pcie_tx_free(struct iwl_trans *trans)
/* Tx queues */ /* Tx queues */
if (trans_pcie->txq) { if (trans_pcie->txq) {
for (txq_id = 0; for (txq_id = 0;
txq_id < cfg(trans)->base_params->num_of_queues; txq_id++) txq_id < trans->cfg->base_params->num_of_queues; txq_id++)
iwl_tx_queue_free(trans, txq_id); iwl_tx_queue_free(trans, txq_id);
} }
...@@ -547,7 +547,7 @@ static int iwl_trans_tx_alloc(struct iwl_trans *trans) ...@@ -547,7 +547,7 @@ static int iwl_trans_tx_alloc(struct iwl_trans *trans)
int txq_id, slots_num; int txq_id, slots_num;
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
u16 scd_bc_tbls_size = cfg(trans)->base_params->num_of_queues * u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues *
sizeof(struct iwlagn_scd_bc_tbl); sizeof(struct iwlagn_scd_bc_tbl);
/*It is not allowed to alloc twice, so warn when this happens. /*It is not allowed to alloc twice, so warn when this happens.
...@@ -571,7 +571,7 @@ static int iwl_trans_tx_alloc(struct iwl_trans *trans) ...@@ -571,7 +571,7 @@ static int iwl_trans_tx_alloc(struct iwl_trans *trans)
goto error; goto error;
} }
trans_pcie->txq = kcalloc(cfg(trans)->base_params->num_of_queues, trans_pcie->txq = kcalloc(trans->cfg->base_params->num_of_queues,
sizeof(struct iwl_tx_queue), GFP_KERNEL); sizeof(struct iwl_tx_queue), GFP_KERNEL);
if (!trans_pcie->txq) { if (!trans_pcie->txq) {
IWL_ERR(trans, "Not enough memory for txq\n"); IWL_ERR(trans, "Not enough memory for txq\n");
...@@ -580,7 +580,7 @@ static int iwl_trans_tx_alloc(struct iwl_trans *trans) ...@@ -580,7 +580,7 @@ static int iwl_trans_tx_alloc(struct iwl_trans *trans)
} }
/* Alloc and init all Tx queues, including the command queue (#4/#9) */ /* Alloc and init all Tx queues, including the command queue (#4/#9) */
for (txq_id = 0; txq_id < cfg(trans)->base_params->num_of_queues; for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
txq_id++) { txq_id++) {
slots_num = (txq_id == trans_pcie->cmd_queue) ? slots_num = (txq_id == trans_pcie->cmd_queue) ?
TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
...@@ -626,7 +626,7 @@ static int iwl_tx_init(struct iwl_trans *trans) ...@@ -626,7 +626,7 @@ static int iwl_tx_init(struct iwl_trans *trans)
spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
/* Alloc and init all Tx queues, including the command queue (#4/#9) */ /* Alloc and init all Tx queues, including the command queue (#4/#9) */
for (txq_id = 0; txq_id < cfg(trans)->base_params->num_of_queues; for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
txq_id++) { txq_id++) {
slots_num = (txq_id == trans_pcie->cmd_queue) ? slots_num = (txq_id == trans_pcie->cmd_queue) ?
TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
...@@ -749,9 +749,9 @@ static int iwl_apm_init(struct iwl_trans *trans) ...@@ -749,9 +749,9 @@ static int iwl_apm_init(struct iwl_trans *trans)
iwl_apm_config(trans); iwl_apm_config(trans);
/* Configure analog phase-lock-loop before activating to D0A */ /* Configure analog phase-lock-loop before activating to D0A */
if (cfg(trans)->base_params->pll_cfg_val) if (trans->cfg->base_params->pll_cfg_val)
iwl_set_bit(trans, CSR_ANA_PLL_CFG, iwl_set_bit(trans, CSR_ANA_PLL_CFG,
cfg(trans)->base_params->pll_cfg_val); trans->cfg->base_params->pll_cfg_val);
/* /*
* Set "initialization complete" bit to move adapter from * Set "initialization complete" bit to move adapter from
...@@ -861,7 +861,7 @@ static int iwl_nic_init(struct iwl_trans *trans) ...@@ -861,7 +861,7 @@ static int iwl_nic_init(struct iwl_trans *trans)
if (iwl_tx_init(trans)) if (iwl_tx_init(trans))
return -ENOMEM; return -ENOMEM;
if (cfg(trans)->base_params->shadow_reg_enable) { if (trans->cfg->base_params->shadow_reg_enable) {
/* enable shadow regs in HW */ /* enable shadow regs in HW */
iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL,
0x800FFFFF); 0x800FFFFF);
...@@ -1080,7 +1080,7 @@ static void iwl_tx_start(struct iwl_trans *trans) ...@@ -1080,7 +1080,7 @@ static void iwl_tx_start(struct iwl_trans *trans)
iwl_write_targ_mem(trans, a, 0); iwl_write_targ_mem(trans, a, 0);
for (; a < trans_pcie->scd_base_addr + for (; a < trans_pcie->scd_base_addr +
SCD_TRANS_TBL_OFFSET_QUEUE( SCD_TRANS_TBL_OFFSET_QUEUE(
cfg(trans)->base_params->num_of_queues); trans->cfg->base_params->num_of_queues);
a += 4) a += 4)
iwl_write_targ_mem(trans, a, 0); iwl_write_targ_mem(trans, a, 0);
...@@ -1103,7 +1103,7 @@ static void iwl_tx_start(struct iwl_trans *trans) ...@@ -1103,7 +1103,7 @@ static void iwl_tx_start(struct iwl_trans *trans)
iwl_write_prph(trans, SCD_AGGR_SEL, 0); iwl_write_prph(trans, SCD_AGGR_SEL, 0);
/* initiate the queues */ /* initiate the queues */
for (i = 0; i < cfg(trans)->base_params->num_of_queues; i++) { for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
iwl_write_prph(trans, SCD_QUEUE_RDPTR(i), 0); iwl_write_prph(trans, SCD_QUEUE_RDPTR(i), 0);
iwl_write_direct32(trans, HBUS_TARG_WRPTR, 0 | (i << 8)); iwl_write_direct32(trans, HBUS_TARG_WRPTR, 0 | (i << 8));
iwl_write_targ_mem(trans, trans_pcie->scd_base_addr + iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
...@@ -1120,7 +1120,7 @@ static void iwl_tx_start(struct iwl_trans *trans) ...@@ -1120,7 +1120,7 @@ static void iwl_tx_start(struct iwl_trans *trans)
} }
iwl_write_prph(trans, SCD_INTERRUPT_MASK, iwl_write_prph(trans, SCD_INTERRUPT_MASK,
IWL_MASK(0, cfg(trans)->base_params->num_of_queues)); IWL_MASK(0, trans->cfg->base_params->num_of_queues));
/* Activate all Tx DMA/FIFO channels */ /* Activate all Tx DMA/FIFO channels */
iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7)); iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7));
...@@ -1188,7 +1188,7 @@ static int iwl_trans_tx_stop(struct iwl_trans *trans) ...@@ -1188,7 +1188,7 @@ static int iwl_trans_tx_stop(struct iwl_trans *trans)
} }
/* Unmap DMA from host system and free skb's */ /* Unmap DMA from host system and free skb's */
for (txq_id = 0; txq_id < cfg(trans)->base_params->num_of_queues; for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
txq_id++) txq_id++)
iwl_tx_queue_unmap(trans, txq_id); iwl_tx_queue_unmap(trans, txq_id);
...@@ -1617,7 +1617,7 @@ static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans *trans) ...@@ -1617,7 +1617,7 @@ static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans *trans)
int ret = 0; int ret = 0;
/* waiting for all the tx frames complete might take a while */ /* waiting for all the tx frames complete might take a while */
for (cnt = 0; cnt < cfg(trans)->base_params->num_of_queues; cnt++) { for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
if (cnt == trans_pcie->cmd_queue) if (cnt == trans_pcie->cmd_queue)
continue; continue;
txq = &trans_pcie->txq[cnt]; txq = &trans_pcie->txq[cnt];
...@@ -1829,7 +1829,7 @@ static ssize_t iwl_dbgfs_tx_queue_read(struct file *file, ...@@ -1829,7 +1829,7 @@ static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
int ret; int ret;
size_t bufsz; size_t bufsz;
bufsz = sizeof(char) * 64 * cfg(trans)->base_params->num_of_queues; bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues;
if (!trans_pcie->txq) { if (!trans_pcie->txq) {
IWL_ERR(trans, "txq not ready\n"); IWL_ERR(trans, "txq not ready\n");
...@@ -1839,7 +1839,7 @@ static ssize_t iwl_dbgfs_tx_queue_read(struct file *file, ...@@ -1839,7 +1839,7 @@ static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
if (!buf) if (!buf)
return -ENOMEM; return -ENOMEM;
for (cnt = 0; cnt < cfg(trans)->base_params->num_of_queues; cnt++) { for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
txq = &trans_pcie->txq[cnt]; txq = &trans_pcie->txq[cnt];
q = &txq->q; q = &txq->q;
pos += scnprintf(buf + pos, bufsz - pos, pos += scnprintf(buf + pos, bufsz - pos,
...@@ -2085,7 +2085,8 @@ const struct iwl_trans_ops trans_ops_pcie = { ...@@ -2085,7 +2085,8 @@ const struct iwl_trans_ops trans_ops_pcie = {
struct iwl_trans *iwl_trans_pcie_alloc(struct iwl_shared *shrd, struct iwl_trans *iwl_trans_pcie_alloc(struct iwl_shared *shrd,
struct pci_dev *pdev, struct pci_dev *pdev,
const struct pci_device_id *ent) const struct pci_device_id *ent,
const struct iwl_cfg *cfg)
{ {
struct iwl_trans_pcie *trans_pcie; struct iwl_trans_pcie *trans_pcie;
struct iwl_trans *trans; struct iwl_trans *trans;
...@@ -2102,6 +2103,7 @@ struct iwl_trans *iwl_trans_pcie_alloc(struct iwl_shared *shrd, ...@@ -2102,6 +2103,7 @@ struct iwl_trans *iwl_trans_pcie_alloc(struct iwl_shared *shrd,
trans->ops = &trans_ops_pcie; trans->ops = &trans_ops_pcie;
trans->shrd = shrd; trans->shrd = shrd;
trans->cfg = cfg;
trans_pcie->trans = trans; trans_pcie->trans = trans;
spin_lock_init(&trans_pcie->irq_lock); spin_lock_init(&trans_pcie->irq_lock);
init_waitqueue_head(&trans_pcie->ucode_write_waitq); init_waitqueue_head(&trans_pcie->ucode_write_waitq);
......
...@@ -429,6 +429,7 @@ enum iwl_trans_state { ...@@ -429,6 +429,7 @@ enum iwl_trans_state {
* @ops - pointer to iwl_trans_ops * @ops - pointer to iwl_trans_ops
* @op_mode - pointer to the op_mode * @op_mode - pointer to the op_mode
* @shrd - pointer to iwl_shared which holds shared data from the upper layer * @shrd - pointer to iwl_shared which holds shared data from the upper layer
* @cfg - pointer to the configuration
* @reg_lock - protect hw register access * @reg_lock - protect hw register access
* @dev - pointer to struct device * that represents the device * @dev - pointer to struct device * that represents the device
* @hw_id: a u32 with the ID of the device / subdevice. * @hw_id: a u32 with the ID of the device / subdevice.
...@@ -441,6 +442,7 @@ struct iwl_trans { ...@@ -441,6 +442,7 @@ struct iwl_trans {
const struct iwl_trans_ops *ops; const struct iwl_trans_ops *ops;
struct iwl_op_mode *op_mode; struct iwl_op_mode *op_mode;
struct iwl_shared *shrd; struct iwl_shared *shrd;
const struct iwl_cfg *cfg;
enum iwl_trans_state state; enum iwl_trans_state state;
spinlock_t reg_lock; spinlock_t reg_lock;
...@@ -625,12 +627,14 @@ struct pci_device_id; ...@@ -625,12 +627,14 @@ struct pci_device_id;
extern const struct iwl_trans_ops trans_ops_pcie; extern const struct iwl_trans_ops trans_ops_pcie;
struct iwl_trans *iwl_trans_pcie_alloc(struct iwl_shared *shrd, struct iwl_trans *iwl_trans_pcie_alloc(struct iwl_shared *shrd,
struct pci_dev *pdev, struct pci_dev *pdev,
const struct pci_device_id *ent); const struct pci_device_id *ent,
const struct iwl_cfg *cfg);
int __must_check iwl_pci_register_driver(void); int __must_check iwl_pci_register_driver(void);
void iwl_pci_unregister_driver(void); void iwl_pci_unregister_driver(void);
extern const struct iwl_trans_ops trans_ops_idi; extern const struct iwl_trans_ops trans_ops_idi;
struct iwl_trans *iwl_trans_idi_alloc(struct iwl_shared *shrd, struct iwl_trans *iwl_trans_idi_alloc(struct iwl_shared *shrd,
void *pdev_void, void *pdev_void,
const void *ent_void); const void *ent_void,
const struct iwl_cfg *cfg);
#endif /* __iwl_trans_h__ */ #endif /* __iwl_trans_h__ */
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