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Commit 041e6a1f authored by Sam Ravnborg's avatar Sam Ravnborg
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kbuild: Update Documentation/kbuild/makefiles.txt 

makefiles.txt brought up-to-date with the changes that has occured
in kbuild within the last couple of months.
Restructured to present relevant info earlier, and rewritten the
architecture specific section to a certain degree.

One change in style is that makefiles used throughout the kernel tree is called
"kbuild makefiles", because they follow the kbuild syntax.
Old notation was "subdirectory makefiles".

There is added a TODO section, if anyone feel tempted to add a bit more text.
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Documentation/kbuild/makefiles.txt
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Linux Kernel Makefiles Linux Kernel Makefiles
2000-September-14
Michael Elizabeth Chastain, <mec@shout.net>
=== Table of Contents
This document describes the Linux kernel Makefiles. This document describes the Linux kernel Makefiles.
1 Overview === Table of Contents
2 Who does what
3 Makefile language
4 Variables passed down from the top
5 The structure of an arch Makefile
5.1 Architecture-specific variables
5.2 Vmlinux build variables
5.3 Post-vmlinux goals
5.4 Mandatory arch-specific goals
6 The structure of a subdirectory Makefile
6.1 Comments
6.2 Goal definitions
6.3 Adapter section
6.4 Rules.make section
6.5 Special rules
7 Rules.make variables
7.1 Subdirectories
7.2 Object file goals
7.3 Library file goals
7.4 Loadable module goals
7.5 Multi-part modules
7.6 Compilation flags
7.7 Miscellaneous variables
8 New-style variables
8.1 New variables
8.2 Converting to old-style
9 Credits
=== 1 Overview
=== 2 Who does what
=== 3 The kbuild Makefiles
--- 3.1 Goal definitions
--- 3.2 Built-in object goals - obj-y
--- 3.3 Loadable module goals - obj-m
--- 3.4 Objects which export symbols - export-objs
--- 3.5 Library file goals - L_TARGET
--- 3.6 Descending down in directories
--- 3.7 Compilation flags
--- 3.8 Command line dependency
--- 3.9 Dependency tracking
--- 3.10 Special Rules
=== 4 Host Program support
--- 4.1 Simple Host Program
--- 4.2 Composite Host Programs
--- 4.3 Defining shared libraries
--- 4.4 Using C++ for host programs
--- 4.5 Controlling compiler options for host programs
--- 4.6 When host programs are actually built
=== 5 Kbuild clean infrastructure
=== 6 Architecture Makefiles
--- 6.1 Set variables to tweak the build to the architecture
--- 6.2 Add prerequisites to prepare:
--- 6.3 List directories to visit when descending
--- 6.4 Architecture specific boot images
--- 6.5 Building non-kbuild targets
--- 6.6 Commands useful for building a boot image
--- 6.7 Custom kbuild commands
=== 7 Kbuild Variables
=== 8 Makefile language
=== 9 Credits
=== 10 TODO
=== 1 Overview === 1 Overview
The Makefiles have five parts: The Makefiles have five parts:
Makefile: the top Makefile. Makefile the top Makefile.
.config: the kernel configuration file. .config the kernel configuration file.
arch/*/Makefile: the arch Makefiles. arch/$(ARCH)/Makefile the arch Makefile.
Subdirectory Makefiles: there are about 300 of these. scripts/Makefile.* common rules etc. for all kbuild Makefiles.
Rules.make: the common rules for all subdirectory Makefiles. kbuild Makefiles there are about 500 of these.
The top Makefile reads the .config file, which comes from the The top Makefile reads the .config file, which comes from the kernel
kernel configuration process. configuration process.
The top Makefile is responsible for building two major products: vmlinux The top Makefile is responsible for building two major products: vmlinux
(the resident kernel image) and modules (any module files). It builds (the resident kernel image) and modules (any module files).
these goals by recursively descending into the subdirectories of the It builds these goals by recursively descending into the subdirectories of
kernel source tree. The list of subdirectories which are visited depends the kernel source tree.
upon the kernel configuration. The list of subdirectories which are visited depends upon the kernel
configuration. The top Makefile textually includes an arch Makefile
The top Makefile textually includes an arch Makefile with the name with the name arch/$(ARCH)/Makefile. The arch Makefile supplies
arch/$(ARCH)/Makefile. The arch Makefile supplies architecture-specific architecture-specific information to the top Makefile.
information to the top Makefile.
Each subdirectory has a Makefile which carries out the commands passed Each subdirectory has a kbuild Makefile which carries out the commands
down from above. The subdirectory Makefile uses information from the passed down from above. The kbuild Makefile uses information from the
.config file to construct various file lists, and then it textually .config file to construct various file lists used by kbuild to build
includes the common rules in Rules.make. any built-in or modular targets.
Rules.make defines rules which are common to all the subdirectory
Makefiles. It has a public interface in the form of certain variable
lists. It then declares rules based on those lists.
scripts/Makefile.* contains all the definitions/rules etc. that
are used to build the kernel based on the kbuild makefiles.
=== 2 Who does what === 2 Who does what
...@@ -76,19 +78,19 @@ lists. It then declares rules based on those lists. ...@@ -76,19 +78,19 @@ lists. It then declares rules based on those lists.
People have four different relationships with the kernel Makefiles. People have four different relationships with the kernel Makefiles.
*Users* are people who build kernels. These people type commands such as *Users* are people who build kernels. These people type commands such as
"make menuconfig" or "make bzImage". They usually do not read or edit "make menuconfig" or "make". They usually do not read or edit
any kernel Makefiles (or any other source files). any kernel Makefiles (or any other source files).
*Normal developers* are people who work on features such as device *Normal developers* are people who work on features such as device
drivers, file systems, and network protocols. These people need to drivers, file systems, and network protocols. These people need to
maintain the subdirectory Makefiles for the subsystem that they are maintain the kbuild Makefiles for the subsystem that they are
working on. In order to do this effectively, they need some overall working on. In order to do this effectively, they need some overall
knowledge about the kernel Makefiles, plus detailed knowledge about the knowledge about the kernel Makefiles, plus detailed knowledge about the
public interface for Rules.make. public interface for kbuild.
*Arch developers* are people who work on an entire architecture, such *Arch developers* are people who work on an entire architecture, such
as sparc or ia64. Arch developers need to know about the arch Makefiles as sparc or ia64. Arch developers need to know about the arch Makefile
as well as subdirectory Makefiles. as well as kbuild Makefiles.
*Kbuild developers* are people who work on the kernel build system itself. *Kbuild developers* are people who work on the kernel build system itself.
These people need to know about all aspects of the kernel Makefiles. These people need to know about all aspects of the kernel Makefiles.
...@@ -96,883 +98,895 @@ These people need to know about all aspects of the kernel Makefiles. ...@@ -96,883 +98,895 @@ These people need to know about all aspects of the kernel Makefiles.
This document is aimed towards normal developers and arch developers. This document is aimed towards normal developers and arch developers.
=== 3 The kbuild Makefiles
=== 3 Makefile language Most Makefiles within the kernel are kbuild Makefiles that use the
kbuild infrastructure. This chapter introduce the syntax used in the
The kernel Makefiles are designed to run with GNU Make. The Makefiles kbuild makefiles.
use only the documented features of GNU Make, but they do use many
GNU extensions.
GNU Make supports elementary list-processing functions. The kernel
Makefiles use a novel style of list building and manipulation with few
"if" statements.
GNU Make has two assignment operators, ":=" and "=". ":=" performs
immediate evaluation of the right-hand side and stores an actual string
into the left-hand side. "=" is like a formula definition; it stores the
right-hand side in an unevaluated form and then evaluates this form each
time the left-hand side is used.
There are some cases where "=" is appropriate. Usually, though, ":="
is the right choice.
All of the examples in this document were drawn from actual kernel
sources. The examples have been reformatted (white space changed, lines
split), but are otherwise exactly the same.
=== 4 Variables passed down from the top
The top Makefile exports the following variables:
VERSION, PATCHLEVEL, SUBLEVEL, EXTRAVERSION
These variables define the current kernel version. A few arch
Makefiles actually use these values directly; they should use
$(KERNELRELEASE) instead.
$(VERSION), $(PATCHLEVEL), and $(SUBLEVEL) define the basic
three-part version number, such as "2", "4", and "0". These three
values are always numeric.
$(EXTRAVERSION) defines an even tinier sublevel for pre-patches
or additional patches. It is usually some non-numeric string
such as "-pre4", and is often blank.
KERNELRELEASE
$(KERNELRELEASE) is a single string such as "2.4.0-pre4", suitable
for constructing installation directory names or showing in
version strings. Some arch Makefiles use it for this purpose.
ARCH Section 3.1 "Goal definitions" is a quick intro, further chapters provide
more details, with real examples.
This variable defines the target architecture, such as "i386", --- 3.1 Goal definitions
"arm", or "sparc". Many subdirectory Makefiles test $(ARCH)
to determine which files to compile.
By default, the top Makefile sets $(ARCH) to be the same as the Goal definitions are the main part (heart) of the kbuild Makefile.
host system system architecture. For a cross build, a user may These lines define the files to be built, any special compilation
override the value of $(ARCH) on the command line: options, and any subdirectories to be entered recursively.
make ARCH=m68k ...
TOPDIR, HPATH
$(TOPDIR) is the path to the top of the kernel source tree. The most simple kbuild makefile contains one line:
Subdirectory Makefiles need this so that they can include
$(TOPDIR)/Rules.make.
$(HPATH) is equal to $(TOPDIR)/include. A few arch Makefiles Example:
need to use this to do special things using include files. obj-y += foo.o
SUBDIRS
$(SUBDIRS) is a list of directories which the top Makefile
enters in order to build either vmlinux or modules. The actual
directories in $(SUBDIRS) depend on the kernel configuration.
The top Makefile defines this variable, and the arch Makefile
extends it.
HEAD, CORE_FILES, NETWORKS, DRIVERS, LIBS
LINKFLAGS
$(HEAD), $(CORE_FILES), $(NETWORKS), $(DRIVERS), and $(LIBS)
specify lists of object files and libraries to be linked into
vmlinux.
The files in $(HEAD) are linked first in vmlinux.
$(LINKFLAGS) specifies the flags to build vmlinux. This tell kbuild that there is one object in that directory named
foo.o. foo.o will be build from foo.c or foo.S.
The top Makefile and the arch Makefile jointly define these If foo.o shall be built as a module, the variable obj-m is used.
variables. The top Makefile defines $(CORE_FILES), $(NETWORKS), Therefore the following pattern is often used:
$(DRIVERS), and $(LIBS). The arch Makefile defines $(HEAD)
and $(LINKFLAGS), and extends $(CORE_FILES) and $(LIBS).
Note: there are more variables here than necessary. $(NETWORKS), Example:
$(DRIVERS), and even $(LIBS) could be subsumed into $(CORE_FILES). obj-$(CONFIG_FOO) += foo.o
CPP, CC, AS, LD, AR, NM, STRIP, OBJCOPY, OBJDUMP $(CONFIG_FOO) evaluates to either y (for built-in) or m (for module).
CPPFLAGS, CFLAGS, CFLAGS_KERNEL, MODFLAGS, AFLAGS, LDFLAGS If CONFIG_FOO is neither y nor m, then the file will not be compiled
PERL nor linked.
GENKSYMS
These variables specify the commands and flags that Rules.make --- 3.2 Built-in object goals - obj-y
uses to build goal files from source files.
$(CFLAGS_KERNEL) contains extra C compiler flags used to compile The kbuild Makefile specifies object files for vmlinux
resident kernel code. in the lists $(obj-y). These lists depend on the kernel
configuration.
$(MODFLAGS) contains extra C compiler flags used to compile code Kbuild compiles all the $(obj-y) files. It then calls
for loadable kernel modules. In the future, this flag may be "$(LD) -r" to merge these files into one built-in.o file.
renamed to the more regular name $(CFLAGS_MODULE). built-in.o is later linked into vmlinux by the parent Makefile.
$(AFLAGS) contains assembler flags. The order of files in $(obj-y) is significant. Duplicates in
the lists are allowed: the first instance will be linked into
built-in.o and succeeding instances will be ignored.
$(GENKSYMS) contains the command used to generate kernel symbol Link order is significant, because certain functions
signatures when CONFIG_MODVERSIONS is enabled. The genksyms (module_init() / __initcall) will be called during boot in the
command comes from the module-init-tools package. order they appear. So keep in mind that changing the link
order may e.g. change the order in which your SCSI
controllers are detected, and thus you disks are renumbered.
CROSS_COMPILE Example:
#drivers/isdn/i4l/Makefile
# Makefile for the kernel ISDN subsystem and device drivers.
# Each configuration option enables a list of files.
obj-$(CONFIG_ISDN) += isdn.o
obj-$(CONFIG_ISDN_PPP_BSDCOMP) += isdn_bsdcomp.o
This variable is a prefix path for other variables such as $(CC), --- 3.3 Loadable module goals - obj-m
$(AS), and $(LD). The arch Makefiles sometimes use and set this
variable explicitly. Subdirectory Makefiles don't need to worry
about it.
The user may override $(CROSS_COMPILE) on the command line if $(obj-m) specify object files which are built as loadable
desired. kernel modules.
HOSTCC, HOSTCFLAGS A module may be built from one source file or several source
files. In the case of one source file, the kbuild makefile
simply adds the file to $(obj-m).
These variables define the C compiler and C compiler flags to Example:
be used for compiling host side programs. These are separate #drivers/isdn/i4l/Makefile
variables because the target architecture can be different from obj-$(CONFIG_ISDN_PPP_BSDCOMP) += isdn_bsdcomp.o
the host architecture.
If your Makefile compiles and runs a program that is executed Note: In this example $(CONFIG_ISDN_PPP_BSDCOMP) evaluates to 'm'
during the course of building the kernel, then it should use
$(HOSTCC) and $(HOSTCFLAGS).
For example, the subdirectory drivers/pci has a helper program If a kernel module is built from several source files, you specify
named gen-devlist.c. This program reads a list of PCI ID's and that you want to build a module in the same way as above.
generates C code in the output files classlist.h and devlist.h.
Suppose that a user has an i386 computer and wants to build a Kbuild needs to know which the parts that you want to build your
kernel for an ia64 machine. Then the user would use an ia64 module from, so you have to tell it by setting an
cross-compiler for most of the compilation, but would use a $(<module_name>-objs) variable.
native i386 host compiler to compile drivers/pci/gen-devlist.c.
For another example, kbuild helper programs such as Example:
scripts/mkdep.c and scripts/lxdialog/*.c are compiled with #drivers/isdn/i4l/Makefile
$(HOSTCC) rather than $(CC). obj-$(CONFIG_ISDN) += isdn.o
isdn-objs := isdn_net_lib.o isdn_v110.o isdn_common.o
ROOT_DEV, SVGA_MODE, RAMDISK In this example, the module name will be isdn.o. Kbuild will
compile the objects listed in $(isdn-objs) and then run
"$(LD) -r" on the list of these files to generate isdn.o.
End users edit these variables to specify certain information Kbuild recognises objects used for composite objects by the suffix
about the configuration of their kernel. These variables -objs, and the suffix -y. This allows the Makefiles to use
are ancient! They are also specific to the i386 architecture. the value of a CONFIG_ symbol to determine if an object is part
They really should be replaced with CONFIG_* options. of a composite object.
MAKEBOOT Example:
#fs/ext2/Makefile
obj-$(CONFIG_EXT2_FS) += ext2.o
ext2-y := balloc.o bitmap.o
ext2-$(CONFIG_EXT2_FS_XATTR) += xattr.o
This variable is defined and used only inside the main arch In this example xattr.o is only part of the composite object
Makefiles. The top Makefile should not export it. ext2.o, if $(CONFIG_EXT2_FS_XATTR) evaluates to 'y'.
INSTALL_PATH Note: Of course, when you are building objects into the kernel,
the syntax above will also work. So, if you have CONFIG_EXT2_FS=y,
kbuild will build an ext2.o file for you out of the individual
parts and then link this into built-in.o, as you would expect.
This variable defines a place for the arch Makefiles to install --- 3.4 Objects which export symbols - export-objs
the resident kernel image and System.map file.
INSTALL_MOD_PATH, MODLIB When using loadable modules, not every global symbol in the
kernel / other modules is automatically available, only those
explicitly exported are available for your module.
$(INSTALL_MOD_PATH) specifies a prefix to $(MODLIB) for module To make a symbol available for use in modules, to "export" it,
installation. This variable is not defined in the Makefile but use the EXPORT_SYMBOL(<symbol>) directive in your source. In
may be passed in by the user if desired. addition, you need to list all object files which export symbols
(i.e. their source contains an EXPORT_SYMBOL() directive) in the
Makefile variable $(export-objs).
$(MODLIB) specifies the directory for module installation. Example:
The top Makefile defines $(MODLIB) to #drivers/isdn/i4l/Makefile
$(INSTALL_MOD_PATH)/lib/modules/$(KERNELRELEASE). The user may # Objects that export symbols.
override this value on the command line if desired. export-objs := isdn_common.o
CONFIG_SHELL since isdn_common.c contains
This variable is private between Makefile and Rules.make. EXPORT_SYMBOL(register_isdn);
Arch makefiles and subdirectory Makefiles should never use this.
MODVERFILE which makes the function register_isdn available to
low-level ISDN drivers.
There exist a EXPORT_SYMBOL_GPL() variant with similar functionality,
but more restrictive with what may use that symbol. The requirement
to list the .o file in export-objs is the same.
An internal variable. This doesn't need to be exported, as it --- 3.5 Library file goals - L_TARGET
is never used outside of the top Makefile.
MAKE, MAKEFILES Instead of building a built-in.o file, you may also
build an archive which again contains objects listed in $(obj-y).
This is normally not necessary and only used in lib/ and
arch/$(ARCH)/lib directories.
Only the name lib.a is allowed.
Some variables internal to GNU Make. Example:
#arch/i386/lib/Makefile
L_TARGET := lib.a
obj-y := checksum.o delay.o
$(MAKEFILES) in particular is used to force the arch Makefiles This will create a library lib.a based on checksum.o and delay.o.
and subdirectory Makefiles to read $(TOPDIR)/.config without
including it explicitly. (This was an implementational hack
and could be fixed).
--- 3.6 Descending down in directories
A Makefile is only responsible for building objects in its own
directory. Files in subdirectories should be taken care of by
Makefiles in these subdirs. The build system will automatically
invoke make recursively in subdirectories, provided you let it know of
them.
=== 5 The structure of an arch Makefile To do so obj-y and obj-m are used.
ext2 lives in a separate directory, and the Makefile present in fs/
tells kbuild to descend down using the following assignment.
Example:
#fs/Makefile
obj-$(CONfIG_EXT2_FS) += ext2/
If CONFIG_EXT2_FS is set to either 'y' (built-in) or 'm' (modular)
the corresponding obj- variable will be set, and kbuild will descend
down in the ext2 directory.
Kbuild only uses this information to decide that it needs to visit
the directory, it is the Makefile in the subdirectory that
specifies what is modules and what is built-in.
--- 5.1 Architecture-specific variables It is good practice to use a CONFIG_ variable when assigning directory
names. This allows kbuild to totally skip the directory if the
corresponding CONFIG_ option is neither 'y' nor 'm'.
The top Makefile includes one arch Makefile file, arch/$(ARCH)/Makefile. --- 3.7 Compilation flags
This section describes the functions of the arch Makefile.
An arch Makefile extends some of the top Makefile's variables with EXTRA_CFLAGS, EXTRA_AFLAGS, EXTRA_LDFLAGS, EXTRA_ARFLAGS
architecture-specific values.
SUBDIRS All the EXTRA_ variables apply only to the kbuild makefile
where they are assigned. The EXTRA_ variables apply to all
commands executed in the kbuild makefile.
The top Makefile defines $(SUBDIRS). The arch Makefile extends $(EXTRA_CFLAGS) specifies options for compiling C files with
$(SUBDIRS) with a list of architecture-specific directories. $(CC).
Example: Example:
# drivers/sound/emu10k1/Makefile
# arch/alpha/Makefile EXTRA_CFLAGS += -I$(obj)
ifdef DEBUG
SUBDIRS := $(SUBDIRS) arch/alpha/kernel arch/alpha/mm \ EXTRA_CFLAGS += -DEMU10K1_DEBUG
arch/alpha/lib arch/alpha/math-emu
This list may depend on the configuration:
# arch/arm/Makefile
ifeq ($(CONFIG_ARCH_ACORN),y)
SUBDIRS += drivers/acorn
...
endif endif
CPP, CC, AS, LD, AR, NM, STRIP, OBJCOPY, OBJDUMP
CPPFLAGS, CFLAGS, CFLAGS_KERNEL, MODFLAGS, AFLAGS, LDFLAGS
The top Makefile defines these variables, and the arch Makefile
extends them.
Many arch Makefiles dynamically run the target C compiler to
probe supported options:
# arch/i386/Makefile
# prevent gcc from keeping the stack 16 byte aligned
CFLAGS += $(shell if $(CC) -mpreferred-stack-boundary=2 \
-S -o /dev/null -xc /dev/null >/dev/null 2>&1; \
then echo "-mpreferred-stack-boundary=2"; fi)
And, of course, $(CFLAGS) can depend on the configuration:
# arch/i386/Makefile
ifdef CONFIG_M386 This variable is necessary because the top Makefile owns the
CFLAGS += -march=i386 variable $(CFLAGS) and uses it for compilation flags for the
endif entire tree.
ifdef CONFIG_M486 $(EXTRA_AFLAGS) is a similar string for per-directory options
CFLAGS += -march=i486 when compiling assembly language source.
endif
ifdef CONFIG_M586 Example:
CFLAGS += -march=i586 #arch/x86_64/kernel/Makefile
endif EXTRA_AFLAGS := -traditional
Some arch Makefiles redefine the compilation commands in order
to add architecture-specific flags:
# arch/s390/Makefile $(EXTRA_LDFLAGS) and $(EXTRA_ARFLAGS) are similar strings for
per-directory options to $(LD) and $(AR).
LD=$(CROSS_COMPILE)ld -m elf_s390 Example:
OBJCOPY=$(CROSS_COMPILE)objcopy -O binary -R .note -R .comment -S #arch/m68k/fpsp040/Makefile
EXTRA_LDFLAGS := -x
CFLAGS_$@, AFLAGS_$@
CFLAGS_$@ and AFLAGS_$@ only apply to commands in current
kbuild makefile.
--- 5.2 Vmlinux build variables $(CFLAGS_$@) specifies per-file options for $(CC). The $@
part has a literal value which specifies the file that it is for.
An arch Makefile cooperates with the top Makefile to define variables Example:
which specify how to build the vmlinux file. Note that there is no # drivers/scsi/Makefile
corresponding arch-specific section for modules; the module-building CFLAGS_aha152x.o = -DAHA152X_STAT -DAUTOCONF
machinery is all architecture-independent. CFLAGS_gdth.o = # -DDEBUG_GDTH=2 -D__SERIAL__ -D__COM2__ \
-DGDTH_STATISTICS
CFLAGS_seagate.o = -DARBITRATE -DPARITY -DSEAGATE_USE_ASM
HEAD, CORE_FILES, LIBS These three lines specify compilation flags for aha152x.o,
LINKFLAGS gdth.o, and seagate.o
The top Makefile defines the architecture-independent core of $(AFLAGS_$@) is a similar feature for source files in assembly
thse variables, and the arch Makefile extends them. Note that the languages.
arch Makefile defines (not just extends) $(HEAD) and $(LINKFLAGS).
Example: Example:
# arch/arm/kernel/Makefile
AFLAGS_head-armv.o := -DTEXTADDR=$(TEXTADDR) -traditional
AFLAGS_head-armo.o := -DTEXTADDR=$(TEXTADDR) -traditional
# arch/m68k/Makefile --- 3.9 Dependency tracking
ifndef CONFIG_SUN3 Kbuild track dependencies on the following:
LINKFLAGS = -T $(TOPDIR)/arch/m68k/vmlinux.lds 1) All prerequisite files (both *.c and *.h)
else 2) CONFIG_ options used in all prerequisite files
LINKFLAGS = -T $(TOPDIR)/arch/m68k/vmlinux-sun3.lds -N 3) Command-line used to compile target
endif
... Thus, if you change an option to $(CC) all affected files will
be re-compiled.
ifndef CONFIG_SUN3 --- 3.10 Special Rules
HEAD := arch/m68k/kernel/head.o
else
HEAD := arch/m68k/kernel/sun3-head.o
endif
SUBDIRS += arch/m68k/kernel arch/m68k/mm arch/m68k/lib Special rules are used when the kbuild infrastructure does
CORE_FILES := arch/m68k/kernel/kernel.o arch/m68k/mm/mm.o $(CORE_FILES) not provide the required support. A typical example is
LIBS += arch/m68k/lib/lib.a header files generated during the build process.
Another example is the architecture specific Makefiles which
needs special rules to prepare boot images etc.
Special rules are written as normal Make rules.
Kbuild is not executing in the directory where the Makefile is
located, so all special rules shall provide a relative
path to prerequisite files and target files.
Two variables are used when defining special rules:
--- 5.3 Post-vmlinux goals $(src)
$(src) is a relative path which points to the directory
where the Makefile is located. Always use $(src) when
referring to files located in the src tree.
An arch Makefile specifies goals that take the vmlinux file, compress $(obj)
it, wrap it in bootstrapping code, and copy the resulting files somewhere. $(obj) is a relative path which points to the directory
This includes various kinds of installation commands. where the target is saved. Always use $(obj) when
referring to generated files.
These post-vmlinux goals are not standardized across different Example:
architectures. Here is a list of these goals and the architectures #drivers/scsi/Makefile
that support each of them (as of kernel version 2.4.0-test6-pre5): $(obj)/53c8xx_d.h: $(src)/53c7,8xx.scr $(src)/script_asm.pl
$(CPP) -DCHIP=810 - < $< | ... $(src)/script_asm.pl
balo mips This is a special rule, following the normal syntax
bootimage alpha required by make.
bootpfile alpha, ia64 The target file depends on two prerequisite files. References
bzImage i386, m68k to the target file are prefixed with $(obj), references
bzdisk i386 to prerequisites are referenced with $(src) (because they are not
bzlilo i386 generated files).
compressed i386, m68k, mips, mips64, sh
dasdfmt s390
Image arm
image s390
install arm, i386
lilo m68k
msb alpha, ia64
my-special-boot alpha, ia64
orionboot mips
rawboot alpha
silo s390
srmboot alpha
tftpboot.img sparc, sparc64
vmlinux.64 mips64
vmlinux.aout sparc64
zImage arm, i386, m68k, mips, mips64, ppc, sh
zImage.initrd ppc
zdisk i386, mips, mips64, sh
zinstall arm
zlilo i386
znetboot.initrd ppc
=== 4 Host Program support
--- 5.4 Mandatory arch-specific goals Kbuild supports building executables on the host for use during the
compilation stage.
Two steps are required in order to use a host executable.
An arch Makefile must define the following arch-specific goals. The first step is to tell kbuild that a host program exists. This is
These goals provide arch-specific actions for the corresponding goals done utilising the variable host-prog.
in the top Makefile:
archclean clean The second step is to add an explicit dependency to the executable.
archdep dep This can be done in two ways. Either add the dependency in a rule,
archmrproper mrproper or utilise the variable build-targets.
Both possibilities are described in the following.
--- 4.1 Simple Host Program
In some cases there is a need to compile and run a program on the
computer where the build is running.
The following line tells kbuild that the program bin2hex shall be
built on the build host.
=== 6 The structure of a subdirectory Makefile Example:
host-progs := bin2hex
A subdirectory Makefile has four sections. Kbuild assumes in the above example that bin2hex is made from a single
c-source file named bin2hex.c located in the same directory as
the Makefile.
--- 4.2 Composite Host Programs
Host programs can be made up based on composite objects.
The syntax used to define composite objetcs for host programs is
similar to the syntax used for kernel objects.
$(<executeable>-objs) list all objects used to link the final
executable.
--- 6.1 Comments Example:
#scripts/lxdialog/Makefile
host-progs := lxdialog
lxdialog-objs := checklist.o lxdialog.o
The first section is a comment header. Historically, many anonymous Objects with extension .o are compiled from the corresponding .c
people have edited kernel Makefiles without leaving any change files. In the above example checklist.c is compiled to checklist.o
histories in the header; comments from them would have been valuable. and lxdialog.c is compiled to lxdialog.o.
Finally the two .o files are linked to the executable, lxdialog.
Note: The syntax <executable>-y is not permitted for host-programs.
--- 4.3 Defining shared libraries
Objects with extension .so are considered shared libraries, and
will be compiled as position independent objects.
Kbuild provides support for shared libraries, but the usage
shall be restricted.
In the following example the libkconfig.so shared library is used
to link the executable conf.
--- 6.2 Goal definitions Example:
#scripts/kconfig/Makefile
host-progs := conf
conf-objs := conf.o libkconfig.so
libkconfig-objs := expr.o type.o
The second section is a bunch of definitions that are the heart of the Shared libraries always require a corresponding -objs line, and
subdirectory Makefile. These lines define the files to be built, any in the example above the shared library libkconfig is composed by
special compilation options, and any subdirectories to be recursively the two objects expr.o and type.o.
entered. The declarations in these lines depend heavily on the kernel expr.o and type.o will be built as position independent code and
configuration variables (CONFIG_* symbols). linked as a shared library libkconfig.so. C++ is not supported for
shared libraries.
The second section looks like this: --- 4.4 Using C++ for host programs
# drivers/block/Makefile kbuild offers support for host programs written in C++. This was
obj-$(CONFIG_MAC_FLOPPY) += swim3.o introduced solely to support kconfig, and is not recommended
obj-$(CONFIG_BLK_DEV_FD) += floppy.o for general use.
obj-$(CONFIG_AMIGA_FLOPPY) += amiflop.o
obj-$(CONFIG_ATARI_FLOPPY) += ataflop.o
Example:
#scripts/kconfig/Makefile
host-progs := qconf
qconf-cxxobjs := qconf.o
--- 6.4 Rules.make section In the example above the executable is composed of the C++ file
qconf.cc - identified by $(qconf-cxxobjs).
The third section is the single line: If qconf is composed by a mixture of .c and .cc files, then an
additional line can be used to identify this.
include $(TOPDIR)/Rules.make Example:
#scripts/kconfig/Makefile
host-progs := qconf
qconf-cxxobjs := qconf.o
qconf-objs := check.o
--- 4.5 Controlling compiler options for host programs
When compiling host programs, it is possible to set specific flags.
The programs will always be compiled utilising $(HOSTCC) passed
the options specified in $(HOSTCFLAGS).
To set flags that will take effect for all host programs created
in that Makefile use the variable HOST_EXTRACFLAGS.
--- 6.5 Special rules Example:
#scripts/lxdialog/Makefile
HOST_EXTRACFLAGS += -I/usr/include/ncurses
The fourth section contains any special Makefile rules needed that are To set specific flags for a single file the following construction
not available through the common rules in Rules.make. is used:
Example:
#arch/ppc64/boot/Makefile
HOSTCFLAGS_piggyback.o := -DKERNELBASE=$(KERNELBASE)
It is also possible to specify additional options to the linker.
=== 7 Rules.make variables Example:
#scripts/kconfig/Makefile
HOSTLOADLIBES_qconf := -L$(QTDIR)/lib
The public interface of Rules.make consists of the following variables: When linking qconf it will be passed the extra option "-L$(QTDIR)/lib".
--- 4.6 When host programs are actually built
Kbuild will only build host-programs when they are referenced
as a prerequisite.
This is possible in two ways:
--- 7.1 Subdirectories (1) List the prerequisite explicitly in a special rule.
A Makefile is only responsible for building objects in its own Example:
directory. Files in subdirectories should be taken care of by #drivers/pci/Makefile
Makefiles in the these subdirs. The build system will automatically host-progs := gen-devlist
invoke make recursively in subdirectories, provided you let it know of $(obj)/devlist.h: $(src)/pci.ids $(obj)/gen-devlist
them. ( cd $(obj); ./gen-devlist ) < $<
To do so, use the subdir-{y,m,n,} variables: The target $(obj)/devlist.h will not be built before
$(obj)/gen-devlist is updated. Note that references to
the host programs in special rules must be prefixed with $(obj).
subdir-$(CONFIG_ISDN) += i4l (2) Use $(build-targets)
subdir-$(CONFIG_ISDN_CAPI) += capi When there is no suitable special rule, and the host program
shall be built when a makefile is entered, the $(build-targets)
variable shall be used.
When building the actual kernel, i.e. vmlinux ("make Example:
{vmlinux,bzImage,...}"), make will recursively descend into #scripts/lxdialog/Makefile
directories listed in $(subdir-y). host-progs := lxdialog
build-targets := $(host-progs)
When building modules ("make modules"), make will recursively descend This will tell kbuild to build lxdialog even if not referenced in
into directories listed in $(subdir-m). any rule.
When building the dependencies ("make dep") make needs to visit every === 5 Kbuild clean infrastructure
subdir, so it'll descend into every directory listed in
$(subdir-y), $(subdir-m), $(subdir-n), $(subdir-).
You may encounter the case where a config option may be set to "y", but "make clean" deletes most generated files in the src tree where the kernel
you still want to possibly build modules in that subdirectory. is compiled. This includes generated files such as host programs.
Kbuild knows targets listed in $(host-progs) and $(EXTRA_TARGETS) and
they are all deleted during "make clean".
Files matching the patterns "*.[oas]", "*.ko", plus some additional files
generated by kbuild are deleted all over the kernel src tree when
"make clean" is executed.
For example, drivers/isdn/capi/Makefile has Additional files can be specified by means of $(clean-files).
obj-$(CONFIG_ISDN_CAPI) += kernelcapi.o capiutil.o Example:
obj-$(CONFIG_ISDN_CAPI_CAPI20) += capi.o #drivers/pci/Makefile
clean-files := devlist.h classlist.h
where it's possible that CONFIG_ISDN_CAPI=y, but When executing "make clean", the two files "devlist.h classlist.h" will
CONFIG_ISDN_CAPI_CAPI20=m. be deleted. Kbuild knows that files specified by $(clean-files) are
located in the same directory as the makefile.
This is expressed by the following construct in the parent Makefile Usually kbuild descends down in subdirectories due to "obj-* := dir/",
drivers/isdn/Makefile: but in the architecture makefiles where the kbuild infrastructure
is not sufficent this sometimes needs to be explicit.
mod-subdirs := i4l hisax capi eicon Example:
subdir-$(CONFIG_ISDN_CAPI) += capi #arch/i386/boot/Makefile
subdir- := compressed/
Having a subdir ("capi") listed in the variable $(mod-subdirs) will The above assignment instructs kbuild to descend down in the
make the build system enter the specified subdirectory during "make directory compressed/ when "make clean" is executed.
modules" also, even though the subdir ("capi") is listed only in
$(subdir-y), not $(subdir-m).
To support the clean infrastructure in the Makefiles that builds the
final bootimage there is an optional target named archclean:
--- 7.2 Object file goals Example:
#arch/i386/Makefile
archclean:
$(Q)$(MAKE) $(clean)=arch/i386/boot
When "make clean" is executed, make will descend down in arch/i386/boot,
and clean as usual. The Makefile located in arch/i386/boot/ may use
the subdir- trick to descend further down.
Note 1: arch/$(ARCH)/Makefile cannot use "subdir-", because that file is
included in the top level makefile, and the kbuild infrastructure
is not operational at that point.
Note 2: All directories listed in core-y, libs-y, drivers-y and net-y will
be visited during "make clean".
=== 6 Architecture Makefiles
The top level Makefile sets up the environment and does the preparation,
before starting to descend down in the individual directories.
The top level makefile contains the generic part, whereas the
arch/$(ARCH)/Makefile contains what is required to set-up kbuild
to the said architecture.
To do so arch/$(ARCH)/Makefile sets a number of variables, and defines
a few targets.
When kbuild executes the following steps are followed (roughly):
1) Configuration of the kernel => produced .config
2) Store kernel version in include/linux/version.h
3) Symlink include/asm to include/asm-$(ARCH)
4) Updating all other prerequisites to the target prepare:
- Additional prerequisites are specified in arch/$(ARCH)/Makefile
5) Recursively descend down in all directories listed in
init-* core* drivers-* net-* libs-* and build all targets.
- The value of the above variables are extended in arch/$(ARCH)/Makefile.
6) All object files are then linked and the resulting file vmlinux is
located at the root of the src tree.
The very first objects linked are listed in head-y, assigned by
arch/$(ARCH)/Makefile.
7) Finally the architecture specific part does any required post processing
and builds the final bootimage.
- This includes building boot records
- Preparing initrd images and the like
--- 6.1 Set variables to tweak the build to the architecture
LDFLAGS Generic $(LD) options
Flags used for all invocations of the linker.
Often specifying the emulation is sufficient.
O_TARGET, obj-y Example:
#arch/s390/Makefile
LDFLAGS := -m elf_s390
Note: EXTRA_LDFLAGS and LDFLAGS_$@ can be used to further customise
the flags used. See chapter 7.
The subdirectory Makefile specifies object files for vmlinux LDFLAGS_MODULE Options for $(LD) when linking modules
in the lists $(obj-y). These lists depend on the kernel
configuration.
Rules.make compiles all the $(obj-y) files. It then calls LDFLAGS_MODULE is used to set specific flags for $(LD) when
"$(LD) -r" to merge these files into one .o file with the name linking the .ko files used for modules.
$(O_TARGET). This $(O_TARGET) is later linked into vmlinux by Default is "-r", for relocatable output.
a parent Makefile.
The order of files in $(obj-y) is significant. Duplicates in LDFLAGS_vmlinux Options for $(LD) when linking vmlinux
the lists are allowed: the first instance will be linked into
$(O_TARGET) and succeeding instances will be ignored.
Link order is significant, because certain functions LDFLAGS_vmlinux is used to specify additional flags to pass to
(module_init() / __initcall) will be called during boot in the the linker when linking the final vmlinux.
order they appear. So keep in mind that changing the link LDFLAGS_vmlinux uses the LDFLAGS_$@ support.
order may e.g. change the order in which your SCSI
controllers are detected, and thus you disks are renumbered.
Example: Example:
#arch/i386/Makefile
LDFLAGS_vmlinux := -e stext
# Makefile for the kernel ISDN subsystem and device drivers. LDFLAGS_BLOB Options for $(LD) when linking the initramfs blob
# The target object and module list name.
O_TARGET := vmlinux-obj.o
# Each configuration option enables a list of files. The image used for initramfs is made during the build process.
LDFLAGS_BLOB is used to specify additional flags to be used when
creating the initramfs_data.o file.
Example:
#arch/i386/Makefile
LDFLAGS_BLOB := --format binary --oformat elf32-i386
obj-$(CONFIG_ISDN) += isdn.o OBJCOPYFLAGS objcopy flags
obj-$(CONFIG_ISDN_PPP_BSDCOMP) += isdn_bsdcomp.o
# The global Rules.make. When $(call if_changed,objcopy) is used to translate a .o file,
then the flags specified in OBJCOPYFLAGS will be used.
$(call if_changed,objcopy) is often used to generate raw binaries on
vmlinux.
include $(TOPDIR)/Rules.make Example:
#arch/s390/Makefile
OBJCOPYFLAGS := -O binary
--- 7.3 Library file goals #arch/s390/boot/Makefile
$(obj)/image: vmlinux FORCE
$(call if_changed,objcopy)
L_TARGET In this example the binary $(obj)/image is a binary version of
vmlinux. The usage of $(call if_changed,xxx) will be described later.
Instead of building an O_TARGET object file, you may also AFLAGS $(AS) assembler flags
build an archive which again contains objects listed in
$(obj-y). This is normally not necessary and only used in
the lib, arch/$(ARCH)/lib directories.
Default value - see top level Makefile
Append or modify as required per architecture.
--- 7.4 Loadable module goals Example:
#arch/sparc64/Makefile
AFLAGS += -m64 -mcpu=ultrasparc
obj-m CFLAGS $(CC) compiler flags
$(obj-m) specify object files which are built as loadable Default value - see top level Makefile
kernel modules. Append or modify as required per architecture.
A module may be built from one source file or several source Often the CFLAGS variable depends on the configuration.
files. In the case of one source file, the subdirectory
Makefile simply adds the file to $(obj-m)
Example: Example:
#arch/i386/Makefile
cflags-$(CONFIG_M386) += -march=i386
CFLAGS += $(cflags-y)
obj-$(CONFIG_ISDN_PPP_BSDCOMP) += isdn_bsdcomp.o Many arch Makefiles dynamically run the target C compiler to
probe supported options:
If a kernel module is built from several source files, you specify
that you want to build a module in the same way as above.
However, the build system of course needs to know which the parts
are that you want to build your module of, so you have to tell it
by setting an $(<module_name>-objs) variable.
Example: #arch/i386/Makefile
check_gcc = $(shell if $(CC) $(1) -S -o /dev/null -xc \
/dev/null\ > /dev/null 2>&1; then echo "$(1)"; \
else echo "$(2)"; fi)
cflags-$(CONFIG_MCYRIXIII) += $(call check_gcc,\
-march=c3,-march=i486)
obj-$(CONFIG_ISDN) += isdn.o CFLAGS += $(cflags-y)
isdn-objs := isdn_net.o isdn_tty.o isdn_v110.o isdn_common.o The above examples both utilise the trick that a config option expands
to 'y' when selected.
In this example, the module name will be isdn.o. Rules.make CFLAGS_KERNEL $(CC) options specific for built-in
will compile the objects listed in $(isdn-objs) and then run
"$(LD) -r" on the list of these files to generate isdn.o
Note: Of course, when you are building objects into the kernel, $(CFLAGS_KERNEL) contains extra C compiler flags used to compile
the syntax above will also work. So, if you have CONFIG_ISDN=y, resident kernel code.
the build system will build an isdn.o for you out of the individual
parts and then link this into the $(O_TARGET), as you'd expect.
CFLAGS_MODULE $(CC) options specific for modules
--- 7.5 Objects which export symbols $(CFLAGS_MODULE) contains extra C compiler flags used to compile code
for loadable kernel modules.
export-objs
When using loadable modules, not every global symbol in the --- 6.2 Add prerequisites to prepare:
kernel / other modules is automatically available, only those
explicitly exported are available for your module.
To make a symbol available for use in modules, to "export" it, The prepare: rule is used to list prerequisites that needs to be
use the EXPORT_SYMBOL(<symbol>) directive in your source. In built before starting to descend down in the subdirectories.
addition, you need to list all object files which export symbols This is usual header files containing assembler constants.
(i.e. their source contains an EXPORT_SYMBOL() directive) in the
Makefile variable $(export-objs).
Example: Example:
#arch/s390/Makefile
prepare: include/asm-$(ARCH)/offsets.h
# Objects that export symbols. In this example the file include/asm-$(ARCH)/offsets.h will
be built before descending down in the subdirectories.
See also chapter XXX-TODO that describe how kbuild supports
generating offset header files.
export-objs := isdn_common.o
since isdn_common.c contains --- 6.3 List directories to visit when descending
EXPORT_SYMBOL(register_isdn); An arch Makefile cooperates with the top Makefile to define variables
which specify how to build the vmlinux file. Note that there is no
corresponding arch-specific section for modules; the module-building
machinery is all architecture-independent.
which makes the function register_isdn available to
low-level ISDN drivers.
head-y, init-y, core-y, libs-y, drivers-y, net-y
--- 7.6 Compilation flags $(head-y) list objects to be linked first in vmlinux.
$(libs-y) list directories where a libs.a archive can be located.
The rest list directories where a built-in.o object file can be located.
EXTRA_CFLAGS, EXTRA_AFLAGS, EXTRA_LDFLAGS, EXTRA_ARFLAGS $(init-y) objects will be located after $(head-y).
Then the rest follows in this order:
$(core-y), $(libs-y), $(drivers-y) and $(net-y).
$(EXTRA_CFLAGS) specifies options for compiling C files with The top level Makefile define values for all generic directories,
$(CC). The options in this variable apply to all $(CC) commands and arch/$(ARCH)/Makefile only adds architecture specific directories.
for files in the current directory.
Example: Example:
#arch/sparc64/Makefile
core-y += arch/sparc64/kernel/
libs-y += arch/sparc64/prom/ arch/sparc64/lib/
drivers-$(CONFIG_OPROFILE) += arch/sparc64/oprofile/
# drivers/sound/emu10k1/Makefile
EXTRA_CFLAGS += -I.
ifdef DEBUG
EXTRA_CFLAGS += -DEMU10K1_DEBUG
endif
$(EXTRA_CFLAGS) does not apply to subdirectories of the current
directory. Also, it does not apply to files compiled with
$(HOSTCC).
This variable is necessary because the top Makefile owns the --- 6.4 Architecture specific boot images
variable $(CFLAGS) and uses it for compilation flags for the
entire tree.
$(EXTRA_AFLAGS) is a similar string for per-directory options An arch Makefile specifies goals that take the vmlinux file, compress
when compiling assembly language source. it, wrap it in bootstrapping code, and copy the resulting files
somewhere. This includes various kinds of installation commands.
The actual goals are not standardized across architectures.
Example: at the time of writing, there were no examples of It is common to locate any additional processing in a boot/
$(EXTRA_AFLAGS) in the kernel corpus. directory below arch/$(ARCH)/.
$(EXTRA_LDFLAGS) and $(EXTRA_ARFLAGS) are similar strings for Kbuild does not provide any smart way to support building a
per-directory options to $(LD) and $(AR). target specified in boot/. Therefore arch/$(ARCH)/Makefile shall
call make manually to build a target in boot/.
Example: at the time of writing, there were no examples of The recommended approach is to include shortcuts in
$(EXTRA_LDFLAGS) or $(EXTRA_ARFLAGS) in the kernel corpus. arch/$(ARCH)/Makefile, and use the full path when calling down
into the arch/$(ARCH)/boot/Makefile.
CFLAGS_$@, AFLAGS_$@
$(CFLAGS_$@) specifies per-file options for $(CC). The $@
part has a literal value which specifies the file that it's for.
Example: Example:
#arch/i386/Makefile
boot := arch/i386/boot
bzImage: vmlinux
$(Q)$(MAKE) $(build)=$(boot) $(boot)/$@
# drivers/scsi/Makefile "$(Q)$(MAKE) $(build)=<dir>" is the recommended way to invoke
CFLAGS_aha152x.o = -DAHA152X_STAT -DAUTOCONF make in a subdirectory.
CFLAGS_gdth.o = # -DDEBUG_GDTH=2 -D__SERIAL__ -D__COM2__ \
-DGDTH_STATISTICS
CFLAGS_seagate.o = -DARBITRATE -DPARITY -DSEAGATE_USE_ASM
These three lines specify compilation flags for aha152x.o, There are no rules for naming of the architecture specific targets,
gdth.o, and seagate.o but executing "make help" will list all relevant targets.
To support this $(archhelp) must be defined.
$(AFLAGS_$@) is a similar feature for source files in assembly
languages.
Example: Example:
#arch/i386/Makefile
define archhelp
echo '* bzImage - Image (arch/$(ARCH)/boot/bzImage)'
endef
When make is executed without arguments, the first goal encountered
will be built. In the top level Makefile the first goal present
is all:.
An architecture shall always per default build a bootable image.
In "make help" the default goal is highlighted with a '*'.
Add a new prerequisite to all: to select a default goal different
from vmlinux.
# arch/arm/kernel/Makefile Example:
AFLAGS_head-armv.o := -DTEXTADDR=$(TEXTADDR) -traditional #arch/i386/Makefile
AFLAGS_head-armo.o := -DTEXTADDR=$(TEXTADDR) -traditional all: bzImage
Rules.make has a feature where an object file depends on the
value of $(CFLAGS_$@) that was used to compile it. (It also
depends on the values of $(CFLAGS) and $(EXTRA_CFLAGS)). Thus,
if you change the value of $(CFLAGS_$@) for a file, either by
editing the Makefile or overriding the value some other way,
Rules.make will do the right thing and re-compile your source
file with the new options.
Note: because of a deficiency in Rules.make, assembly language
files do not have flag dependencies. If you edit $(AFLAGS_$@)
for such a file, you will have to remove the object file in order
to re-build from source.
LD_RFLAG
This variable is used, but never defined. It appears to be a
vestige of some abandoned experiment.
--- 7.7 Miscellaneous variables
IGNORE_FLAGS_OBJS When "make" is executed without arguments, bzImage will be built.
$(IGNORE_FLAGS_OBJS) is a list of object files which will not have --- 6.5 Building non-kbuild targets
their flag dependencies automatically tracked. This is a hackish
feature, used to kludge around a problem in the implementation
of flag dependencies. (The problem is that flag dependencies
assume that a %.o file is built from a matching %.S or %.c file.
This is sometimes not true).
USE_STANDARD_AS_RULE EXTRA_TARGETS
This is a transition variable. If $(USE_STANDARD_AS_RULE) EXTRA_TARGETS specify additional targets created in current
is defined, then Rules.make will provide standard rules for directory, in addition to any targets specified by obj-*.
assembling %.S files into %.o files or %.s files (%.s files
are useful only to developers).
If $(USE_STANDARD_AS_RULE) is not defined, then Rules.make Listing all targets in EXTRA_TARGETS is required for three purposes:
will not provide these standard rules. In this case, the 1) Avoid that the target is linked in as part of built-in.o
subdirectory Makefile must provide its own private rules for 2) Enable kbuild to check changes in command lines
assembling %.S files. - When $(call if_changed,xxx) is used
3) kbuild knows what file to delete during "make clean"
In the past, all Makefiles provided private %.S rules. Newer Example:
Makefiles should define USE_STANDARD_AS_RULE and use the standard #arch/i386/kernel/Makefile
Rules.make rules. As soon as all the Makefiles across all EXTRA_TARGETS := head.o init_task.o
architectures have been converted to USE_STANDARD_AS_RULE, then
Rules.make can drop the conditional test on USE_STANDARD_AS_RULE.
After that, all the other Makefiles can drop the definition of
USE_STANDARD_AS_RULE.
In this example EXTRA_TARGETS is used to list object files that
shall be built, but shall not be linked as part of built-in.o.
Example:
#arch/i386/boot/Makefile
EXTRA_TARGETS := vmlinux.bin bootsect bootsect.o
=== 8 New-style variables In this example EXTRA_TARGETS is used to list all intermediate
targets, and all final targets.
The targets are added to EXTRA_TARGETS to enable 2) and 3) above.
[ This sections dates back from a time where the way to write Makefiles --- 6.6 Commands useful for building a boot image
described above was "new-style". I'm leaving it in as it describes the
same thing in other words, so it may be of some use ]
The "new-style variables" are simpler and more powerful than the Kbuild provide a few macros that are useful when building a
"old-style variables". As a result, many subdirectory Makefiles shrank boot image.
more than 60%. This author hopes that, in time, all arch Makefiles and
subdirectory Makefiles will convert to the new style.
Rules.make does not understand new-style variables. Thus, each new-style if_changed
Makefile has a section of boilerplate code that converts the new-style
variables into old-style variables. There is also some mixing, where
people define most variables using "new style" but then fall back to
"old style" for a few lines.
--- 8.1 New variables if_changed is the infrastructure used for the following commands.
obj-y obj-m obj-n obj- Usage:
target: source(s) FORCE
$(call if_changed,ld/objcopy/gzip)
These variables replace $(O_OBJS), $(OX_OBJS), $(M_OBJS), When the rule is evaluated it is checked to see if any files
and $(MX_OBJS). needs an update, or the commandline has changed since last
invocation. The latter will force a rebuild if any options
to the executable have changed.
Any target that utilises if_changed must be listed in EXTRA_TARGETS,
otherwise the command line check will fail, and the target will
always be built.
if_changed may be used in conjunction with custom commands as
defined in 6.7 "Custom kbuild commands".
Note: It is a typical mistake to forget the FORCE prerequisite.
Example: ld
Link target. Often LDFLAGS_$@ is used to set specific options to ld.
# drivers/block/Makefile objcopy
obj-$(CONFIG_MAC_FLOPPY) += swim3.o Copy binary. Uses OBJCOPYFLAGS usually specified in
obj-$(CONFIG_BLK_DEV_FD) += floppy.o arch/$(ARCH)/Makefile.
obj-$(CONFIG_AMIGA_FLOPPY) += amiflop.o
obj-$(CONFIG_ATARI_FLOPPY) += ataflop.o
Notice the use of $(CONFIG_...) substitutions on the left hand gzip
side of an assignment operator. This gives GNU Make the power Compress target. Use maximum compression to compress target.
of associative indexing! Each of these assignments replaces
eight lines of code in an old-style Makefile.
After executing all of the assignments, the subdirectory
Makefile has built up four lists: $(obj-y), $(obj-m), $(obj-n),
and $(obj-).
$(obj-y) is a list of files to include in vmlinux. --- 6.7 Custom kbuild commands
$(obj-m) is a list of files to build as single-file modules.
$(obj-n) and $(obj-) are ignored.
Each list may contain duplicates items; duplicates are When kbuild is executing with KBUILD_VERBOSE=0 then only a shorthand
automatically removed later. Duplicates in both $(obj-y) and of a command is normally displayed.
$(obj-m) will automatically be removed from the $(obj-m) list. To enable this behaviour for custom commands kbuild requires
two variables to be set:
quiet_cmd_<command> - what shall be echoed
cmd_<command> - the command to execute
Example: Example:
#
quiet_cmd_image = BUILD $@
cmd_image = $(obj)/tools/build $(BUILDFLAGS) \
$(obj)/vmlinux.bin > $@
# drivers/net/Makefile $(obj)/bzImage: $(obj)/vmlinux.bin $(obj)/tools/build FORCE
$(call if_changed,image)
... @echo 'Kernel: $@ is ready'
obj-$(CONFIG_OAKNET) += oaknet.o 8390.o
...
obj-$(CONFIG_NE2K_PCI) += ne2k-pci.o 8390.o
...
obj-$(CONFIG_STNIC) += stnic.o 8390.o
...
obj-$(CONFIG_MAC8390) += daynaport.o 8390.o
...
In this example, four different drivers require the code in
8390.o. If one or more of these four drivers are built into
vmlinux, then 8390.o will also be built into vmlinux, and will
*not* be built as a module -- even if another driver which needs
8390.o is built as a module. (The modular driver is able to
use services of the 8390.o code in the resident vmlinux image).
export-objs
$(export-objs) is a list of all the files in the subdirectory
which potentially export symbols. The canonical way to construct
this list is:
grep -l EXPORT_SYMBOL *.c When updating the $(obj)/bzImage target the line:
(but watch out for sneaky files that call EXPORT_SYMBOL from an BUILD arch/i386/boot/bzImage
included header file!)
This is a potential list, independent of the kernel configuration. will be displayed with "make KBUILD_VERBOSE=0".
All files that export symbols go into $(export-objs). The
boilerplate code then uses the $(export-objs) list to separate
the real file lists into $(*_OBJS) and $(*X_OBJS).
Experience has shown that maintaining the proper X's in an
old-style Makefile is difficult and error-prone. Maintaining the
$(export-objs) list in a new-style Makefile is simpler and easier
to audit.
$(foo)-objs === 7 Kbuild Variables
Some kernel modules are composed of multiple object files linked The top Makefile exports the following variables:
together.
For each multi-part kernel modul there is a list of all the VERSION, PATCHLEVEL, SUBLEVEL, EXTRAVERSION
object files which make up that module. For a kernel module
named foo.o, its object file list is foo-objs.
Example: These variables define the current kernel version. A few arch
Makefiles actually use these values directly; they should use
$(KERNELRELEASE) instead.
# drivers/scsi/Makefile $(VERSION), $(PATCHLEVEL), and $(SUBLEVEL) define the basic
list-multi := scsi_mod.o sr_mod.o initio.o a100u2w.o three-part version number, such as "2", "4", and "0". These three
values are always numeric.
... $(EXTRAVERSION) defines an even tinier sublevel for pre-patches
or additional patches. It is usually some non-numeric string
such as "-pre4", and is often blank.
scsi_mod-objs := hosts.o scsi.o scsi_ioctl.o constants.o \ KERNELRELEASE
scsicam.o scsi_proc.o scsi_error.o \
scsi_obsolete.o scsi_queue.o scsi_lib.o \
scsi_merge.o scsi_dma.o scsi_scan.o \
scsi_syms.o
sr_mod-objs := sr.o sr_ioctl.o sr_vendor.o
initio-objs := ini9100u.o i91uscsi.o
a100u2w-objs := inia100.o i60uscsi.o
The subdirectory Makefile puts the modules onto obj-* lists in $(KERNELRELEASE) is a single string such as "2.4.0-pre4", suitable
the usual configuration-dependent way: for constructing installation directory names or showing in
version strings. Some arch Makefiles use it for this purpose.
obj-$(CONFIG_SCSI) += scsi_mod.o ARCH
obj-$(CONFIG_BLK_DEV_SR) += sr_mod.o
obj-$(CONFIG_SCSI_INITIO) += initio.o
obj-$(CONFIG_SCSI_INIA100) += a100u2w.o
Suppose that CONFIG_SCSI=y. Then vmlinux needs to link in all This variable defines the target architecture, such as "i386",
14 components of scsi_mod.o. "arm", or "sparc". Some kbuild Makefiles test $(ARCH) to
determine which files to compile.
Suppose that CONFIG_BLK_DEV_SR=m. Then the 3 components By default, the top Makefile sets $(ARCH) to be the same as the
of sr_mod.o will be linked together with "$(LD) -r" to make the host system architecture. For a cross build, a user may
kernel module sr_mod.o. override the value of $(ARCH) on the command line:
Also suppose CONFIG_SCSI_INITIO=n. Then initio.o goes onto make ARCH=m68k ...
the $(obj-n) list and that's the end of it. Its component
files are not compiled, and the composite file is not created.
subdir-y subdir-m subdir-n subdir- INSTALL_PATH
These variables replace $(ALL_SUB_DIRS), $(SUB_DIRS) and This variable defines a place for the arch Makefiles to install
$(MOD_SUB_DIRS). the resident kernel image and System.map file.
Use this for architecture specific install targets.
Example: INSTALL_MOD_PATH, MODLIB
# drivers/Makefile $(INSTALL_MOD_PATH) specifies a prefix to $(MODLIB) for module
subdir-$(CONFIG_PCI) += pci installation. This variable is not defined in the Makefile but
subdir-$(CONFIG_PCMCIA) += pcmcia may be passed in by the user if desired.
subdir-$(CONFIG_MTD) += mtd
subdir-$(CONFIG_SBUS) += sbus
These variables work similar to obj-*, but are used for $(MODLIB) specifies the directory for module installation.
subdirectories instead of object files. The top Makefile defines $(MODLIB) to
$(INSTALL_MOD_PATH)/lib/modules/$(KERNELRELEASE). The user may
override this value on the command line if desired.
After executing all assignments, the subdirectory Makefile has === 8 Makefile language
built up four lists: $(subdir-y), $(subdir-m), $(subdir-n),
and $(subdir-).
$(subdir-y) is a list of directories that should be entered The kernel Makefiles are designed to run with GNU Make. The Makefiles
for making vmlinux. use only the documented features of GNU Make, but they do use many
$(subdir-m) is a list of directories that should be entered GNU extensions.
for making modules.
$(subdir-n) and $(subdir-) are only used for collecting a list
of all subdirectories of this directory.
Each list besides subdir-y may contain duplicates items; duplicates GNU Make supports elementary list-processing functions. The kernel
are automatically removed later. Makefiles use a novel style of list building and manipulation with few
"if" statements.
mod-subdirs GNU Make has two assignment operators, ":=" and "=". ":=" performs
immediate evaluation of the right-hand side and stores an actual string
into the left-hand side. "=" is like a formula definition; it stores the
right-hand side in an unevaluated form and then evaluates this form each
time the left-hand side is used.
$(mod-subdirs) is a list of all the subdirectories that should There are some cases where "=" is appropriate. Usually, though, ":="
be added to $(subdir-m), too if they appear in $(subdir-y) is the right choice.
Example: === 9 Credits
# fs/Makefile Original version made by Michael Elizabeth Chastain, <mailto:mec@shout.net>
mod-subdirs := nls Updates by Kai Germaschewski <kai@tp1.ruhr-uni-bochum.de>
Updates by Sam Ravnborg <sam@ravnborg.org>
This means nls should be added to (subdir-y) and $(subdir-m) if === 10 TODO
CONFIG_NFS = y.
=== 9 Credits - Describe how kbuild support shipped files with _shipped.
- Generating offset header files.
- Add more variables to section 7?
Thanks to the members of the linux-kbuild mailing list for reviewing
drafts of this document, with particular thanks to Peter Samuelson
and Thomas Molina.
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