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Commit 098fde11 authored by chas williams - CONTRACTOR's avatar chas williams - CONTRACTOR Committed by David S. Miller
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atm: [nicstar] reformatted with Lindent 

Signed-off-by: default avatarChas Williams - CONTRACTOR <chas@cmf.nrl.navy.mil>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 741a00be
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drivers/atm/nicstar.c
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drivers/atm/nicstar.h
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drivers/atm/nicstarmac.c
View file @ 098fde11
...@@ -13,15 +13,15 @@ typedef void __iomem *virt_addr_t; ...@@ -13,15 +13,15 @@ typedef void __iomem *virt_addr_t;
#define CYCLE_DELAY 5 #define CYCLE_DELAY 5
/* This was the original definition /*
This was the original definition
#define osp_MicroDelay(microsec) \ #define osp_MicroDelay(microsec) \
do { int _i = 4*microsec; while (--_i > 0) { __SLOW_DOWN_IO; }} while (0) do { int _i = 4*microsec; while (--_i > 0) { __SLOW_DOWN_IO; }} while (0)
*/ */
#define osp_MicroDelay(microsec) {unsigned long useconds = (microsec); \ #define osp_MicroDelay(microsec) {unsigned long useconds = (microsec); \
udelay((useconds));} udelay((useconds));}
/*
* The following tables represent the timing diagrams found in
/* The following tables represent the timing diagrams found in
* the Data Sheet for the Xicor X25020 EEProm. The #defines below * the Data Sheet for the Xicor X25020 EEProm. The #defines below
* represent the bits in the NICStAR's General Purpose register * represent the bits in the NICStAR's General Purpose register
* that must be toggled for the corresponding actions on the EEProm * that must be toggled for the corresponding actions on the EEProm
...@@ -32,7 +32,7 @@ typedef void __iomem *virt_addr_t; ...@@ -32,7 +32,7 @@ typedef void __iomem *virt_addr_t;
/* Read Data From EEProm on falling edge of CLK */ /* Read Data From EEProm on falling edge of CLK */
#define CS_HIGH 0x0002 /* Chip select high */ #define CS_HIGH 0x0002 /* Chip select high */
#define CS_LOW 0x0000 /* Chip select low (active low)*/ #define CS_LOW 0x0000 /* Chip select low (active low) */
#define CLK_HIGH 0x0004 /* Clock high */ #define CLK_HIGH 0x0004 /* Clock high */
#define CLK_LOW 0x0000 /* Clock low */ #define CLK_LOW 0x0000 /* Clock low */
#define SI_HIGH 0x0001 /* Serial input data high */ #define SI_HIGH 0x0001 /* Serial input data high */
...@@ -40,8 +40,7 @@ typedef void __iomem *virt_addr_t; ...@@ -40,8 +40,7 @@ typedef void __iomem *virt_addr_t;
/* Read Status Register = 0000 0101b */ /* Read Status Register = 0000 0101b */
#if 0 #if 0
static u_int32_t rdsrtab[] = static u_int32_t rdsrtab[] = {
{
CS_HIGH | CLK_HIGH, CS_HIGH | CLK_HIGH,
CS_LOW | CLK_LOW, CS_LOW | CLK_LOW,
CLK_HIGH, /* 0 */ CLK_HIGH, /* 0 */
...@@ -62,10 +61,8 @@ static u_int32_t rdsrtab[] = ...@@ -62,10 +61,8 @@ static u_int32_t rdsrtab[] =
}; };
#endif /* 0 */ #endif /* 0 */
/* Read from EEPROM = 0000 0011b */ /* Read from EEPROM = 0000 0011b */
static u_int32_t readtab[] = static u_int32_t readtab[] = {
{
/* /*
CS_HIGH | CLK_HIGH, CS_HIGH | CLK_HIGH,
*/ */
...@@ -87,10 +84,8 @@ static u_int32_t readtab[] = ...@@ -87,10 +84,8 @@ static u_int32_t readtab[] =
CLK_HIGH | SI_HIGH /* 1 */ CLK_HIGH | SI_HIGH /* 1 */
}; };
/* Clock to read from/write to the eeprom */ /* Clock to read from/write to the eeprom */
static u_int32_t clocktab[] = static u_int32_t clocktab[] = {
{
CLK_LOW, CLK_LOW,
CLK_HIGH, CLK_HIGH,
CLK_LOW, CLK_LOW,
...@@ -110,7 +105,6 @@ static u_int32_t clocktab[] = ...@@ -110,7 +105,6 @@ static u_int32_t clocktab[] =
CLK_LOW CLK_LOW
}; };
#define NICSTAR_REG_WRITE(bs, reg, val) \ #define NICSTAR_REG_WRITE(bs, reg, val) \
while ( readl(bs + STAT) & 0x0200 ) ; \ while ( readl(bs + STAT) & 0x0200 ) ; \
writel((val),(base)+(reg)) writel((val),(base)+(reg))
...@@ -124,101 +118,92 @@ static u_int32_t clocktab[] = ...@@ -124,101 +118,92 @@ static u_int32_t clocktab[] =
* register. * register.
*/ */
#if 0 #if 0
u_int32_t u_int32_t nicstar_read_eprom_status(virt_addr_t base)
nicstar_read_eprom_status( virt_addr_t base )
{ {
u_int32_t val; u_int32_t val;
u_int32_t rbyte; u_int32_t rbyte;
int32_t i, j; int32_t i, j;
/* Send read instruction */ /* Send read instruction */
val = NICSTAR_REG_READ( base, NICSTAR_REG_GENERAL_PURPOSE ) & 0xFFFFFFF0; val = NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE) & 0xFFFFFFF0;
for (i=0; i<ARRAY_SIZE(rdsrtab); i++) for (i = 0; i < ARRAY_SIZE(rdsrtab); i++) {
{ NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
NICSTAR_REG_WRITE( base, NICSTAR_REG_GENERAL_PURPOSE, (val | rdsrtab[i]));
(val | rdsrtab[i]) ); osp_MicroDelay(CYCLE_DELAY);
osp_MicroDelay( CYCLE_DELAY );
} }
/* Done sending instruction - now pull data off of bit 16, MSB first */ /* Done sending instruction - now pull data off of bit 16, MSB first */
/* Data clocked out of eeprom on falling edge of clock */ /* Data clocked out of eeprom on falling edge of clock */
rbyte = 0; rbyte = 0;
for (i=7, j=0; i>=0; i--) for (i = 7, j = 0; i >= 0; i--) {
{ NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
NICSTAR_REG_WRITE( base, NICSTAR_REG_GENERAL_PURPOSE, (val | clocktab[j++]));
(val | clocktab[j++]) ); rbyte |= (((NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE)
rbyte |= (((NICSTAR_REG_READ( base, NICSTAR_REG_GENERAL_PURPOSE)
& 0x00010000) >> 16) << i); & 0x00010000) >> 16) << i);
NICSTAR_REG_WRITE( base, NICSTAR_REG_GENERAL_PURPOSE, NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
(val | clocktab[j++]) ); (val | clocktab[j++]));
osp_MicroDelay( CYCLE_DELAY ); osp_MicroDelay(CYCLE_DELAY);
} }
NICSTAR_REG_WRITE( base, NICSTAR_REG_GENERAL_PURPOSE, 2 ); NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, 2);
osp_MicroDelay( CYCLE_DELAY ); osp_MicroDelay(CYCLE_DELAY);
return rbyte; return rbyte;
} }
#endif /* 0 */ #endif /* 0 */
/* /*
* This routine will clock the Read_data function into the X2520 * This routine will clock the Read_data function into the X2520
* eeprom, followed by the address to read from, through the NicSTaR's General * eeprom, followed by the address to read from, through the NicSTaR's General
* Purpose register. * Purpose register.
*/ */
static u_int8_t static u_int8_t read_eprom_byte(virt_addr_t base, u_int8_t offset)
read_eprom_byte(virt_addr_t base, u_int8_t offset)
{ {
u_int32_t val = 0; u_int32_t val = 0;
int i,j=0; int i, j = 0;
u_int8_t tempread = 0; u_int8_t tempread = 0;
val = NICSTAR_REG_READ( base, NICSTAR_REG_GENERAL_PURPOSE ) & 0xFFFFFFF0; val = NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE) & 0xFFFFFFF0;
/* Send READ instruction */ /* Send READ instruction */
for (i=0; i<ARRAY_SIZE(readtab); i++) for (i = 0; i < ARRAY_SIZE(readtab); i++) {
{ NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
NICSTAR_REG_WRITE( base, NICSTAR_REG_GENERAL_PURPOSE, (val | readtab[i]));
(val | readtab[i]) ); osp_MicroDelay(CYCLE_DELAY);
osp_MicroDelay( CYCLE_DELAY );
} }
/* Next, we need to send the byte address to read from */ /* Next, we need to send the byte address to read from */
for (i=7; i>=0; i--) for (i = 7; i >= 0; i--) {
{ NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
NICSTAR_REG_WRITE( base, NICSTAR_REG_GENERAL_PURPOSE, (val | clocktab[j++] | ((offset >> i) & 1)));
(val | clocktab[j++] | ((offset >> i) & 1) ) ); osp_MicroDelay(CYCLE_DELAY);
NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
(val | clocktab[j++] | ((offset >> i) & 1)));
osp_MicroDelay(CYCLE_DELAY); osp_MicroDelay(CYCLE_DELAY);
NICSTAR_REG_WRITE( base, NICSTAR_REG_GENERAL_PURPOSE,
(val | clocktab[j++] | ((offset >> i) & 1) ) );
osp_MicroDelay( CYCLE_DELAY );
} }
j = 0; j = 0;
/* Now, we can read data from the eeprom by clocking it in */ /* Now, we can read data from the eeprom by clocking it in */
for (i=7; i>=0; i--) for (i = 7; i >= 0; i--) {
{ NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
NICSTAR_REG_WRITE( base, NICSTAR_REG_GENERAL_PURPOSE, (val | clocktab[j++]));
(val | clocktab[j++]) ); osp_MicroDelay(CYCLE_DELAY);
osp_MicroDelay( CYCLE_DELAY ); tempread |=
tempread |= (((NICSTAR_REG_READ( base, NICSTAR_REG_GENERAL_PURPOSE ) (((NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE)
& 0x00010000) >> 16) << i); & 0x00010000) >> 16) << i);
NICSTAR_REG_WRITE( base, NICSTAR_REG_GENERAL_PURPOSE, NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
(val | clocktab[j++]) ); (val | clocktab[j++]));
osp_MicroDelay( CYCLE_DELAY ); osp_MicroDelay(CYCLE_DELAY);
} }
NICSTAR_REG_WRITE( base, NICSTAR_REG_GENERAL_PURPOSE, 2 ); NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, 2);
osp_MicroDelay( CYCLE_DELAY ); osp_MicroDelay(CYCLE_DELAY);
return tempread; return tempread;
} }
static void nicstar_init_eprom(virt_addr_t base)
static void
nicstar_init_eprom( virt_addr_t base )
{ {
u_int32_t val; u_int32_t val;
...@@ -229,48 +214,35 @@ nicstar_init_eprom( virt_addr_t base ) ...@@ -229,48 +214,35 @@ nicstar_init_eprom( virt_addr_t base )
NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
(val | CS_HIGH | CLK_HIGH)); (val | CS_HIGH | CLK_HIGH));
osp_MicroDelay( CYCLE_DELAY ); osp_MicroDelay(CYCLE_DELAY);
NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
(val | CS_HIGH | CLK_LOW)); (val | CS_HIGH | CLK_LOW));
osp_MicroDelay( CYCLE_DELAY ); osp_MicroDelay(CYCLE_DELAY);
NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
(val | CS_HIGH | CLK_HIGH)); (val | CS_HIGH | CLK_HIGH));
osp_MicroDelay( CYCLE_DELAY ); osp_MicroDelay(CYCLE_DELAY);
NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
(val | CS_HIGH | CLK_LOW)); (val | CS_HIGH | CLK_LOW));
osp_MicroDelay( CYCLE_DELAY ); osp_MicroDelay(CYCLE_DELAY);
} }
/* /*
* This routine will be the interface to the ReadPromByte function * This routine will be the interface to the ReadPromByte function
* above. * above.
*/ */
static void static void
nicstar_read_eprom( nicstar_read_eprom(virt_addr_t base,
virt_addr_t base, u_int8_t prom_offset, u_int8_t * buffer, u_int32_t nbytes)
u_int8_t prom_offset,
u_int8_t *buffer,
u_int32_t nbytes )
{ {
u_int i; u_int i;
for (i=0; i<nbytes; i++) for (i = 0; i < nbytes; i++) {
{ buffer[i] = read_eprom_byte(base, prom_offset);
buffer[i] = read_eprom_byte( base, prom_offset );
++prom_offset; ++prom_offset;
osp_MicroDelay( CYCLE_DELAY ); osp_MicroDelay(CYCLE_DELAY);
} }
} }
/*
void osp_MicroDelay(int x) {
}
*/
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