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Commit 09a31a7e authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'mips_5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux 

Pull MIPS updates from Thomas Bogendoerfer:

 - removed support for PNX833x alias NXT_STB22x

 - included Ingenic SoC support into generic MIPS kernels

 - added support for new Ingenic SoCs

 - converted workaround selection to use Kconfig

 - replaced old boot mem functions by memblock_*

 - enabled COP2 usage in kernel for Loongson64 to make use
   of 16byte load/stores possible

 - cleanups and fixes

* tag 'mips_5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (92 commits)
  MIPS: DEC: Restore bootmem reservation for firmware working memory area
  MIPS: dec: fix section mismatch
  bcm963xx_tag.h: fix duplicated word
  mips: ralink: enable zboot support
  MIPS: ingenic: Remove CPU_SUPPORTS_HUGEPAGES
  MIPS: cpu-probe: remove MIPS_CPU_BP_GHIST option bit
  MIPS: cpu-probe: introduce exclusive R3k CPU probe
  MIPS: cpu-probe: move fpu probing/handling into its own file
  MIPS: replace add_memory_region with memblock
  MIPS: Loongson64: Clean up numa.c
  MIPS: Loongson64: Select SMP in Kconfig to avoid build error
  mips: octeon: Add Ubiquiti E200 and E220 boards
  MIPS: SGI-IP28: disable use of ll/sc in kernel
  MIPS: tx49xx: move tx4939_add_memory_regions into only user
  MIPS: pgtable: Remove used PAGE_USERIO define
  MIPS: alchemy: Share prom_init implementation
  MIPS: alchemy: Fix build breakage, if TOUCHSCREEN_WM97XX is disabled
  MIPS: process: include exec.h header in process.c
  MIPS: process: Add prototype for function arch_dup_task_struct
  MIPS: idle: Add prototype for function check_wait
  ...
parents 847d4287 cf3af0a4
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Documentation/devicetree/bindings/mips/ingenic/devices.yaml
View file @ 09a31a7e
......@@ -47,4 +47,9 @@ properties:
items:
- const: yna,cu1830-neo
- const: ingenic,x1830
- description: YSH & ATIL General Board, CU2000 Module with Neo Backplane
items:
- const: yna,cu2000-neo
- const: ingenic,x2000e
...
MAINTAINERS
View file @ 09a31a7e
......@@ -8675,8 +8675,9 @@ INGENIC JZ47xx SoCs
M: Paul Cercueil <paul@crapouillou.net>
S: Maintained
F: arch/mips/boot/dts/ingenic/
F: arch/mips/include/asm/mach-jz4740/
F: arch/mips/jz4740/
F: arch/mips/generic/board-ingenic.c
F: arch/mips/include/asm/mach-ingenic/
F: arch/mips/ingenic/Kconfig
F: drivers/clk/ingenic/
F: drivers/dma/dma-jz4780.c
F: drivers/gpu/drm/ingenic/
......
arch/mips/Kbuild.platforms
View file @ 09a31a7e
......@@ -13,7 +13,6 @@ platform-$(CONFIG_MIPS_COBALT) += cobalt/
platform-$(CONFIG_MACH_DECSTATION) += dec/
platform-$(CONFIG_MIPS_GENERIC) += generic/
platform-$(CONFIG_MACH_JAZZ) += jazz/
platform-$(CONFIG_MACH_INGENIC) += jz4740/
platform-$(CONFIG_LANTIQ) += lantiq/
platform-$(CONFIG_MACH_LOONGSON2EF) += loongson2ef/
platform-$(CONFIG_MACH_LOONGSON32) += loongson32/
......@@ -22,7 +21,6 @@ platform-$(CONFIG_MIPS_MALTA) += mti-malta/
platform-$(CONFIG_NLM_COMMON) += netlogic/
platform-$(CONFIG_PIC32MZDA) += pic32/
platform-$(CONFIG_MACH_PISTACHIO) += pistachio/
platform-$(CONFIG_SOC_PNX833X) += pnx833x/
platform-$(CONFIG_RALINK) += ralink/
platform-$(CONFIG_MIKROTIK_RB532) += rb532/
platform-$(CONFIG_SGI_IP22) += sgi-ip22/
......
arch/mips/Kconfig
View file @ 09a31a7e
......@@ -94,14 +94,34 @@ config MIPS
config MIPS_FIXUP_BIGPHYS_ADDR
bool
config MIPS_GENERIC
bool
config MACH_INGENIC
bool
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_ZBOOT
select DMA_NONCOHERENT
select IRQ_MIPS_CPU
select PINCTRL
select GPIOLIB
select COMMON_CLK
select GENERIC_IRQ_CHIP
select BUILTIN_DTB if MIPS_NO_APPENDED_DTB
select USE_OF
select CPU_SUPPORTS_CPUFREQ
select MIPS_EXTERNAL_TIMER
menu "Machine selection"
choice
prompt "System type"
default MIPS_GENERIC
default MIPS_GENERIC_KERNEL
config MIPS_GENERIC
config MIPS_GENERIC_KERNEL
bool "Generic board-agnostic MIPS kernel"
select MIPS_GENERIC
select BOOT_RAW
select BUILTIN_DTB
select CEVT_R4K
......@@ -138,6 +158,7 @@ config MIPS_GENERIC
select SYS_SUPPORTS_MULTITHREADING
select SYS_SUPPORTS_RELOCATABLE
select SYS_SUPPORTS_SMARTMIPS
select SYS_SUPPORTS_ZBOOT
select UHI_BOOT
select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
......@@ -390,20 +411,11 @@ config MACH_JAZZ
Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
Olivetti M700-10 workstations.
config MACH_INGENIC
config MACH_INGENIC_SOC
bool "Ingenic SoC based machines"
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_LITTLE_ENDIAN
select MIPS_GENERIC
select MACH_INGENIC
select SYS_SUPPORTS_ZBOOT_UART16550
select CPU_SUPPORTS_HUGEPAGES
select DMA_NONCOHERENT
select IRQ_MIPS_CPU
select PINCTRL
select GPIOLIB
select COMMON_CLK
select GENERIC_IRQ_CHIP
select BUILTIN_DTB if MIPS_NO_APPENDED_DTB
select USE_OF
config LANTIQ
bool "Lantiq based platforms"
......@@ -476,6 +488,7 @@ config MACH_LOONGSON64
select SYS_SUPPORTS_ZBOOT
select ZONE_DMA32
select NUMA
select SMP
select COMMON_CLK
select USE_OF
select BUILTIN_DTB
......@@ -569,6 +582,7 @@ config MIPS_MALTA
select SYS_SUPPORTS_VPE_LOADER
select SYS_SUPPORTS_ZBOOT
select USE_OF
select WAR_ICACHE_REFILLS
select ZONE_DMA32 if 64BIT
help
This enables support for the MIPS Technologies Malta evaluation
......@@ -590,19 +604,6 @@ config MACH_VR41XX
select SYS_SUPPORTS_MIPS16
select GPIOLIB
config NXP_STB220
bool "NXP STB220 board"
select SOC_PNX833X
help
Support for NXP Semiconductors STB220 Development Board.
config NXP_STB225
bool "NXP 225 board"
select SOC_PNX833X
select SOC_PNX8335
help
Support for NXP Semiconductors STB225 Development Board.
config RALINK
bool "Ralink based machines"
select CEVT_R4K
......@@ -616,6 +617,7 @@ config RALINK
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_MIPS16
select SYS_SUPPORTS_ZBOOT
select SYS_HAS_EARLY_PRINTK
select CLKDEV_LOOKUP
select ARCH_HAS_RESET_CONTROLLER
......@@ -652,6 +654,9 @@ config SGI_IP22
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
select WAR_R4600_V1_INDEX_ICACHEOP
select WAR_R4600_V1_HIT_CACHEOP
select WAR_R4600_V2_HIT_CACHEOP
select MIPS_L1_CACHE_SHIFT_7
help
This are the SGI Indy, Challenge S and Indigo2, as well as certain
......@@ -679,6 +684,7 @@ config SGI_IP27
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_NUMA
select SYS_SUPPORTS_SMP
select WAR_R10000_LLSC
select MIPS_L1_CACHE_SHIFT_7
select NUMA
help
......@@ -714,6 +720,7 @@ config SGI_IP28
select SYS_HAS_EARLY_PRINTK
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
select WAR_R10000_LLSC
select MIPS_L1_CACHE_SHIFT_7
help
This is the SGI Indigo2 with R10000 processor. To compile a Linux
......@@ -740,6 +747,7 @@ config SGI_IP30
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_SMP
select WAR_R10000_LLSC
select MIPS_L1_CACHE_SHIFT_7
select ARC_MEMORY
help
......@@ -767,6 +775,7 @@ config SGI_IP32
select SYS_HAS_CPU_NEVADA
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
select WAR_ICACHE_REFILLS
help
If you want this kernel to run on SGI O2 workstation, say Y here.
......@@ -890,6 +899,7 @@ config SNI_RM
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_HIGHMEM
select SYS_SUPPORTS_LITTLE_ENDIAN
select WAR_R4600_V2_HIT_CACHEOP
help
The SNI RM200/300/400 are MIPS-based machines manufactured by
Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
......@@ -901,6 +911,7 @@ config MACH_TX39XX
config MACH_TX49XX
bool "Toshiba TX49 series based machines"
select WAR_TX49XX_ICACHE_INDEX_INV
config MIKROTIK_RB532
bool "Mikrotik RB532 boards"
......@@ -1026,8 +1037,8 @@ source "arch/mips/bcm47xx/Kconfig"
source "arch/mips/bcm63xx/Kconfig"
source "arch/mips/bmips/Kconfig"
source "arch/mips/generic/Kconfig"
source "arch/mips/ingenic/Kconfig"
source "arch/mips/jazz/Kconfig"
source "arch/mips/jz4740/Kconfig"
source "arch/mips/lantiq/Kconfig"
source "arch/mips/pic32/Kconfig"
source "arch/mips/pistachio/Kconfig"
......@@ -1267,23 +1278,6 @@ config PCI_XTALK_BRIDGE
config NO_EXCEPT_FILL
bool
config SOC_PNX833X
bool
select CEVT_R4K
select CSRC_R4K
select IRQ_MIPS_CPU
select DMA_NONCOHERENT
select SYS_HAS_CPU_MIPS32_R2
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_MIPS16
select CPU_MIPSR2_IRQ_VI
config SOC_PNX8335
bool
select SOC_PNX833X
config MIPS_SPRAM
bool
......@@ -1620,7 +1614,6 @@ config CPU_P5600
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM
select CPU_SUPPORTS_MSA
select CPU_SUPPORTS_UNCACHED_ACCELERATED
select CPU_SUPPORTS_CPUFREQ
select CPU_MIPSR2_IRQ_VI
select CPU_MIPSR2_IRQ_EI
......@@ -1891,6 +1884,7 @@ config SYS_SUPPORTS_ZBOOT
select HAVE_KERNEL_LZMA
select HAVE_KERNEL_LZO
select HAVE_KERNEL_XZ
select HAVE_KERNEL_ZSTD
config SYS_SUPPORTS_ZBOOT_UART16550
bool
......@@ -2272,7 +2266,7 @@ config FORCE_MAX_ZONEORDER
default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
range 12 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
range 11 64
range 0 64
default "11"
help
The kernel memory allocator divides physically contiguous memory
......@@ -2638,6 +2632,76 @@ config MIPS_ASID_BITS_VARIABLE
config MIPS_CRC_SUPPORT
bool
# R4600 erratum. Due to the lack of errata information the exact
# technical details aren't known. I've experimentally found that disabling
# interrupts during indexed I-cache flushes seems to be sufficient to deal
# with the issue.
config WAR_R4600_V1_INDEX_ICACHEOP
bool
# Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata:
#
# 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
# Hit_Invalidate_D and Create_Dirty_Excl_D should only be
# executed if there is no other dcache activity. If the dcache is
# accessed for another instruction immeidately preceding when these
# cache instructions are executing, it is possible that the dcache
# tag match outputs used by these cache instructions will be
# incorrect. These cache instructions should be preceded by at least
# four instructions that are not any kind of load or store
# instruction.
#
# This is not allowed: lw
# nop
# nop
# nop
# cache Hit_Writeback_Invalidate_D
#
# This is allowed: lw
# nop
# nop
# nop
# nop
# cache Hit_Writeback_Invalidate_D
config WAR_R4600_V1_HIT_CACHEOP
bool
# Writeback and invalidate the primary cache dcache before DMA.
#
# R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
# Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
# operate correctly if the internal data cache refill buffer is empty. These
# CACHE instructions should be separated from any potential data cache miss
# by a load instruction to an uncached address to empty the response buffer."
# (Revision 2.0 device errata from IDT available on https://www.idt.com/
# in .pdf format.)
config WAR_R4600_V2_HIT_CACHEOP
bool
# From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
# the line which this instruction itself exists, the following
# operation is not guaranteed."
#
# Workaround: do two phase flushing for Index_Invalidate_I
config WAR_TX49XX_ICACHE_INDEX_INV
bool
# The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
# opposes it being called that) where invalid instructions in the same
# I-cache line worth of instructions being fetched may case spurious
# exceptions.
config WAR_ICACHE_REFILLS
bool
# On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that
# may cause ll / sc and lld / scd sequences to execute non-atomically.
config WAR_R10000_LLSC
bool
# 34K core erratum: "Problems Executing the TLBR Instruction"
config WAR_MIPS34K_MISSED_ITLB
bool
#
# - Highmem only makes sense for the 32-bit kernel.
# - The current highmem code will only work properly on physically indexed
......
arch/mips/alchemy/Kconfig
View file @ 09a31a7e
# SPDX-License-Identifier: GPL-2.0
# au1000-style gpio and interrupt controllers
config ALCHEMY_GPIOINT_AU1000
bool
# au1300-style GPIO/INT controller
config ALCHEMY_GPIOINT_AU1300
bool
choice
prompt "Machine type"
depends on MIPS_ALCHEMY
......@@ -15,7 +7,6 @@ choice
config MIPS_MTX1
bool "4G Systems MTX-1 board"
select HAVE_PCI
select ALCHEMY_GPIOINT_AU1000
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_HAS_EARLY_PRINTK
......@@ -33,13 +24,11 @@ config MIPS_DB1XXX
config MIPS_XXS1500
bool "MyCable XXS1500 board"
select ALCHEMY_GPIOINT_AU1000
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_HAS_EARLY_PRINTK
config MIPS_GPR
bool "Trapeze ITS GPR board"
select ALCHEMY_GPIOINT_AU1000
select HAVE_PCI
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_HAS_EARLY_PRINTK
......
arch/mips/alchemy/board-gpr.c
View file @ 09a31a7e
......@@ -31,23 +31,6 @@ const char *get_system_type(void)
return "GPR";
}
void __init prom_init(void)
{
unsigned char *memsize_str;
unsigned long memsize;
prom_argc = fw_arg0;
prom_argv = (char **)fw_arg1;
prom_envp = (char **)fw_arg2;
prom_init_cmdline();
memsize_str = prom_getenv("memsize");
if (!memsize_str || kstrtoul(memsize_str, 0, &memsize))
memsize = 0x04000000;
add_memory_region(0, memsize, BOOT_MEM_RAM);
}
void prom_putchar(char c)
{
alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
......
arch/mips/alchemy/board-mtx1.c
View file @ 09a31a7e
......@@ -30,23 +30,6 @@ const char *get_system_type(void)
return "MTX-1";
}
void __init prom_init(void)
{
unsigned char *memsize_str;
unsigned long memsize;
prom_argc = fw_arg0;
prom_argv = (char **)fw_arg1;
prom_envp = (char **)fw_arg2;
prom_init_cmdline();
memsize_str = prom_getenv("memsize");
if (!memsize_str || kstrtoul(memsize_str, 0, &memsize))
memsize = 0x04000000;
add_memory_region(0, memsize, BOOT_MEM_RAM);
}
void prom_putchar(char c)
{
alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
......
arch/mips/alchemy/board-xxs1500.c
View file @ 09a31a7e
......@@ -25,24 +25,6 @@ const char *get_system_type(void)
return "XXS1500";
}
void __init prom_init(void)
{
unsigned char *memsize_str;
unsigned long memsize;
prom_argc = fw_arg0;
prom_argv = (char **)fw_arg1;
prom_envp = (char **)fw_arg2;
prom_init_cmdline();
memsize_str = prom_getenv("memsize");
if (!memsize_str || kstrtoul(memsize_str, 0, &memsize))
memsize = 0x04000000;
add_memory_region(0, memsize, BOOT_MEM_RAM);
}
void prom_putchar(char c)
{
alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
......
arch/mips/alchemy/common/prom.c
View file @ 09a31a7e
......@@ -34,6 +34,9 @@
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/memblock.h>
#include <linux/sizes.h>
#include <linux/string.h>
#include <asm/bootinfo.h>
......@@ -76,6 +79,24 @@ char *prom_getenv(char *envname)
return NULL;
}
void __init prom_init(void)
{
unsigned char *memsize_str;
unsigned long memsize;
prom_argc = (int)fw_arg0;
prom_argv = (char **)fw_arg1;
prom_envp = (char **)fw_arg2;
prom_init_cmdline();
memsize_str = prom_getenv("memsize");
if (!memsize_str || kstrtoul(memsize_str, 0, &memsize))
memsize = SZ_64M; /* minimum memsize is 64MB RAM */
memblock_add(0, memsize);
}
static inline unsigned char str2hexnum(unsigned char c)
{
if (c >= '0' && c <= '9')
......
arch/mips/alchemy/devboards/db1300.c
View file @ 09a31a7e
......@@ -731,6 +731,7 @@ static struct platform_device db1300_lcd_dev = {
/**********************************************************************/
#if IS_ENABLED(CONFIG_TOUCHSCREEN_WM97XX)
static void db1300_wm97xx_irqen(struct wm97xx *wm, int enable)
{
if (enable)
......@@ -762,6 +763,12 @@ static int db1300_wm97xx_probe(struct platform_device *pdev)
return wm97xx_register_mach_ops(wm, &db1300_wm97xx_ops);
}
#else
static int db1300_wm97xx_probe(struct platform_device *pdev)
{
return -ENODEV;
}
#endif
static struct platform_driver db1300_wm97xx_driver = {
.driver.name = "wm97xx-touch",
......
arch/mips/alchemy/devboards/platform.c
View file @ 09a31a7e
......@@ -20,23 +20,6 @@
#include <prom.h>
void __init prom_init(void)
{
unsigned char *memsize_str;
unsigned long memsize;
prom_argc = (int)fw_arg0;
prom_argv = (char **)fw_arg1;
prom_envp = (char **)fw_arg2;
prom_init_cmdline();
memsize_str = prom_getenv("memsize");
if (!memsize_str || kstrtoul(memsize_str, 0, &memsize))
memsize = 64 << 20; /* all devboards have at least 64MB RAM */
add_memory_region(0, memsize, BOOT_MEM_RAM);
}
void prom_putchar(char c)
{
if (alchemy_get_cputype() == ALCHEMY_CPU_AU1300)
......
arch/mips/ar7/memory.c
View file @ 09a31a7e
......@@ -47,7 +47,7 @@ void __init prom_meminit(void)
unsigned long pages;
pages = memsize() >> PAGE_SHIFT;
add_memory_region(PHYS_OFFSET, pages << PAGE_SHIFT, BOOT_MEM_RAM);
memblock_add(PHYS_OFFSET, pages << PAGE_SHIFT);
}
void __init prom_free_prom_memory(void)
......
arch/mips/ath25/ar2315.c
View file @ 09a31a7e
......@@ -19,6 +19,7 @@
#include <linux/bitops.h>
#include <linux/irqdomain.h>
#include <linux/interrupt.h>
#include <linux/memblock.h>
#include <linux/platform_device.h>
#include <linux/reboot.h>
#include <asm/bootinfo.h>
......@@ -266,7 +267,7 @@ void __init ar2315_plat_mem_setup(void)
memsize <<= 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_COL_WIDTH);
memsize <<= 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_ROW_WIDTH);
memsize <<= 3;
add_memory_region(0, memsize, BOOT_MEM_RAM);
memblock_add(0, memsize);
iounmap(sdram_base);
ar2315_rst_base = ioremap(AR2315_RST_BASE, AR2315_RST_SIZE);
......
arch/mips/ath25/ar5312.c
View file @ 09a31a7e
......@@ -19,6 +19,7 @@
#include <linux/bitops.h>
#include <linux/irqdomain.h>
#include <linux/interrupt.h>
#include <linux/memblock.h>
#include <linux/platform_device.h>
#include <linux/mtd/physmap.h>
#include <linux/reboot.h>
......@@ -363,7 +364,7 @@ void __init ar5312_plat_mem_setup(void)
memsize = (bank0_ac ? (1 << (bank0_ac + 1)) : 0) +
(bank1_ac ? (1 << (bank1_ac + 1)) : 0);
memsize <<= 20;
add_memory_region(0, memsize, BOOT_MEM_RAM);
memblock_add(0, memsize);
iounmap(sdram_base);
ar5312_rst_base = ioremap(AR5312_RST_BASE, AR5312_RST_SIZE);
......
arch/mips/bcm47xx/prom.c
View file @ 09a31a7e
......@@ -27,6 +27,7 @@
#include <linux/init.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/memblock.h>
#include <linux/spinlock.h>
#include <linux/ssb/ssb_driver_chipcommon.h>
#include <linux/ssb/ssb_regs.h>
......@@ -97,7 +98,7 @@ static __init void prom_init_mem(void)
*/
if (c->cputype == CPU_74K && (mem == (128 << 20)))
mem -= 0x1000;
add_memory_region(0, mem, BOOT_MEM_RAM);
memblock_add(0, mem);
}
/*
......
arch/mips/bcm47xx/setup.c
View file @ 09a31a7e
......@@ -141,7 +141,7 @@ static void __init bcm47xx_register_bcma(void)
/*
* Memory setup is done in the early part of MIPS's arch_mem_init. It's supposed
* to detect memory and record it with add_memory_region.
* to detect memory and record it with memblock_add.
* Any extra initializaion performed here must not use kmalloc or bootmem.
*/
void __init plat_mem_setup(void)
......
arch/mips/bcm63xx/boards/board_bcm963xx.c
View file @ 09a31a7e
// SPDX-License-Identifier: GPL-2.0-only
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
* Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
*/
......@@ -32,7 +29,6 @@
#include <uapi/linux/bcm933xx_hcs.h>
#define HCS_OFFSET_128K 0x20000
static struct board_info board;
......@@ -45,12 +41,13 @@ static struct board_info __initdata board_cvg834g = {
.name = "CVG834G_E15R3921",
.expected_cpu_id = 0x3368,
.ephy_reset_gpio = 36,
.ephy_reset_gpio_flags = GPIOF_INIT_HIGH,
.has_pci = 1,
.has_uart0 = 1,
.has_uart1 = 1,
.has_enet0 = 1,
.has_pci = 1,
.enet0 = {
.has_phy = 1,
.use_internal_phy = 1,
......@@ -63,9 +60,6 @@ static struct board_info __initdata board_cvg834g = {
.default_trigger= "default-on",
},
},
.ephy_reset_gpio = 36,
.ephy_reset_gpio_flags = GPIOF_INIT_HIGH,
};
#endif /* CONFIG_BCM63XX_CPU_3368 */
......@@ -77,10 +71,10 @@ static struct board_info __initdata board_96328avng = {
.name = "96328avng",
.expected_cpu_id = 0x6328,
.has_uart0 = 1,
.has_pci = 1,
.has_usbd = 0,
.has_uart0 = 1,
.has_usbd = 0,
.usbd = {
.use_fullspeed = 0,
.port_no = 0,
......@@ -125,15 +119,15 @@ static struct board_info __initdata board_96338gw = {
.name = "96338GW",
.expected_cpu_id = 0x6338,
.has_ohci0 = 1,
.has_uart0 = 1,
.has_enet0 = 1,
.enet0 = {
.force_speed_100 = 1,
.force_duplex_full = 1,
},
.has_ohci0 = 1,
.leds = {
{
.name = "adsl",
......@@ -169,6 +163,7 @@ static struct board_info __initdata board_96338w = {
.expected_cpu_id = 0x6338,
.has_uart0 = 1,
.has_enet0 = 1,
.enet0 = {
.force_speed_100 = 1,
......@@ -226,10 +221,10 @@ static struct board_info __initdata board_96348r = {
.name = "96348R",
.expected_cpu_id = 0x6348,
.has_uart0 = 1,
.has_enet0 = 1,
.has_pci = 1,
.has_uart0 = 1,
.has_enet0 = 1,
.enet0 = {
.has_phy = 1,
.use_internal_phy = 1,
......@@ -270,24 +265,23 @@ static struct board_info __initdata board_96348gw_10 = {
.name = "96348GW-10",
.expected_cpu_id = 0x6348,
.has_uart0 = 1,
.has_enet0 = 1,
.has_enet1 = 1,
.has_ohci0 = 1,
.has_pccard = 1,
.has_pci = 1,
.has_uart0 = 1,
.has_enet0 = 1,
.enet0 = {
.has_phy = 1,
.use_internal_phy = 1,
},
.has_enet1 = 1,
.enet1 = {
.force_speed_100 = 1,
.force_duplex_full = 1,
},
.has_ohci0 = 1,
.has_pccard = 1,
.has_ehci0 = 1,
.leds = {
{
.name = "adsl-fail",
......@@ -322,26 +316,23 @@ static struct board_info __initdata board_96348gw_11 = {
.name = "96348GW-11",
.expected_cpu_id = 0x6348,
.has_uart0 = 1,
.has_enet0 = 1,
.has_enet1 = 1,
.has_ohci0 = 1,
.has_pccard = 1,
.has_pci = 1,
.has_uart0 = 1,
.has_enet0 = 1,
.enet0 = {
.has_phy = 1,
.use_internal_phy = 1,
},
.has_enet1 = 1,
.enet1 = {
.force_speed_100 = 1,
.force_duplex_full = 1,
},
.has_ohci0 = 1,
.has_pccard = 1,
.has_ehci0 = 1,
.leds = {
{
.name = "adsl-fail",
......@@ -376,22 +367,22 @@ static struct board_info __initdata board_96348gw = {
.name = "96348GW",
.expected_cpu_id = 0x6348,
.has_uart0 = 1,
.has_enet0 = 1,
.has_enet1 = 1,
.has_ohci0 = 1,
.has_pci = 1,
.has_uart0 = 1,
.has_enet0 = 1,
.enet0 = {
.has_phy = 1,
.use_internal_phy = 1,
},
.has_enet1 = 1,
.enet1 = {
.force_speed_100 = 1,
.force_duplex_full = 1,
},
.has_ohci0 = 1,
.leds = {
{
.name = "adsl-fail",
......@@ -426,38 +417,37 @@ static struct board_info __initdata board_FAST2404 = {
.name = "F@ST2404",
.expected_cpu_id = 0x6348,
.has_uart0 = 1,
.has_enet0 = 1,
.has_enet1 = 1,
.has_ohci0 = 1,
.has_pccard = 1,
.has_pci = 1,
.has_uart0 = 1,
.has_enet0 = 1,
.enet0 = {
.has_phy = 1,
.use_internal_phy = 1,
},
.has_enet1 = 1,
.enet1 = {
.force_speed_100 = 1,
.force_duplex_full = 1,
},
.has_ohci0 = 1,
.has_pccard = 1,
.has_ehci0 = 1,
};
static struct board_info __initdata board_rta1025w_16 = {
.name = "RTA1025W_16",
.expected_cpu_id = 0x6348,
.has_enet0 = 1,
.has_enet1 = 1,
.has_pci = 1,
.has_enet0 = 1,
.enet0 = {
.has_phy = 1,
.use_internal_phy = 1,
},
.has_enet1 = 1,
.enet1 = {
.force_speed_100 = 1,
.force_duplex_full = 1,
......@@ -468,16 +458,17 @@ static struct board_info __initdata board_DV201AMR = {
.name = "DV201AMR",
.expected_cpu_id = 0x6348,
.has_uart0 = 1,
.has_pci = 1,
.has_ohci0 = 1,
.has_pci = 1,
.has_uart0 = 1,
.has_enet0 = 1,
.has_enet1 = 1,
.enet0 = {
.has_phy = 1,
.use_internal_phy = 1,
},
.has_enet1 = 1,
.enet1 = {
.force_speed_100 = 1,
.force_duplex_full = 1,
......@@ -488,21 +479,21 @@ static struct board_info __initdata board_96348gw_a = {
.name = "96348GW-A",
.expected_cpu_id = 0x6348,
.has_uart0 = 1,
.has_enet0 = 1,
.has_enet1 = 1,
.has_ohci0 = 1,
.has_pci = 1,
.has_uart0 = 1,
.has_enet0 = 1,
.enet0 = {
.has_phy = 1,
.use_internal_phy = 1,
},
.has_enet1 = 1,
.enet1 = {
.force_speed_100 = 1,
.force_duplex_full = 1,
},
.has_ohci0 = 1,
};
#endif /* CONFIG_BCM63XX_CPU_6348 */
......@@ -514,25 +505,24 @@ static struct board_info __initdata board_96358vw = {
.name = "96358VW",
.expected_cpu_id = 0x6358,
.has_uart0 = 1,
.has_enet0 = 1,
.has_enet1 = 1,
.has_ehci0 = 1,
.has_ohci0 = 1,
.has_pccard = 1,
.has_pci = 1,
.has_uart0 = 1,
.has_enet0 = 1,
.enet0 = {
.has_phy = 1,
.use_internal_phy = 1,
},
.has_enet1 = 1,
.enet1 = {
.force_speed_100 = 1,
.force_duplex_full = 1,
},
.has_ohci0 = 1,
.has_pccard = 1,
.has_ehci0 = 1,
.leds = {
{
.name = "adsl-fail",
......@@ -565,26 +555,24 @@ static struct board_info __initdata board_96358vw2 = {
.name = "96358VW2",
.expected_cpu_id = 0x6358,
.has_uart0 = 1,
.has_enet0 = 1,
.has_enet1 = 1,
.has_ehci0 = 1,
.has_ohci0 = 1,
.has_pccard = 1,
.has_pci = 1,
.has_uart0 = 1,
.has_enet0 = 1,
.enet0 = {
.has_phy = 1,
.use_internal_phy = 1,
},
.has_enet1 = 1,
.enet1 = {
.force_speed_100 = 1,
.force_duplex_full = 1,
},
.has_ohci0 = 1,
.has_pccard = 1,
.has_ehci0 = 1,
.leds = {
{
.name = "adsl",
......@@ -613,44 +601,43 @@ static struct board_info __initdata board_AGPFS0 = {
.name = "AGPF-S0",
.expected_cpu_id = 0x6358,
.has_uart0 = 1,
.has_enet0 = 1,
.has_enet1 = 1,
.has_ehci0 = 1,
.has_ohci0 = 1,
.has_pci = 1,
.has_uart0 = 1,
.has_enet0 = 1,
.enet0 = {
.has_phy = 1,
.use_internal_phy = 1,
},
.has_enet1 = 1,
.enet1 = {
.force_speed_100 = 1,
.force_duplex_full = 1,
},
.has_ohci0 = 1,
.has_ehci0 = 1,
};
static struct board_info __initdata board_DWVS0 = {
.name = "DWV-S0",
.expected_cpu_id = 0x6358,
.has_enet0 = 1,
.has_enet1 = 1,
.has_ehci0 = 1,
.has_ohci0 = 1,
.has_pci = 1,
.has_enet0 = 1,
.enet0 = {
.has_phy = 1,
.use_internal_phy = 1,
},
.has_enet1 = 1,
.enet1 = {
.force_speed_100 = 1,
.force_duplex_full = 1,
},
.has_ohci0 = 1,
};
#endif /* CONFIG_BCM63XX_CPU_6358 */
......
arch/mips/bcm63xx/setup.c
View file @ 09a31a7e
......@@ -146,7 +146,7 @@ void __init plat_time_init(void)
void __init plat_mem_setup(void)
{
add_memory_region(0, bcm63xx_get_memory_size(), BOOT_MEM_RAM);
memblock_add(0, bcm63xx_get_memory_size());
_machine_halt = bcm63xx_machine_halt;
_machine_restart = __bcm63xx_machine_reboot;
......
arch/mips/boot/compressed/Makefile
View file @ 09a31a7e
......@@ -22,7 +22,12 @@ KBUILD_CFLAGS := $(filter-out -pg, $(KBUILD_CFLAGS))
KBUILD_CFLAGS := $(filter-out -fstack-protector, $(KBUILD_CFLAGS))
KBUILD_CFLAGS := $(KBUILD_CFLAGS) -D__KERNEL__ \
# Disable lq/sq in zboot
ifdef CONFIG_CPU_LOONGSON64
KBUILD_CFLAGS := $(filter-out -march=loongson3a, $(KBUILD_CFLAGS)) -march=mips64r2
endif
KBUILD_CFLAGS := $(KBUILD_CFLAGS) -D__KERNEL__ -D__DISABLE_EXPORTS \
-DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE) -D"VMLINUX_LOAD_ADDRESS_ULL=$(VMLINUX_LOAD_ADDRESS)ull"
KBUILD_AFLAGS := $(KBUILD_AFLAGS) -D__ASSEMBLY__ \
......@@ -70,6 +75,7 @@ tool_$(CONFIG_KERNEL_LZ4) = lz4
tool_$(CONFIG_KERNEL_LZMA) = lzma
tool_$(CONFIG_KERNEL_LZO) = lzo
tool_$(CONFIG_KERNEL_XZ) = xzkern
tool_$(CONFIG_KERNEL_ZSTD) = zstd22
targets += vmlinux.bin.z
$(obj)/vmlinux.bin.z: $(obj)/vmlinux.bin FORCE
......
arch/mips/boot/compressed/decompress.c
View file @ 09a31a7e
......@@ -72,6 +72,10 @@ void error(char *x)
#include "../../../../lib/decompress_unxz.c"
#endif
#ifdef CONFIG_KERNEL_ZSTD
#include "../../../../lib/decompress_unzstd.c"
#endif
const unsigned long __stack_chk_guard = 0x000a0dff;
void __stack_chk_fail(void)
......
arch/mips/boot/compressed/string.c
View file @ 09a31a7e
......@@ -5,6 +5,7 @@
* Very small subset of simple string routines
*/
#include <linux/compiler_attributes.h>
#include <linux/types.h>
void *memcpy(void *dest, const void *src, size_t n)
......@@ -27,3 +28,19 @@ void *memset(void *s, int c, size_t n)
ss[i] = c;
return s;
}
void * __weak memmove(void *dest, const void *src, size_t n)
{
unsigned int i;
const char *s = src;
char *d = dest;
if ((uintptr_t)dest < (uintptr_t)src) {
for (i = 0; i < n; i++)
d[i] = s[i];
} else {
for (i = n; i > 0; i--)
d[i - 1] = s[i - 1];
}
return dest;
}
arch/mips/boot/dts/ingenic/jz4725b.dtsi
View file @ 09a31a7e
......@@ -7,6 +7,20 @@ / {
#size-cells = <1>;
compatible = "ingenic,jz4725b";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "ingenic,xburst-mxu1.0";
reg = <0>;
clocks = <&cgu JZ4725B_CLK_CCLK>;
clock-names = "cpu";
};
};
cpuintc: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
......
arch/mips/boot/dts/ingenic/jz4740.dtsi
View file @ 09a31a7e
......@@ -7,6 +7,20 @@ / {
#size-cells = <1>;
compatible = "ingenic,jz4740";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "ingenic,xburst-mxu1.0";
reg = <0>;
clocks = <&cgu JZ4740_CLK_CCLK>;
clock-names = "cpu";
};
};
cpuintc: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
......
arch/mips/boot/dts/ingenic/jz4770.dtsi
View file @ 09a31a7e
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/clock/jz4770-cgu.h>
#include <dt-bindings/clock/ingenic,tcu.h>
......@@ -8,6 +7,20 @@ / {
#size-cells = <1>;
compatible = "ingenic,jz4770";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "ingenic,xburst-fpu1.0-mxu1.1";
reg = <0>;
clocks = <&cgu JZ4770_CLK_CCLK>;
clock-names = "cpu";
};
};
cpuintc: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
......
arch/mips/boot/dts/ingenic/jz4780.dtsi
View file @ 09a31a7e
......@@ -8,6 +8,29 @@ / {
#size-cells = <1>;
compatible = "ingenic,jz4780";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "ingenic,xburst-fpu1.0-mxu1.1";
reg = <0>;
clocks = <&cgu JZ4780_CLK_CPU>;
clock-names = "cpu";
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "ingenic,xburst-fpu1.0-mxu1.1";
reg = <1>;
clocks = <&cgu JZ4780_CLK_CORE1>;
clock-names = "cpu";
};
};
cpuintc: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
......
arch/mips/boot/dts/ingenic/qi_lb60.dts
View file @ 09a31a7e
......@@ -109,74 +109,73 @@ keyboard {
debounce-delay-ms = <10>;
wakeup-source;
row-gpios = <&gpd 18 0 &gpd 19 0 &gpd 20 0 &gpd 21 0
&gpd 22 0 &gpd 23 0 &gpd 24 0 &gpd 26 0>;
col-gpios = <&gpc 10 0 &gpc 11 0 &gpc 12 0 &gpc 13 0
&gpc 14 0 &gpc 15 0 &gpc 16 0 &gpc 17 0>;
row-gpios = <&gpd 18 0>, <&gpd 19 0>, <&gpd 20 0>, <&gpd 21 0>,
<&gpd 22 0>, <&gpd 23 0>, <&gpd 24 0>, <&gpd 26 0>;
col-gpios = <&gpc 10 0>, <&gpc 11 0>, <&gpc 12 0>, <&gpc 13 0>,
<&gpc 14 0>, <&gpc 15 0>, <&gpc 16 0>, <&gpc 17 0>;
gpio-activelow;
linux,keymap = <
MATRIX_KEY(0, 0, KEY_F1) /* S2 */
MATRIX_KEY(0, 1, KEY_F2) /* S3 */
MATRIX_KEY(0, 2, KEY_F3) /* S4 */
MATRIX_KEY(0, 3, KEY_F4) /* S5 */
MATRIX_KEY(0, 4, KEY_F5) /* S6 */
MATRIX_KEY(0, 5, KEY_F6) /* S7 */
MATRIX_KEY(0, 6, KEY_F7) /* S8 */
MATRIX_KEY(1, 0, KEY_Q) /* S10 */
MATRIX_KEY(1, 1, KEY_W) /* S11 */
MATRIX_KEY(1, 2, KEY_E) /* S12 */
MATRIX_KEY(1, 3, KEY_R) /* S13 */
MATRIX_KEY(1, 4, KEY_T) /* S14 */
MATRIX_KEY(1, 5, KEY_Y) /* S15 */
MATRIX_KEY(1, 6, KEY_U) /* S16 */
MATRIX_KEY(1, 7, KEY_I) /* S17 */
MATRIX_KEY(2, 0, KEY_A) /* S18 */
MATRIX_KEY(2, 1, KEY_S) /* S19 */
MATRIX_KEY(2, 2, KEY_D) /* S20 */
MATRIX_KEY(2, 3, KEY_F) /* S21 */
MATRIX_KEY(2, 4, KEY_G) /* S22 */
MATRIX_KEY(2, 5, KEY_H) /* S23 */
MATRIX_KEY(2, 6, KEY_J) /* S24 */
MATRIX_KEY(2, 7, KEY_K) /* S25 */
MATRIX_KEY(3, 0, KEY_ESC) /* S26 */
MATRIX_KEY(3, 1, KEY_Z) /* S27 */
MATRIX_KEY(3, 2, KEY_X) /* S28 */
MATRIX_KEY(3, 3, KEY_C) /* S29 */
MATRIX_KEY(3, 4, KEY_V) /* S30 */
MATRIX_KEY(3, 5, KEY_B) /* S31 */
MATRIX_KEY(3, 6, KEY_N) /* S32 */
MATRIX_KEY(3, 7, KEY_M) /* S33 */
MATRIX_KEY(4, 0, KEY_TAB) /* S34 */
MATRIX_KEY(4, 1, KEY_CAPSLOCK) /* S35 */
MATRIX_KEY(4, 2, KEY_BACKSLASH) /* S36 */
MATRIX_KEY(4, 3, KEY_APOSTROPHE) /* S37 */
MATRIX_KEY(4, 4, KEY_COMMA) /* S38 */
MATRIX_KEY(4, 5, KEY_DOT) /* S39 */
MATRIX_KEY(4, 6, KEY_SLASH) /* S40 */
MATRIX_KEY(4, 7, KEY_UP) /* S41 */
MATRIX_KEY(5, 0, KEY_O) /* S42 */
MATRIX_KEY(5, 1, KEY_L) /* S43 */
MATRIX_KEY(5, 2, KEY_EQUAL) /* S44 */
MATRIX_KEY(5, 3, KEY_QI_UPRED) /* S45 */
MATRIX_KEY(5, 4, KEY_SPACE) /* S46 */
MATRIX_KEY(5, 5, KEY_QI_QI) /* S47 */
MATRIX_KEY(5, 6, KEY_RIGHTCTRL) /* S48 */
MATRIX_KEY(5, 7, KEY_LEFT) /* S49 */
MATRIX_KEY(6, 0, KEY_F8) /* S50 */
MATRIX_KEY(6, 1, KEY_P) /* S51 */
MATRIX_KEY(6, 2, KEY_BACKSPACE)/* S52 */
MATRIX_KEY(6, 3, KEY_ENTER) /* S53 */
MATRIX_KEY(6, 4, KEY_QI_VOLUP) /* S54 */
MATRIX_KEY(6, 5, KEY_QI_VOLDOWN) /* S55 */
MATRIX_KEY(6, 6, KEY_DOWN) /* S56 */
MATRIX_KEY(6, 7, KEY_RIGHT) /* S57 */
MATRIX_KEY(7, 0, KEY_LEFTSHIFT) /* S58 */
MATRIX_KEY(7, 1, KEY_LEFTALT) /* S59 */
MATRIX_KEY(7, 2, KEY_QI_FN) /* S60 */
>;
linux,keymap =
<MATRIX_KEY(0, 0, KEY_F1)>, /* S2 */
<MATRIX_KEY(0, 1, KEY_F2)>, /* S3 */
<MATRIX_KEY(0, 2, KEY_F3)>, /* S4 */
<MATRIX_KEY(0, 3, KEY_F4)>, /* S5 */
<MATRIX_KEY(0, 4, KEY_F5)>, /* S6 */
<MATRIX_KEY(0, 5, KEY_F6)>, /* S7 */
<MATRIX_KEY(0, 6, KEY_F7)>, /* S8 */
<MATRIX_KEY(1, 0, KEY_Q)>, /* S10 */
<MATRIX_KEY(1, 1, KEY_W)>, /* S11 */
<MATRIX_KEY(1, 2, KEY_E)>, /* S12 */
<MATRIX_KEY(1, 3, KEY_R)>, /* S13 */
<MATRIX_KEY(1, 4, KEY_T)>, /* S14 */
<MATRIX_KEY(1, 5, KEY_Y)>, /* S15 */
<MATRIX_KEY(1, 6, KEY_U)>, /* S16 */
<MATRIX_KEY(1, 7, KEY_I)>, /* S17 */
<MATRIX_KEY(2, 0, KEY_A)>, /* S18 */
<MATRIX_KEY(2, 1, KEY_S)>, /* S19 */
<MATRIX_KEY(2, 2, KEY_D)>, /* S20 */
<MATRIX_KEY(2, 3, KEY_F)>, /* S21 */
<MATRIX_KEY(2, 4, KEY_G)>, /* S22 */
<MATRIX_KEY(2, 5, KEY_H)>, /* S23 */
<MATRIX_KEY(2, 6, KEY_J)>, /* S24 */
<MATRIX_KEY(2, 7, KEY_K)>, /* S25 */
<MATRIX_KEY(3, 0, KEY_ESC)>, /* S26 */
<MATRIX_KEY(3, 1, KEY_Z)>, /* S27 */
<MATRIX_KEY(3, 2, KEY_X)>, /* S28 */
<MATRIX_KEY(3, 3, KEY_C)>, /* S29 */
<MATRIX_KEY(3, 4, KEY_V)>, /* S30 */
<MATRIX_KEY(3, 5, KEY_B)>, /* S31 */
<MATRIX_KEY(3, 6, KEY_N)>, /* S32 */
<MATRIX_KEY(3, 7, KEY_M)>, /* S33 */
<MATRIX_KEY(4, 0, KEY_TAB)>, /* S34 */
<MATRIX_KEY(4, 1, KEY_CAPSLOCK)>, /* S35 */
<MATRIX_KEY(4, 2, KEY_BACKSLASH)>, /* S36 */
<MATRIX_KEY(4, 3, KEY_APOSTROPHE)>, /* S37 */
<MATRIX_KEY(4, 4, KEY_COMMA)>, /* S38 */
<MATRIX_KEY(4, 5, KEY_DOT)>, /* S39 */
<MATRIX_KEY(4, 6, KEY_SLASH)>, /* S40 */
<MATRIX_KEY(4, 7, KEY_UP)>, /* S41 */
<MATRIX_KEY(5, 0, KEY_O)>, /* S42 */
<MATRIX_KEY(5, 1, KEY_L)>, /* S43 */
<MATRIX_KEY(5, 2, KEY_EQUAL)>, /* S44 */
<MATRIX_KEY(5, 3, KEY_QI_UPRED)>, /* S45 */
<MATRIX_KEY(5, 4, KEY_SPACE)>, /* S46 */
<MATRIX_KEY(5, 5, KEY_QI_QI)>, /* S47 */
<MATRIX_KEY(5, 6, KEY_RIGHTCTRL)>, /* S48 */
<MATRIX_KEY(5, 7, KEY_LEFT)>, /* S49 */
<MATRIX_KEY(6, 0, KEY_F8)>, /* S50 */
<MATRIX_KEY(6, 1, KEY_P)>, /* S51 */
<MATRIX_KEY(6, 2, KEY_BACKSPACE)>,/* S52 */
<MATRIX_KEY(6, 3, KEY_ENTER)>, /* S53 */
<MATRIX_KEY(6, 4, KEY_QI_VOLUP)>, /* S54 */
<MATRIX_KEY(6, 5, KEY_QI_VOLDOWN)>, /* S55 */
<MATRIX_KEY(6, 6, KEY_DOWN)>, /* S56 */
<MATRIX_KEY(6, 7, KEY_RIGHT)>, /* S57 */
<MATRIX_KEY(7, 0, KEY_LEFTSHIFT)>, /* S58 */
<MATRIX_KEY(7, 1, KEY_LEFTALT)>, /* S59 */
<MATRIX_KEY(7, 2, KEY_QI_FN)>; /* S60 */
};
spi {
......@@ -261,12 +260,12 @@ nandc: nand-controller@1 {
#address-cells = <1>;
#size-cells = <0>;
ingenic,bch-controller = <&ecc>;
ecc-engine = <&ecc>;
pinctrl-names = "default";
pinctrl-0 = <&pins_nemc>;
rb-gpios = <&gpc 30 GPIO_ACTIVE_LOW>;
rb-gpios = <&gpc 30 GPIO_ACTIVE_HIGH>;
nand@1 {
reg = <1>;
......@@ -324,7 +323,7 @@ pins_lcd: lcd {
pins_nemc: nemc {
function = "nand";
groups = "nand-cs1";
groups = "nand-fre-fwe", "nand-cs1";
};
pins_uart0: uart0 {
......
arch/mips/boot/dts/ingenic/x1000.dtsi
View file @ 09a31a7e
......@@ -8,6 +8,20 @@ / {
#size-cells = <1>;
compatible = "ingenic,x1000", "ingenic,x1000e";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "ingenic,xburst-fpu1.0-mxu1.1";
reg = <0>;
clocks = <&cgu X1000_CLK_CPU>;
clock-names = "cpu";
};
};
cpuintc: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
......
arch/mips/boot/dts/ingenic/x1830.dtsi
View file @ 09a31a7e
......@@ -8,6 +8,20 @@ / {
#size-cells = <1>;
compatible = "ingenic,x1830";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "ingenic,xburst-fpu2.0-mxu2.0";
reg = <0>;
clocks = <&cgu X1830_CLK_CPU>;
clock-names = "cpu";
};
};
cpuintc: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
......
arch/mips/boot/dts/loongson/ls7a-pch.dtsi
View file @ 09a31a7e
......@@ -19,6 +19,45 @@ pic: interrupt-controller@10000000 {
#interrupt-cells = <2>;
};
ls7a_uart0: serial@10080000 {
compatible = "ns16550a";
reg = <0 0x10080000 0 0x100>;
clock-frequency = <50000000>;
interrupt-parent = <&pic>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
no-loopback-test;
};
ls7a_uart1: serial@10080100 {
status = "disabled";
compatible = "ns16550a";
reg = <0 0x10080100 0 0x100>;
clock-frequency = <50000000>;
interrupt-parent = <&pic>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
no-loopback-test;
};
ls7a_uart2: serial@10080200 {
status = "disabled";
compatible = "ns16550a";
reg = <0 0x10080200 0 0x100>;
clock-frequency = <50000000>;
interrupt-parent = <&pic>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
no-loopback-test;
};
ls7a_uart3: serial@10080300 {
status = "disabled";
compatible = "ns16550a";
reg = <0 0x10080300 0 0x100>;
clock-frequency = <50000000>;
interrupt-parent = <&pic>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
no-loopback-test;
};
pci@1a000000 {
compatible = "loongson,ls7a-pci";
device_type = "pci";
......
arch/mips/cavium-octeon/setup.c
View file @ 09a31a7e
......@@ -16,6 +16,7 @@
#include <linux/export.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/memblock.h>
#include <linux/serial.h>
#include <linux/smp.h>
#include <linux/types.h>
......@@ -930,7 +931,7 @@ static __init void memory_exclude_page(u64 addr, u64 *mem, u64 *size)
{
if (addr > *mem && addr < *mem + *size) {
u64 inc = addr - *mem;
add_memory_region(*mem, inc, BOOT_MEM_RAM);
memblock_add(*mem, inc);
*mem += inc;
*size -= inc;
}
......@@ -992,19 +993,18 @@ void __init plat_mem_setup(void)
/* Crashkernel ignores bootmem list. It relies on mem=X@Y option */
#ifdef CONFIG_CRASH_DUMP
add_memory_region(reserve_low_mem, max_memory, BOOT_MEM_RAM);
memblock_add(reserve_low_mem, max_memory);
total += max_memory;
#else
#ifdef CONFIG_KEXEC
if (crashk_size > 0) {
add_memory_region(crashk_base, crashk_size, BOOT_MEM_RAM);
memblock_add(crashk_base, crashk_size);
crashk_end = crashk_base + crashk_size;
}
#endif
/*
* When allocating memory, we want incrementing addresses from
* bootmem_alloc so the code in add_memory_region can merge
* regions next to each other.
* When allocating memory, we want incrementing addresses,
* which is handled by memblock
*/
cvmx_bootmem_lock();
while (total < max_memory) {
......@@ -1039,13 +1039,9 @@ void __init plat_mem_setup(void)
*/
if (memory < crashk_base && end > crashk_end) {
/* region is fully in */
add_memory_region(memory,
crashk_base - memory,
BOOT_MEM_RAM);
memblock_add(memory, crashk_base - memory);
total += crashk_base - memory;
add_memory_region(crashk_end,
end - crashk_end,
BOOT_MEM_RAM);
memblock_add(crashk_end, end - crashk_end);
total += end - crashk_end;
continue;
}
......@@ -1073,7 +1069,7 @@ void __init plat_mem_setup(void)
*/
mem_alloc_size -= end - crashk_base;
#endif
add_memory_region(memory, mem_alloc_size, BOOT_MEM_RAM);
memblock_add(memory, mem_alloc_size);
total += mem_alloc_size;
/* Recovering mem_alloc_size */
mem_alloc_size = 4 << 20;
......@@ -1088,7 +1084,7 @@ void __init plat_mem_setup(void)
/* Adjust for physical offset. */
kernel_start &= ~0xffffffff80000000ULL;
add_memory_region(kernel_start, kernel_size, BOOT_MEM_RAM);
memblock_add(kernel_start, kernel_size);
#endif /* CONFIG_CRASH_DUMP */
#ifdef CONFIG_CAVIUM_RESERVE32
......@@ -1126,7 +1122,7 @@ EXPORT_SYMBOL(prom_putchar);
void __init prom_free_prom_memory(void)
{
if (CAVIUM_OCTEON_DCACHE_PREFETCH_WAR) {
if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
/* Check for presence of Core-14449 fix. */
u32 insn;
u32 *foo;
......
arch/mips/cobalt/setup.c
View file @ 09a31a7e
......@@ -13,6 +13,7 @@
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/memblock.h>
#include <linux/pm.h>
#include <asm/bootinfo.h>
......@@ -112,7 +113,7 @@ void __init prom_init(void)
strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE);
}
add_memory_region(0x0, memsz, BOOT_MEM_RAM);
memblock_add(0, memsz);
setup_8250_early_printk_port(CKSEG1ADDR(0x1c800000), 0, 0);
}
......
arch/mips/configs/ci20_defconfig
View file @ 09a31a7e
......@@ -22,7 +22,7 @@ CONFIG_EMBEDDED=y
# CONFIG_VM_EVENT_COUNTERS is not set
# CONFIG_COMPAT_BRK is not set
CONFIG_SLAB=y
CONFIG_MACH_INGENIC=y
CONFIG_MACH_INGENIC_SOC=y
CONFIG_JZ4780_CI20=y
CONFIG_HIGHMEM=y
CONFIG_HZ_100=y
......@@ -42,7 +42,7 @@ CONFIG_IP_PNP_DHCP=y
# CONFIG_IPV6 is not set
# CONFIG_WIRELESS is not set
CONFIG_DEVTMPFS=y
# CONFIG_FW_LOADER is not set
CONFIG_FW_LOADER=m
# CONFIG_ALLOW_DEV_COREDUMP is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
......
arch/mips/configs/cu1000-neo_defconfig
View file @ 09a31a7e
CONFIG_LOCALVERSION_AUTO=y
CONFIG_KERNEL_GZIP=y
CONFIG_SYSVIPC=y
CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
......@@ -9,7 +7,6 @@ CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_CGROUPS=y
CONFIG_MEMCG=y
CONFIG_MEMCG_KMEM=y
CONFIG_CGROUP_SCHED=y
CONFIG_CGROUP_FREEZER=y
CONFIG_CGROUP_DEVICE=y
......@@ -22,7 +19,7 @@ CONFIG_EMBEDDED=y
# CONFIG_VM_EVENT_COUNTERS is not set
# CONFIG_COMPAT_BRK is not set
CONFIG_SLAB=y
CONFIG_MACH_INGENIC=y
CONFIG_MACH_INGENIC_SOC=y
CONFIG_X1000_CU1000_NEO=y
CONFIG_HIGHMEM=y
CONFIG_HZ_100=y
......@@ -31,7 +28,6 @@ CONFIG_HZ_100=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
# CONFIG_COMPACTION is not set
CONFIG_CMA=y
CONFIG_CMA_AREAS=7
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
......@@ -40,19 +36,16 @@ CONFIG_CFG80211=y
CONFIG_UEVENT_HELPER=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
# CONFIG_FW_LOADER is not set
# CONFIG_ALLOW_DEV_COREDUMP is not set
CONFIG_NETDEVICES=y
CONFIG_STMMAC_ETH=y
CONFIG_SMSC_PHY=y
CONFIG_BRCMFMAC=y
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
CONFIG_VT_HW_CONSOLE_BINDING=y
CONFIG_LEGACY_PTY_COUNT=2
CONFIG_SERIAL_EARLYCON=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=3
......@@ -66,8 +59,6 @@ CONFIG_GPIO_SYSFS=y
CONFIG_SENSORS_ADS7828=y
CONFIG_WATCHDOG=y
CONFIG_JZ4740_WDT=y
# CONFIG_LCD_CLASS_DEVICE is not set
# CONFIG_BACKLIGHT_CLASS_DEVICE is not set
# CONFIG_VGA_CONSOLE is not set
# CONFIG_HID is not set
# CONFIG_USB_SUPPORT is not set
......@@ -82,8 +73,6 @@ CONFIG_RTC_DRV_JZ4740=y
CONFIG_DMADEVICES=y
CONFIG_DMA_JZ4780=y
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_NVMEM=y
CONFIG_NVMEM_SYSFS=y
CONFIG_EXT4_FS=y
# CONFIG_DNOTIFY is not set
CONFIG_AUTOFS_FS=y
......@@ -108,8 +97,8 @@ CONFIG_CONSOLE_LOGLEVEL_QUIET=15
CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
CONFIG_DEBUG_INFO=y
CONFIG_STRIP_ASM_SYMS=y
CONFIG_DEBUG_FS=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
CONFIG_PANIC_ON_OOPS=y
CONFIG_PANIC_TIMEOUT=10
# CONFIG_SCHED_DEBUG is not set
......
arch/mips/configs/cu1830-neo_defconfig
View file @ 09a31a7e
CONFIG_LOCALVERSION_AUTO=y
CONFIG_KERNEL_GZIP=y
CONFIG_SYSVIPC=y
CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
......@@ -9,7 +7,6 @@ CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_CGROUPS=y
CONFIG_MEMCG=y
CONFIG_MEMCG_KMEM=y
CONFIG_CGROUP_SCHED=y
CONFIG_CGROUP_FREEZER=y
CONFIG_CGROUP_DEVICE=y
......@@ -22,7 +19,7 @@ CONFIG_EMBEDDED=y
# CONFIG_VM_EVENT_COUNTERS is not set
# CONFIG_COMPAT_BRK is not set
CONFIG_SLAB=y
CONFIG_MACH_INGENIC=y
CONFIG_MACH_INGENIC_SOC=y
CONFIG_X1830_CU1830_NEO=y
CONFIG_HIGHMEM=y
CONFIG_HZ_100=y
......@@ -31,7 +28,6 @@ CONFIG_HZ_100=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
# CONFIG_COMPACTION is not set
CONFIG_CMA=y
CONFIG_CMA_AREAS=7
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
......@@ -40,7 +36,6 @@ CONFIG_CFG80211=y
CONFIG_UEVENT_HELPER=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
# CONFIG_FW_LOADER is not set
# CONFIG_ALLOW_DEV_COREDUMP is not set
CONFIG_MD=y
CONFIG_BLK_DEV_MD=y
......@@ -49,13 +44,11 @@ CONFIG_NETDEVICES=y
CONFIG_STMMAC_ETH=y
CONFIG_ICPLUS_PHY=y
CONFIG_BRCMFMAC=y
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
CONFIG_VT_HW_CONSOLE_BINDING=y
CONFIG_LEGACY_PTY_COUNT=2
CONFIG_SERIAL_EARLYCON=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=2
......@@ -69,8 +62,6 @@ CONFIG_GPIO_SYSFS=y
CONFIG_SENSORS_ADS7828=y
CONFIG_WATCHDOG=y
CONFIG_JZ4740_WDT=y
# CONFIG_LCD_CLASS_DEVICE is not set
# CONFIG_BACKLIGHT_CLASS_DEVICE is not set
# CONFIG_VGA_CONSOLE is not set
# CONFIG_HID is not set
# CONFIG_USB_SUPPORT is not set
......@@ -85,8 +76,6 @@ CONFIG_RTC_DRV_JZ4740=y
CONFIG_DMADEVICES=y
CONFIG_DMA_JZ4780=y
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_NVMEM=y
CONFIG_NVMEM_SYSFS=y
CONFIG_EXT4_FS=y
# CONFIG_DNOTIFY is not set
CONFIG_AUTOFS_FS=y
......@@ -111,8 +100,8 @@ CONFIG_CONSOLE_LOGLEVEL_QUIET=15
CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
CONFIG_DEBUG_INFO=y
CONFIG_STRIP_ASM_SYMS=y
CONFIG_DEBUG_FS=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
CONFIG_PANIC_ON_OOPS=y
CONFIG_PANIC_TIMEOUT=10
# CONFIG_SCHED_DEBUG is not set
......
arch/mips/configs/gcw0_defconfig
View file @ 09a31a7e
......@@ -4,7 +4,7 @@ CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT_VOLUNTARY=y
CONFIG_EMBEDDED=y
CONFIG_PROFILING=y
CONFIG_MACH_INGENIC=y
CONFIG_MACH_INGENIC_SOC=y
CONFIG_JZ4770_GCW0=y
CONFIG_HIGHMEM=y
# CONFIG_SECCOMP is not set
......
arch/mips/configs/loongson3_defconfig
View file @ 09a31a7e
......@@ -30,7 +30,6 @@ CONFIG_EMBEDDED=y
CONFIG_PERF_EVENTS=y
CONFIG_MACH_LOONGSON64=y
CONFIG_CPU_HAS_MSA=y
CONFIG_SMP=y
CONFIG_NR_CPUS=16
CONFIG_HZ_256=y
CONFIG_KEXEC=y
......@@ -403,7 +402,6 @@ CONFIG_CRYPTO_TEA=m
CONFIG_CRYPTO_TWOFISH=m
CONFIG_CRYPTO_DEFLATE=m
CONFIG_PRINTK_TIME=y
CONFIG_FRAME_WARN=1024
CONFIG_STRIP_ASM_SYMS=y
CONFIG_MAGIC_SYSRQ=y
# CONFIG_SCHED_DEBUG is not set
......
arch/mips/configs/pnx8335_stb225_defconfig deleted 100644 → 0
View file @ 847d4287
# CONFIG_LOCALVERSION_AUTO is not set
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT_VOLUNTARY=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_EXPERT=y
CONFIG_SLAB=y
CONFIG_NXP_STB225=y
CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_HZ_128=y
# CONFIG_SECCOMP is not set
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_INET_AH=y
# CONFIG_IPV6 is not set
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_LE_BYTE_SWAP=y
CONFIG_MTD_CFI_GEOMETRY=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_SD=y
# CONFIG_SCSI_LOWLEVEL is not set
CONFIG_ATA=y
CONFIG_NETDEVICES=y
CONFIG_INPUT_EVDEV=m
CONFIG_INPUT_EVBUG=m
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_VT_CONSOLE is not set
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_PNX8XXX=y
CONFIG_SERIAL_PNX8XXX_CONSOLE=y
CONFIG_HW_RANDOM=y
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
# CONFIG_HWMON is not set
CONFIG_FB=y
# CONFIG_VGA_CONSOLE is not set
CONFIG_SOUND=m
CONFIG_SND=m
CONFIG_SND_VERBOSE_PRINTK=y
CONFIG_SND_DEBUG=y
CONFIG_SND_SEQUENCER=m
CONFIG_EXT2_FS=m
# CONFIG_DNOTIFY is not set
CONFIG_MSDOS_FS=m
CONFIG_VFAT_FS=m
CONFIG_TMPFS=y
CONFIG_JFFS2_FS=y
CONFIG_CRAMFS=y
CONFIG_NFS_FS=y
CONFIG_ROOT_NFS=y
CONFIG_NFSD=m
CONFIG_NFSD_V3=y
CONFIG_NLS=y
CONFIG_NLS_CODEPAGE_437=m
CONFIG_NLS_CODEPAGE_850=m
CONFIG_NLS_CODEPAGE_932=m
CONFIG_NLS_ASCII=m
CONFIG_NLS_ISO8859_1=m
CONFIG_NLS_ISO8859_15=m
CONFIG_NLS_UTF8=m
arch/mips/configs/qi_lb60_defconfig
View file @ 09a31a7e
......@@ -7,7 +7,8 @@ CONFIG_EMBEDDED=y
# CONFIG_VM_EVENT_COUNTERS is not set
# CONFIG_COMPAT_BRK is not set
CONFIG_SLAB=y
CONFIG_MACH_INGENIC=y
CONFIG_MACH_INGENIC_SOC=y
CONFIG_JZ4740_QI_LB60=y
CONFIG_HZ_100=y
# CONFIG_SECCOMP is not set
CONFIG_MODULES=y
......@@ -72,9 +73,7 @@ CONFIG_DRM=y
CONFIG_DRM_FBDEV_OVERALLOC=200
CONFIG_DRM_PANEL_SIMPLE=y
CONFIG_DRM_INGENIC=y
# CONFIG_LCD_CLASS_DEVICE is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=y
# CONFIG_BACKLIGHT_GENERIC is not set
# CONFIG_VGA_CONSOLE is not set
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_LOGO=y
......@@ -170,9 +169,9 @@ CONFIG_PRINTK_TIME=y
CONFIG_DEBUG_INFO=y
CONFIG_STRIP_ASM_SYMS=y
CONFIG_READABLE_ASM=y
CONFIG_KGDB=y
CONFIG_DEBUG_KMEMLEAK=y
CONFIG_DEBUG_MEMORY_INIT=y
CONFIG_DEBUG_STACKOVERFLOW=y
CONFIG_PANIC_ON_OOPS=y
# CONFIG_FTRACE is not set
CONFIG_KGDB=y
arch/mips/configs/rs90_defconfig
View file @ 09a31a7e
......@@ -19,7 +19,7 @@ CONFIG_EMBEDDED=y
# CONFIG_PERF_EVENTS is not set
CONFIG_SLAB=y
CONFIG_PROFILING=y
CONFIG_MACH_INGENIC=y
CONFIG_MACH_INGENIC_SOC=y
CONFIG_JZ4740_RS90=y
CONFIG_PAGE_SIZE_16KB=y
CONFIG_HZ_100=y
......@@ -80,8 +80,8 @@ CONFIG_KEYBOARD_GPIO=y
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
CONFIG_LEGACY_PTY_COUNT=2
# CONFIG_DEVMEM is not set
# CONFIG_HW_RANDOM is not set
# CONFIG_DEVMEM is not set
# CONFIG_I2C_COMPAT is not set
# CONFIG_I2C_HELPER_AUTO is not set
CONFIG_POWER_SUPPLY=y
......
arch/mips/dec/prom/memory.c
View file @ 09a31a7e
......@@ -12,7 +12,6 @@
#include <linux/types.h>
#include <asm/addrspace.h>
#include <asm/bootinfo.h>
#include <asm/dec/machtype.h>
#include <asm/dec/prom.h>
#include <asm/page.h>
......@@ -28,7 +27,7 @@ volatile unsigned long mem_err; /* So we know an error occurred */
#define CHUNK_SIZE 0x400000
static inline void pmax_setup_memory_region(void)
static __init void pmax_setup_memory_region(void)
{
volatile unsigned char *memory_page, dummy;
char old_handler[0x80];
......@@ -50,15 +49,14 @@ static inline void pmax_setup_memory_region(void)
}
memcpy((void *)(CKSEG0 + 0x80), &old_handler, 0x80);
add_memory_region(0, (unsigned long)memory_page - CKSEG1 - CHUNK_SIZE,
BOOT_MEM_RAM);
memblock_add(0, (unsigned long)memory_page - CKSEG1 - CHUNK_SIZE);
}
/*
* Use the REX prom calls to get hold of the memory bitmap, and thence
* determine memory size.
*/
static inline void rex_setup_memory_region(void)
static __init void rex_setup_memory_region(void)
{
int i, bitmap_size;
unsigned long mem_start = 0, mem_size = 0;
......@@ -76,13 +74,13 @@ static inline void rex_setup_memory_region(void)
else if (!mem_size)
mem_start += (8 * bm->pagesize);
else {
add_memory_region(mem_start, mem_size, BOOT_MEM_RAM);
memblock_add(mem_start, mem_size);
mem_start += mem_size + (8 * bm->pagesize);
mem_size = 0;
}
}
if (mem_size)
add_memory_region(mem_start, mem_size, BOOT_MEM_RAM);
memblock_add(mem_start, mem_size);
}
void __init prom_meminit(u32 magic)
......
arch/mips/dec/setup.c
View file @ 09a31a7e
......@@ -6,7 +6,7 @@
* for more details.
*
* Copyright (C) 1998 Harald Koerfgen
* Copyright (C) 2000, 2001, 2002, 2003, 2005 Maciej W. Rozycki
* Copyright (C) 2000, 2001, 2002, 2003, 2005, 2020 Maciej W. Rozycki
*/
#include <linux/console.h>
#include <linux/export.h>
......@@ -15,6 +15,7 @@
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/irqnr.h>
#include <linux/memblock.h>
#include <linux/param.h>
#include <linux/percpu-defs.h>
#include <linux/sched.h>
......@@ -22,6 +23,7 @@
#include <linux/types.h>
#include <linux/pm.h>
#include <asm/addrspace.h>
#include <asm/bootinfo.h>
#include <asm/cpu.h>
#include <asm/cpu-features.h>
......@@ -29,7 +31,9 @@
#include <asm/irq.h>
#include <asm/irq_cpu.h>
#include <asm/mipsregs.h>
#include <asm/page.h>
#include <asm/reboot.h>
#include <asm/sections.h>
#include <asm/time.h>
#include <asm/traps.h>
#include <asm/wbflush.h>
......@@ -146,6 +150,9 @@ void __init plat_mem_setup(void)
ioport_resource.start = ~0UL;
ioport_resource.end = 0UL;
/* Stay away from the firmware working memory area for now. */
memblock_reserve(PHYS_OFFSET, __pa_symbol(&_text) - PHYS_OFFSET);
}
/*
......
arch/mips/fw/arc/memory.c
View file @ 09a31a7e
......@@ -68,20 +68,24 @@ static char *arc_mtypes[8] = {
: arc_mtypes[a.arc]
#endif
enum {
mem_free, mem_prom_used, mem_reserved
};
static inline int memtype_classify_arcs(union linux_memtypes type)
{
switch (type.arcs) {
case arcs_fcontig:
case arcs_free:
return BOOT_MEM_RAM;
return mem_free;
case arcs_atmp:
return BOOT_MEM_ROM_DATA;
return mem_prom_used;
case arcs_eblock:
case arcs_rvpage:
case arcs_bmem:
case arcs_prog:
case arcs_aperm:
return BOOT_MEM_RESERVED;
return mem_reserved;
default:
BUG();
}
......@@ -93,15 +97,15 @@ static inline int memtype_classify_arc(union linux_memtypes type)
switch (type.arc) {
case arc_free:
case arc_fcontig:
return BOOT_MEM_RAM;
return mem_free;
case arc_atmp:
return BOOT_MEM_ROM_DATA;
return mem_prom_used;
case arc_eblock:
case arc_rvpage:
case arc_bmem:
case arc_prog:
case arc_aperm:
return BOOT_MEM_RESERVED;
return mem_reserved;
default:
BUG();
}
......@@ -143,9 +147,17 @@ void __weak __init prom_meminit(void)
size = p->pages << ARC_PAGE_SHIFT;
type = prom_memtype_classify(p->type);
add_memory_region(base, size, type);
/* ignore mirrored RAM on IP28/IP30 */
if (base < PHYS_OFFSET)
continue;
memblock_add(base, size);
if (type == mem_reserved)
memblock_reserve(base, size);
if (type == BOOT_MEM_ROM_DATA) {
if (type == mem_prom_used) {
memblock_reserve(base, size);
if (nr_prom_mem >= 5) {
pr_err("Too many ROM DATA regions");
continue;
......
arch/mips/fw/sni/sniprom.c
View file @ 09a31a7e
......@@ -11,6 +11,7 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/memblock.h>
#include <linux/string.h>
#include <linux/console.h>
......@@ -131,8 +132,7 @@ static void __init sni_mem_init(void)
}
pr_debug("Bank%d: %08x @ %08x\n", i,
memconf[i].size, memconf[i].base);
add_memory_region(memconf[i].base, memconf[i].size,
BOOT_MEM_RAM);
memblock_add(memconf[i].base, memconf[i].size);
}
}
......
arch/mips/generic/Kconfig
View file @ 09a31a7e
# SPDX-License-Identifier: GPL-2.0
if MIPS_GENERIC
if MIPS_GENERIC_KERNEL
config LEGACY_BOARDS
bool
......@@ -73,6 +73,12 @@ config FIT_IMAGE_FDT_OCELOT
from Microsemi in the FIT kernel image.
This requires u-boot on the platform.
config BOARD_INGENIC
bool "Support boards based on Ingenic SoCs"
select MACH_INGENIC_GENERIC
help
Enable support for boards based on Ingenic SoCs.
config VIRT_BOARD_RANCHU
bool "Support Ranchu platform for Android emulator"
help
......
arch/mips/generic/Makefile
View file @ 09a31a7e
......@@ -11,4 +11,5 @@ obj-y += proc.o
obj-$(CONFIG_YAMON_DT_SHIM) += yamon-dt.o
obj-$(CONFIG_LEGACY_BOARD_SEAD3) += board-sead3.o
obj-$(CONFIG_LEGACY_BOARD_OCELOT) += board-ocelot.o
obj-$(CONFIG_MACH_INGENIC) += board-ingenic.o
obj-$(CONFIG_VIRT_BOARD_RANCHU) += board-ranchu.o
arch/mips/generic/Platform
View file @ 09a31a7e
......@@ -8,8 +8,12 @@
# option) any later version.
#
# Note: order matters, keep the asm/mach-generic include last.
cflags-$(CONFIG_MACH_INGENIC_SOC) += -I$(srctree)/arch/mips/include/asm/mach-ingenic
cflags-$(CONFIG_MIPS_GENERIC) += -I$(srctree)/arch/mips/include/asm/mach-generic
load-$(CONFIG_MIPS_GENERIC) += 0xffffffff80100000
zload-$(CONFIG_MIPS_GENERIC) += 0xffffffff81000000
all-$(CONFIG_MIPS_GENERIC) := vmlinux.gz.itb
its-y := vmlinux.its.S
......
arch/mips/generic/board-ingenic.c 0 → 100644
View file @ 09a31a7e
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Support for Ingenic SoCs
*
* Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
* Copyright (C) 2011, Maarten ter Huurne <maarten@treewalker.org>
* Copyright (C) 2020 Paul Cercueil <paul@crapouillou.net>
*/
#include <linux/of_address.h>
#include <linux/of_fdt.h>
#include <linux/pm.h>
#include <linux/sizes.h>
#include <linux/suspend.h>
#include <linux/types.h>
#include <asm/bootinfo.h>
#include <asm/machine.h>
#include <asm/reboot.h>
static __init char *ingenic_get_system_type(unsigned long machtype)
{
switch (machtype) {
case MACH_INGENIC_X2000E:
return "X2000E";
case MACH_INGENIC_X2000:
return "X2000";
case MACH_INGENIC_X1830:
return "X1830";
case MACH_INGENIC_X1000E:
return "X1000E";
case MACH_INGENIC_X1000:
return "X1000";
case MACH_INGENIC_JZ4780:
return "JZ4780";
case MACH_INGENIC_JZ4775:
return "JZ4775";
case MACH_INGENIC_JZ4770:
return "JZ4770";
case MACH_INGENIC_JZ4725B:
return "JZ4725B";
default:
return "JZ4740";
}
}
static __init const void *ingenic_fixup_fdt(const void *fdt, const void *match_data)
{
/*
* Old devicetree files for the qi,lb60 board did not have a /memory
* node. Hardcode the memory info here.
*/
if (!fdt_node_check_compatible(fdt, 0, "qi,lb60") &&
fdt_path_offset(fdt, "/memory") < 0)
early_init_dt_add_memory_arch(0, SZ_32M);
mips_machtype = (unsigned long)match_data;
system_type = ingenic_get_system_type(mips_machtype);
return fdt;
}
static const struct of_device_id ingenic_of_match[] __initconst = {
{ .compatible = "ingenic,jz4740", .data = (void *)MACH_INGENIC_JZ4740 },
{ .compatible = "ingenic,jz4725b", .data = (void *)MACH_INGENIC_JZ4725B },
{ .compatible = "ingenic,jz4770", .data = (void *)MACH_INGENIC_JZ4770 },
{ .compatible = "ingenic,jz4775", .data = (void *)MACH_INGENIC_JZ4775 },
{ .compatible = "ingenic,jz4780", .data = (void *)MACH_INGENIC_JZ4780 },
{ .compatible = "ingenic,x1000", .data = (void *)MACH_INGENIC_X1000 },
{ .compatible = "ingenic,x1000e", .data = (void *)MACH_INGENIC_X1000E },
{ .compatible = "ingenic,x1830", .data = (void *)MACH_INGENIC_X1830 },
{ .compatible = "ingenic,x2000", .data = (void *)MACH_INGENIC_X2000 },
{ .compatible = "ingenic,x2000e", .data = (void *)MACH_INGENIC_X2000E },
{}
};
MIPS_MACHINE(ingenic) = {
.matches = ingenic_of_match,
.fixup_fdt = ingenic_fixup_fdt,
};
static void ingenic_wait_instr(void)
{
__asm__(".set push;\n"
".set mips3;\n"
"wait;\n"
".set pop;\n"
);
}
static void ingenic_halt(void)
{
for (;;)
ingenic_wait_instr();
}
static int __maybe_unused ingenic_pm_enter(suspend_state_t state)
{
ingenic_wait_instr();
return 0;
}
static const struct platform_suspend_ops ingenic_pm_ops __maybe_unused = {
.valid = suspend_valid_only_mem,
.enter = ingenic_pm_enter,
};
static int __init ingenic_pm_init(void)
{
if (boot_cpu_type() == CPU_XBURST) {
if (IS_ENABLED(CONFIG_PM_SLEEP))
suspend_set_ops(&ingenic_pm_ops);
_machine_halt = ingenic_halt;
}
return 0;
}
late_initcall(ingenic_pm_init);
arch/mips/generic/init.c
View file @ 09a31a7e
......@@ -39,12 +39,11 @@ void __init *plat_get_fdt(void)
/* Already set up */
return (void *)fdt;
if ((fw_arg0 == -2) && !fdt_check_header((void *)fw_passed_dtb)) {
if (fw_passed_dtb && !fdt_check_header((void *)fw_passed_dtb)) {
/*
* We booted using the UHI boot protocol, so we have been
* provided with the appropriate device tree for the board.
* Make use of it & search for any machine struct based upon
* the root compatible string.
* We have been provided with the appropriate device tree for
* the board. Make use of it & search for any machine struct
* based upon the root compatible string.
*/
fdt = (void *)fw_passed_dtb;
......@@ -106,7 +105,7 @@ void __init plat_mem_setup(void)
if (mach && mach->fixup_fdt)
fdt = mach->fixup_fdt(fdt, mach_match_data);
strlcpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE);
fw_init_cmdline();
__dt_setup_arch((void *)fdt);
}
......
arch/mips/generic/proc.c
View file @ 09a31a7e
......@@ -8,11 +8,16 @@
#include <asm/bootinfo.h>
char *system_type;
const char *get_system_type(void)
{
const char *str;
int err;
if (system_type)
return system_type;
err = of_property_read_string(of_root, "model", &str);
if (!err)
return str;
......
arch/mips/include/asm/bootinfo.h
View file @ 09a31a7e
......@@ -79,8 +79,10 @@ enum ingenic_machine_type {
MACH_INGENIC_JZ4775,
MACH_INGENIC_JZ4780,
MACH_INGENIC_X1000,
MACH_INGENIC_X1000E,
MACH_INGENIC_X1830,
MACH_INGENIC_X2000,
MACH_INGENIC_X2000E,
};
extern char *system_type;
......@@ -88,13 +90,6 @@ const char *get_system_type(void);
extern unsigned long mips_machtype;
#define BOOT_MEM_RAM 1
#define BOOT_MEM_ROM_DATA 2
#define BOOT_MEM_RESERVED 3
#define BOOT_MEM_INIT_RAM 4
#define BOOT_MEM_NOMAP 5
extern void add_memory_region(phys_addr_t start, phys_addr_t size, long type);
extern void detect_memory_region(phys_addr_t start, phys_addr_t sz_min, phys_addr_t sz_max);
extern void prom_init(void);
......
arch/mips/include/asm/cpu-features.h
View file @ 09a31a7e
......@@ -171,9 +171,6 @@
#ifndef cpu_has_llsc
#define cpu_has_llsc __isa_ge_or_opt(1, MIPS_CPU_LLSC)
#endif
#ifndef cpu_has_bp_ghist
#define cpu_has_bp_ghist __opt(MIPS_CPU_BP_GHIST)
#endif
#ifndef kernel_uses_llsc
#define kernel_uses_llsc cpu_has_llsc
#endif
......
arch/mips/include/asm/cpu.h
View file @ 09a31a7e
......@@ -398,7 +398,6 @@ enum cpu_type_enum {
#define MIPS_CPU_RW_LLB BIT_ULL(32) /* LLADDR/LLB writes are allowed */
#define MIPS_CPU_LPA BIT_ULL(33) /* CPU supports Large Physical Addressing */
#define MIPS_CPU_CDMM BIT_ULL(34) /* CPU has Common Device Memory Map */
#define MIPS_CPU_BP_GHIST BIT_ULL(35) /* R12K+ Branch Prediction Global History */
#define MIPS_CPU_SP BIT_ULL(36) /* Small (1KB) page support */
#define MIPS_CPU_FTLB BIT_ULL(37) /* CPU has Fixed-page-size TLB */
#define MIPS_CPU_NAN_LEGACY BIT_ULL(38) /* Legacy NaN implemented */
......
arch/mips/include/asm/futex.h
View file @ 09a31a7e
......@@ -21,7 +21,7 @@
#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
{ \
if (cpu_has_llsc && R10000_LLSC_WAR) { \
if (cpu_has_llsc && IS_ENABLED(CONFIG_WAR_R10000_LLSC)) { \
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
......@@ -133,7 +133,7 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
if (!access_ok(uaddr, sizeof(u32)))
return -EFAULT;
if (cpu_has_llsc && R10000_LLSC_WAR) {
if (cpu_has_llsc && IS_ENABLED(CONFIG_WAR_R10000_LLSC)) {
__asm__ __volatile__(
"# futex_atomic_cmpxchg_inatomic \n"
" .set push \n"
......
arch/mips/include/asm/idle.h
View file @ 09a31a7e
......@@ -15,6 +15,8 @@ static inline int using_rollback_handler(void)
return cpu_wait == r4k_wait;
}
extern void __init check_wait(void);
extern int mips_cpuidle_wait_enter(struct cpuidle_device *dev,
struct cpuidle_driver *drv, int index);
......
arch/mips/include/asm/llsc.h
View file @ 09a31a7e
......@@ -28,7 +28,7 @@
* works around a bug present in R10000 CPUs prior to revision 3.0 that could
* cause ll-sc sequences to execute non-atomically.
*/
#if R10000_LLSC_WAR
#ifdef CONFIG_WAR_R10000_LLSC
# define __SC_BEQZ "beqzl "
#elif MIPS_ISA_REV >= 6
# define __SC_BEQZ "beqzc "
......
arch/mips/include/asm/local.h
View file @ 09a31a7e
......@@ -31,7 +31,7 @@ static __inline__ long local_add_return(long i, local_t * l)
{
unsigned long result;
if (kernel_uses_llsc && R10000_LLSC_WAR) {
if (kernel_uses_llsc && IS_ENABLED(CONFIG_WAR_R10000_LLSC)) {
unsigned long temp;
__asm__ __volatile__(
......@@ -80,7 +80,7 @@ static __inline__ long local_sub_return(long i, local_t * l)
{
unsigned long result;
if (kernel_uses_llsc && R10000_LLSC_WAR) {
if (kernel_uses_llsc && IS_ENABLED(CONFIG_WAR_R10000_LLSC)) {
unsigned long temp;
__asm__ __volatile__(
......
arch/mips/include/asm/m48t37.h deleted 100644 → 0
View file @ 847d4287
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Registers for the SGS-Thomson M48T37 Timekeeper RAM chip
*/
#ifndef _ASM_M48T37_H
#define _ASM_M48T37_H
#include <linux/spinlock.h>
extern spinlock_t rtc_lock;
struct m48t37_rtc {
volatile u8 pad[0x7ff0]; /* NVRAM */
volatile u8 flags;
volatile u8 century;
volatile u8 alarm_sec;
volatile u8 alarm_min;
volatile u8 alarm_hour;
volatile u8 alarm_data;
volatile u8 interrupts;
volatile u8 watchdog;
volatile u8 control;
volatile u8 sec;
volatile u8 min;
volatile u8 hour;
volatile u8 day;
volatile u8 date;
volatile u8 month;
volatile u8 year;
};
#define M48T37_RTC_SET 0x80
#define M48T37_RTC_STOPPED 0x80
#define M48T37_RTC_READ 0x40
#endif /* _ASM_M48T37_H */
arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h
View file @ 09a31a7e
......@@ -39,7 +39,6 @@
#define cpu_has_guestctl2 0
#define cpu_has_guestid 0
#define cpu_has_drg 0
#define cpu_has_bp_ghist 0
#define cpu_has_mips16 0
#define cpu_has_mips16e2 0
#define cpu_has_mdmx 0
......
arch/mips/include/asm/mach-au1x00/gpio-au1300.h
View file @ 09a31a7e
......@@ -120,141 +120,4 @@ static inline int au1300_gpio_getinitlvl(unsigned int gpio)
return (v >> gpio) & 1;
}
/**********************************************************************/
/* Linux gpio framework integration.
*
* 4 use cases of Alchemy GPIOS:
*(1) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=y:
* Board must register gpiochips.
*(2) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=n:
* A gpiochip for the 75 GPIOs is registered.
*
*(3) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=y:
* the boards' gpio.h must provide the linux gpio wrapper functions,
*
*(4) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=n:
* inlinable gpio functions are provided which enable access to the
* Au1300 gpios only by using the numbers straight out of the data-
* sheets.
* Cases 1 and 3 are intended for boards which want to provide their own
* GPIO namespace and -operations (i.e. for example you have 8 GPIOs
* which are in part provided by spare Au1300 GPIO pins and in part by
* an external FPGA but you still want them to be accessible in linux
* as gpio0-7. The board can of course use the alchemy_gpioX_* functions
* as required).
*/
#ifndef CONFIG_GPIOLIB
#ifdef CONFIG_ALCHEMY_GPIOINT_AU1300
#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (4) */
static inline int gpio_direction_input(unsigned int gpio)
{
return au1300_gpio_direction_input(gpio);
}
static inline int gpio_direction_output(unsigned int gpio, int v)
{
return au1300_gpio_direction_output(gpio, v);
}
static inline int gpio_get_value(unsigned int gpio)
{
return au1300_gpio_get_value(gpio);
}
static inline void gpio_set_value(unsigned int gpio, int v)
{
au1300_gpio_set_value(gpio, v);
}
static inline int gpio_get_value_cansleep(unsigned gpio)
{
return gpio_get_value(gpio);
}
static inline void gpio_set_value_cansleep(unsigned gpio, int value)
{
gpio_set_value(gpio, value);
}
static inline int gpio_is_valid(unsigned int gpio)
{
return au1300_gpio_is_valid(gpio);
}
static inline int gpio_cansleep(unsigned int gpio)
{
return au1300_gpio_cansleep(gpio);
}
static inline int gpio_to_irq(unsigned int gpio)
{
return au1300_gpio_to_irq(gpio);
}
static inline int irq_to_gpio(unsigned int irq)
{
return au1300_irq_to_gpio(irq);
}
static inline int gpio_request(unsigned int gpio, const char *label)
{
return 0;
}
static inline int gpio_request_one(unsigned gpio,
unsigned long flags, const char *label)
{
return 0;
}
static inline int gpio_request_array(struct gpio *array, size_t num)
{
return 0;
}
static inline void gpio_free(unsigned gpio)
{
}
static inline void gpio_free_array(struct gpio *array, size_t num)
{
}
static inline int gpio_set_debounce(unsigned gpio, unsigned debounce)
{
return -ENOSYS;
}
static inline void gpio_unexport(unsigned gpio)
{
}
static inline int gpio_export(unsigned gpio, bool direction_may_change)
{
return -ENOSYS;
}
static inline int gpio_sysfs_set_active_low(unsigned gpio, int value)
{
return -ENOSYS;
}
static inline int gpio_export_link(struct device *dev, const char *name,
unsigned gpio)
{
return -ENOSYS;
}
#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */
#endif /* CONFIG_ALCHEMY_GPIOINT_AU1300 */
#endif /* CONFIG GPIOLIB */
#endif /* _GPIO_AU1300_H_ */
arch/mips/include/asm/mach-bcm47xx/bcm47xx.h
View file @ 09a31a7e
......@@ -10,6 +10,7 @@
#include <linux/bcma/bcma.h>
#include <linux/bcma/bcma_soc.h>
#include <linux/bcm47xx_nvram.h>
#include <linux/bcm47xx_sprom.h>
enum bcm47xx_bus_type {
#ifdef CONFIG_BCM47XX_SSB
......@@ -32,9 +33,6 @@ union bcm47xx_bus {
extern union bcm47xx_bus bcm47xx_bus;
extern enum bcm47xx_bus_type bcm47xx_bus_type;
void bcm47xx_fill_sprom(struct ssb_sprom *sprom, const char *prefix,
bool fallback);
void bcm47xx_set_system_type(u16 chip_id);
#endif /* __ASM_BCM47XX_H */
arch/mips/include/asm/mach-cavium-octeon/war.h deleted 100644 → 0
View file @ 847d4287
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
* Copyright (C) 2008 Cavium Networks <support@caviumnetworks.com>
*/
#ifndef __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
#define __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0
#define MIPS_CACHE_SYNC_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
#define CAVIUM_OCTEON_DCACHE_PREFETCH_WAR \
OCTEON_IS_MODEL(OCTEON_CN6XXX)
#endif /* __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H */
arch/mips/include/asm/mach-generic/irq.h
View file @ 09a31a7e
......@@ -9,7 +9,7 @@
#define __ASM_MACH_GENERIC_IRQ_H
#ifndef NR_IRQS
#define NR_IRQS 128
#define NR_IRQS 256
#endif
#ifdef CONFIG_I8259
......
arch/mips/include/asm/mach-generic/war.h deleted 100644 → 0
View file @ 847d4287
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
*/
#ifndef __ASM_MACH_GENERIC_WAR_H
#define __ASM_MACH_GENERIC_WAR_H
#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0
#define MIPS_CACHE_SYNC_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MACH_GENERIC_WAR_H */
arch/mips/include/asm/mach-ip22/war.h deleted 100644 → 0
View file @ 847d4287
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
*/
#ifndef __ASM_MIPS_MACH_IP22_WAR_H
#define __ASM_MIPS_MACH_IP22_WAR_H
/*
* R4600 CPU modules for the Indy come with both V1.7 and V2.0 processors.
*/
#define R4600_V1_INDEX_ICACHEOP_WAR 1
#define R4600_V1_HIT_CACHEOP_WAR 1
#define R4600_V2_HIT_CACHEOP_WAR 1
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0
#define MIPS_CACHE_SYNC_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MIPS_MACH_IP22_WAR_H */
arch/mips/include/asm/mach-ip27/kmalloc.h deleted 100644 → 0
View file @ 847d4287
#ifndef __ASM_MACH_IP27_KMALLOC_H
#define __ASM_MACH_IP27_KMALLOC_H
/*
* All happy, no need to define ARCH_DMA_MINALIGN
*/
#endif /* __ASM_MACH_IP27_KMALLOC_H */
arch/mips/include/asm/mach-ip27/war.h deleted 100644 → 0
View file @ 847d4287
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
*/
#ifndef __ASM_MIPS_MACH_IP27_WAR_H
#define __ASM_MIPS_MACH_IP27_WAR_H
#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0
#define MIPS_CACHE_SYNC_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 1
#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MIPS_MACH_IP27_WAR_H */
arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h
View file @ 09a31a7e
......@@ -25,7 +25,7 @@
#define cpu_has_mcheck 0
#define cpu_has_ejtag 0
#define cpu_has_llsc 1
#define cpu_has_llsc 0
#define cpu_has_vtag_icache 0
#define cpu_has_dc_aliases 0 /* see probe_pcache() */
#define cpu_has_ic_fills_f_dc 0
......
arch/mips/include/asm/mach-ip28/war.h deleted 100644 → 0
View file @ 847d4287
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
*/
#ifndef __ASM_MIPS_MACH_IP28_WAR_H
#define __ASM_MIPS_MACH_IP28_WAR_H
#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0
#define MIPS_CACHE_SYNC_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 1
#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MIPS_MACH_IP28_WAR_H */
arch/mips/include/asm/mach-ip30/irq.h deleted 100644 → 0
View file @ 847d4287
/* SPDX-License-Identifier: GPL-2.0 */
/*
* HEART IRQ defines
*
* Copyright (C) 2009 Johannes Dickgreber <tanzy@gmx.de>
* 2014-2016 Joshua Kinard <kumba@gentoo.org>
*
*/
#ifndef __ASM_MACH_IP30_IRQ_H
#define __ASM_MACH_IP30_IRQ_H
/*
* HEART has 64 hardware interrupts, but use 128 to leave room for a few
* software interrupts as well (such as the CPU timer interrupt.
*/
#define NR_IRQS 128
extern void __init ip30_install_ipi(void);
/*
* HEART has 64 interrupt vectors available to it, subdivided into five
* priority levels. They are numbered 0 to 63.
*/
#define HEART_NUM_IRQS 64
/*
* These are the five interrupt priority levels and their corresponding
* CPU IPx interrupt pins.
*
* Level 4 - Error Interrupts.
* Level 3 - HEART timer interrupt.
* Level 2 - CPU IPI, CPU debug, power putton, general device interrupts.
* Level 1 - General device interrupts.
* Level 0 - General device GFX flow control interrupts.
*/
#define HEART_L4_INT_MASK 0xfff8000000000000ULL /* IP6 */
#define HEART_L3_INT_MASK 0x0004000000000000ULL /* IP5 */
#define HEART_L2_INT_MASK 0x0003ffff00000000ULL /* IP4 */
#define HEART_L1_INT_MASK 0x00000000ffff0000ULL /* IP3 */
#define HEART_L0_INT_MASK 0x000000000000ffffULL /* IP2 */
/* HEART L0 Interrupts (Low Priority) */
#define HEART_L0_INT_GENERIC 0
#define HEART_L0_INT_FLOW_CTRL_HWTR_0 1
#define HEART_L0_INT_FLOW_CTRL_HWTR_1 2
/* HEART L2 Interrupts (High Priority) */
#define HEART_L2_INT_RESCHED_CPU_0 46
#define HEART_L2_INT_RESCHED_CPU_1 47
#define HEART_L2_INT_CALL_CPU_0 48
#define HEART_L2_INT_CALL_CPU_1 49
/* HEART L3 Interrupts (Compare/Counter Timer) */
#define HEART_L3_INT_TIMER 50
/* HEART L4 Interrupts (Errors) */
#define HEART_L4_INT_XWID_ERR_9 51
#define HEART_L4_INT_XWID_ERR_A 52
#define HEART_L4_INT_XWID_ERR_B 53
#define HEART_L4_INT_XWID_ERR_C 54
#define HEART_L4_INT_XWID_ERR_D 55
#define HEART_L4_INT_XWID_ERR_E 56
#define HEART_L4_INT_XWID_ERR_F 57
#define HEART_L4_INT_XWID_ERR_XBOW 58
#define HEART_L4_INT_CPU_BUS_ERR_0 59
#define HEART_L4_INT_CPU_BUS_ERR_1 60
#define HEART_L4_INT_CPU_BUS_ERR_2 61
#define HEART_L4_INT_CPU_BUS_ERR_3 62
#define HEART_L4_INT_HEART_EXCP 63
/*
* Power Switch is wired via BaseIO BRIDGE slot #6.
*
* ACFail is wired via BaseIO BRIDGE slot #7.
*/
#define IP30_POWER_IRQ HEART_L2_INT_POWER_BTN
#include <asm/mach-generic/irq.h>
#define IP30_HEART_L0_IRQ (MIPS_CPU_IRQ_BASE + 2)
#define IP30_HEART_L1_IRQ (MIPS_CPU_IRQ_BASE + 3)
#define IP30_HEART_L2_IRQ (MIPS_CPU_IRQ_BASE + 4)
#define IP30_HEART_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 5)
#define IP30_HEART_ERR_IRQ (MIPS_CPU_IRQ_BASE + 6)
#endif /* __ASM_MACH_IP30_IRQ_H */
arch/mips/include/asm/mach-ip30/war.h deleted 100644 → 0
View file @ 847d4287
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
*/
#ifndef __ASM_MIPS_MACH_IP30_WAR_H
#define __ASM_MIPS_MACH_IP30_WAR_H
#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0
#define MIPS_CACHE_SYNC_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#ifdef CONFIG_CPU_R10000
#define R10000_LLSC_WAR 1
#else
#define R10000_LLSC_WAR 0
#endif
#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MIPS_MACH_IP30_WAR_H */
arch/mips/include/asm/mach-ip32/war.h deleted 100644 → 0
View file @ 847d4287
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
*/
#ifndef __ASM_MIPS_MACH_IP32_WAR_H
#define __ASM_MIPS_MACH_IP32_WAR_H
#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0
#define MIPS_CACHE_SYNC_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 1
#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MIPS_MACH_IP32_WAR_H */
arch/mips/include/asm/mach-jz4740/irq.h deleted 100644 → 0
View file @ 847d4287
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
* JZ4740 IRQ definitions
*/
#ifndef __ASM_MACH_JZ4740_IRQ_H__
#define __ASM_MACH_JZ4740_IRQ_H__
#define MIPS_CPU_IRQ_BASE 0
#define NR_IRQS 256
#endif
arch/mips/include/asm/mach-loongson2ef/mc146818rtc.h deleted 100644 → 0
View file @ 847d4287
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1998, 2001, 03, 07 by Ralf Baechle (ralf@linux-mips.org)
*
* RTC routines for PC style attached Dallas chip.
*/
#ifndef __ASM_MACH_LOONGSON2EF_MC146818RTC_H
#define __ASM_MACH_LOONGSON2EF_MC146818RTC_H
#include <linux/io.h>
#define RTC_PORT(x) (0x70 + (x))
#define RTC_IRQ 8
static inline unsigned char CMOS_READ(unsigned long addr)
{
outb_p(addr, RTC_PORT(0));
return inb_p(RTC_PORT(1));
}
static inline void CMOS_WRITE(unsigned char data, unsigned long addr)
{
outb_p(addr, RTC_PORT(0));
outb_p(data, RTC_PORT(1));
}
#define RTC_ALWAYS_BCD 0
#ifndef mc146818_decode_year
#define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1970)
#endif
#endif /* __ASM_MACH_LOONGSON2EF_MC146818RTC_H */
arch/mips/include/asm/mach-loongson64/irq.h
View file @ 09a31a7e
......@@ -5,7 +5,8 @@
/* cpu core interrupt numbers */
#define NR_IRQS_LEGACY 16
#define NR_MIPS_CPU_IRQS 8
#define NR_IRQS (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256)
#define NR_MAX_CHAINED_IRQS 40 /* Chained IRQs means those not directly used by devices */
#define NR_IRQS (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + NR_MAX_CHAINED_IRQS + 256)
#define MIPS_CPU_IRQ_BASE NR_IRQS_LEGACY
......
arch/mips/include/asm/mach-loongson64/mmzone.h
View file @ 09a31a7e
......@@ -10,13 +10,9 @@
#define _ASM_MACH_LOONGSON64_MMZONE_H
#define NODE_ADDRSPACE_SHIFT 44
#define NODE0_ADDRSPACE_OFFSET 0x000000000000UL
#define NODE1_ADDRSPACE_OFFSET 0x100000000000UL
#define NODE2_ADDRSPACE_OFFSET 0x200000000000UL
#define NODE3_ADDRSPACE_OFFSET 0x300000000000UL
#define pa_to_nid(addr) (((addr) & 0xf00000000000) >> NODE_ADDRSPACE_SHIFT)
#define nid_to_addrbase(nid) ((nid) << NODE_ADDRSPACE_SHIFT)
#define nid_to_addrbase(nid) ((unsigned long)(nid) << NODE_ADDRSPACE_SHIFT)
extern struct pglist_data *__node_data[];
......
arch/mips/include/asm/mach-malta/malta-dtshim.h deleted 100644 → 0
View file @ 847d4287
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2015 Imagination Technologies
* Author: Paul Burton <paul.burton@mips.com>
*/
#ifndef __MIPS_MALTA_DTSHIM_H__
#define __MIPS_MALTA_DTSHIM_H__
#include <linux/init.h>
#ifdef CONFIG_MIPS_MALTA
extern void __init *malta_dt_shim(void *fdt);
#else /* !CONFIG_MIPS_MALTA */
static inline void *malta_dt_shim(void *fdt)
{
return fdt;
}
#endif /* !CONFIG_MIPS_MALTA */
#endif /* __MIPS_MALTA_DTSHIM_H__ */
arch/mips/include/asm/mach-malta/malta-pm.h deleted 100644 → 0
View file @ 847d4287
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2014 Imagination Technologies
* Author: Paul Burton <paul.burton@mips.com>
*/
#ifndef __ASM_MIPS_MACH_MALTA_PM_H__
#define __ASM_MIPS_MACH_MALTA_PM_H__
#include <asm/mips-boards/piix4.h>
#ifdef CONFIG_MIPS_MALTA_PM
/**
* mips_pm_suspend - enter a suspend state
* @state: the state to enter, one of PIIX4_FUNC3IO_PMCNTRL_SUS_TYP_*
*
* Enters a suspend state via the Malta's PIIX4. If the state to be entered
* is one which loses context (eg. SOFF) then this function will never
* return.
*/
extern int mips_pm_suspend(unsigned state);
#else /* !CONFIG_MIPS_MALTA_PM */
static inline int mips_pm_suspend(unsigned state)
{
return -EINVAL;
}
#endif /* !CONFIG_MIPS_MALTA_PM */
#endif /* __ASM_MIPS_MACH_MALTA_PM_H__ */
arch/mips/include/asm/mach-malta/war.h deleted 100644 → 0
View file @ 847d4287
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
*/
#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
#define __ASM_MIPS_MACH_MIPS_WAR_H
#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 1
#define MIPS_CACHE_SYNC_WAR 1
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 1
#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */
arch/mips/include/asm/mach-paravirt/cpu-feature-overrides.h deleted 100644 → 0
View file @ 847d4287
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2013 Cavium, Inc.
*/
#ifndef __ASM_MACH_PARAVIRT_CPU_FEATURE_OVERRIDES_H
#define __ASM_MACH_PARAVIRT_CPU_FEATURE_OVERRIDES_H
#define cpu_has_4kex 1
#define cpu_has_3k_cache 0
#define cpu_has_tx39_cache 0
#define cpu_has_counter 1
#define cpu_has_llsc 1
/*
* We Disable LL/SC on non SMP systems as it is faster to disable
* interrupts for atomic access than a LL/SC.
*/
#ifdef CONFIG_SMP
# define kernel_uses_llsc 1
#else
# define kernel_uses_llsc 0
#endif
#ifdef CONFIG_CPU_CAVIUM_OCTEON
#define cpu_dcache_line_size() 128
#define cpu_icache_line_size() 128
#define cpu_has_octeon_cache 1
#define cpu_has_4k_cache 0
#else
#define cpu_has_4k_cache 1
#endif
#endif /* __ASM_MACH_PARAVIRT_CPU_FEATURE_OVERRIDES_H */
arch/mips/include/asm/mach-paravirt/irq.h deleted 100644 → 0
View file @ 847d4287
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2013 Cavium, Inc.
*/
#ifndef __ASM_MACH_PARAVIRT_IRQ_H__
#define __ASM_MACH_PARAVIRT_IRQ_H__
#define NR_IRQS 64
#define MIPS_CPU_IRQ_BASE 1
#define MIPS_IRQ_PCIA (MIPS_CPU_IRQ_BASE + 8)
#define MIPS_IRQ_MBOX0 (MIPS_CPU_IRQ_BASE + 32)
#define MIPS_IRQ_MBOX1 (MIPS_CPU_IRQ_BASE + 33)
#endif /* __ASM_MACH_PARAVIRT_IRQ_H__ */
arch/mips/include/asm/mach-paravirt/kernel-entry-init.h deleted 100644 → 0
View file @ 847d4287
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2013 Cavium, Inc
*/
#ifndef __ASM_MACH_PARAVIRT_KERNEL_ENTRY_H
#define __ASM_MACH_PARAVIRT_KERNEL_ENTRY_H
#define CP0_EBASE $15, 1
.macro kernel_entry_setup
#ifdef CONFIG_SMP
mfc0 t0, CP0_EBASE
andi t0, t0, 0x3ff # CPUNum
beqz t0, 1f
# CPUs other than zero goto smp_bootstrap
j smp_bootstrap
#endif /* CONFIG_SMP */
1:
.endm
/*
* Do SMP slave processor setup necessary before we can safely execute
* C code.
*/
.macro smp_slave_setup
mfc0 t0, CP0_EBASE
andi t0, t0, 0x3ff # CPUNum
slti t1, t0, NR_CPUS
bnez t1, 1f
2:
di
wait
b 2b # Unknown CPU, loop forever.
1:
PTR_LA t1, paravirt_smp_sp
PTR_SLL t0, PTR_SCALESHIFT
PTR_ADDU t1, t1, t0
3:
PTR_L sp, 0(t1)
beqz sp, 3b # Spin until told to proceed.
PTR_LA t1, paravirt_smp_gp
PTR_ADDU t1, t1, t0
sync
PTR_L gp, 0(t1)
.endm
#endif /* __ASM_MACH_PARAVIRT_KERNEL_ENTRY_H */
arch/mips/include/asm/mach-pnx833x/gpio.h deleted 100644 → 0
View file @ 847d4287
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* gpio.h: GPIO Support for PNX833X.
*
* Copyright 2008 NXP Semiconductors
* Chris Steel <chris.steel@nxp.com>
* Daniel Laird <daniel.j.laird@nxp.com>
*/
#ifndef __ASM_MIPS_MACH_PNX833X_GPIO_H
#define __ASM_MIPS_MACH_PNX833X_GPIO_H
/* BIG FAT WARNING: races danger!
No protections exist here. Current users are only early init code,
when locking is not needed because no concurrency yet exists there,
and GPIO IRQ dispatcher, which does locking.
However, if many uses will ever happen, proper locking will be needed
- including locking between different uses
*/
#include <asm/mach-pnx833x/pnx833x.h>
#define SET_REG_BIT(reg, bit) do { (reg |= (1 << (bit))); } while (0)
#define CLEAR_REG_BIT(reg, bit) do { (reg &= ~(1 << (bit))); } while (0)
/* Initialize GPIO to a known state */
static inline void pnx833x_gpio_init(void)
{
PNX833X_PIO_DIR = 0;
PNX833X_PIO_DIR2 = 0;
PNX833X_PIO_SEL = 0;
PNX833X_PIO_SEL2 = 0;
PNX833X_PIO_INT_EDGE = 0;
PNX833X_PIO_INT_HI = 0;
PNX833X_PIO_INT_LO = 0;
/* clear any GPIO interrupt requests */
PNX833X_PIO_INT_CLEAR = 0xffff;
PNX833X_PIO_INT_CLEAR = 0;
PNX833X_PIO_INT_ENABLE = 0;
}
/* Select GPIO direction for a pin */
static inline void pnx833x_gpio_select_input(unsigned int pin)
{
if (pin < 32)
CLEAR_REG_BIT(PNX833X_PIO_DIR, pin);
else
CLEAR_REG_BIT(PNX833X_PIO_DIR2, pin & 31);
}
static inline void pnx833x_gpio_select_output(unsigned int pin)
{
if (pin < 32)
SET_REG_BIT(PNX833X_PIO_DIR, pin);
else
SET_REG_BIT(PNX833X_PIO_DIR2, pin & 31);
}
/* Select GPIO or alternate function for a pin */
static inline void pnx833x_gpio_select_function_io(unsigned int pin)
{
if (pin < 32)
CLEAR_REG_BIT(PNX833X_PIO_SEL, pin);
else
CLEAR_REG_BIT(PNX833X_PIO_SEL2, pin & 31);
}
static inline void pnx833x_gpio_select_function_alt(unsigned int pin)
{
if (pin < 32)
SET_REG_BIT(PNX833X_PIO_SEL, pin);
else
SET_REG_BIT(PNX833X_PIO_SEL2, pin & 31);
}
/* Read GPIO pin */
static inline int pnx833x_gpio_read(unsigned int pin)
{
if (pin < 32)
return (PNX833X_PIO_IN >> pin) & 1;
else
return (PNX833X_PIO_IN2 >> (pin & 31)) & 1;
}
/* Write GPIO pin */
static inline void pnx833x_gpio_write(unsigned int val, unsigned int pin)
{
if (pin < 32) {
if (val)
SET_REG_BIT(PNX833X_PIO_OUT, pin);
else
CLEAR_REG_BIT(PNX833X_PIO_OUT, pin);
} else {
if (val)
SET_REG_BIT(PNX833X_PIO_OUT2, pin & 31);
else
CLEAR_REG_BIT(PNX833X_PIO_OUT2, pin & 31);
}
}
/* Configure GPIO interrupt */
#define GPIO_INT_NONE 0
#define GPIO_INT_LEVEL_LOW 1
#define GPIO_INT_LEVEL_HIGH 2
#define GPIO_INT_EDGE_RISING 3
#define GPIO_INT_EDGE_FALLING 4
#define GPIO_INT_EDGE_BOTH 5
static inline void pnx833x_gpio_setup_irq(int when, unsigned int pin)
{
switch (when) {
case GPIO_INT_LEVEL_LOW:
CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin);
SET_REG_BIT(PNX833X_PIO_INT_LO, pin);
break;
case GPIO_INT_LEVEL_HIGH:
CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
SET_REG_BIT(PNX833X_PIO_INT_HI, pin);
CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin);
break;
case GPIO_INT_EDGE_RISING:
SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
SET_REG_BIT(PNX833X_PIO_INT_HI, pin);
CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin);
break;
case GPIO_INT_EDGE_FALLING:
SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin);
SET_REG_BIT(PNX833X_PIO_INT_LO, pin);
break;
case GPIO_INT_EDGE_BOTH:
SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
SET_REG_BIT(PNX833X_PIO_INT_HI, pin);
SET_REG_BIT(PNX833X_PIO_INT_LO, pin);
break;
default:
CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin);
CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin);
break;
}
}
/* Enable/disable GPIO interrupt */
static inline void pnx833x_gpio_enable_irq(unsigned int pin)
{
SET_REG_BIT(PNX833X_PIO_INT_ENABLE, pin);
}
static inline void pnx833x_gpio_disable_irq(unsigned int pin)
{
CLEAR_REG_BIT(PNX833X_PIO_INT_ENABLE, pin);
}
/* Clear GPIO interrupt request */
static inline void pnx833x_gpio_clear_irq(unsigned int pin)
{
SET_REG_BIT(PNX833X_PIO_INT_CLEAR, pin);
CLEAR_REG_BIT(PNX833X_PIO_INT_CLEAR, pin);
}
#endif
arch/mips/include/asm/mach-pnx833x/irq-mapping.h deleted 100644 → 0
View file @ 847d4287
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* irq.h: IRQ mappings for PNX833X.
*
* Copyright 2008 NXP Semiconductors
* Chris Steel <chris.steel@nxp.com>
* Daniel Laird <daniel.j.laird@nxp.com>
*/
#ifndef __ASM_MIPS_MACH_PNX833X_IRQ_MAPPING_H
#define __ASM_MIPS_MACH_PNX833X_IRQ_MAPPING_H
/*
* The "IRQ numbers" are completely virtual.
*
* In PNX8330/1, we have 48 interrupt lines, numbered from 1 to 48.
* Let's use numbers 1..48 for PIC interrupts, number 0 for timer interrupt,
* numbers 49..64 for (virtual) GPIO interrupts.
*
* In PNX8335, we have 57 interrupt lines, numbered from 1 to 57,
* connected to PIC, which uses core hardware interrupt 2, and also
* a timer interrupt through hardware interrupt 5.
* Let's use numbers 1..64 for PIC interrupts, number 0 for timer interrupt,
* numbers 65..80 for (virtual) GPIO interrupts.
*
*/
#include <irq.h>
#define PNX833X_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7)
/* Interrupts supported by PIC */
#define PNX833X_PIC_I2C0_INT (PNX833X_PIC_IRQ_BASE + 1)
#define PNX833X_PIC_I2C1_INT (PNX833X_PIC_IRQ_BASE + 2)
#define PNX833X_PIC_UART0_INT (PNX833X_PIC_IRQ_BASE + 3)
#define PNX833X_PIC_UART1_INT (PNX833X_PIC_IRQ_BASE + 4)
#define PNX833X_PIC_TS_IN0_DV_INT (PNX833X_PIC_IRQ_BASE + 5)
#define PNX833X_PIC_TS_IN0_DMA_INT (PNX833X_PIC_IRQ_BASE + 6)
#define PNX833X_PIC_GPIO_INT (PNX833X_PIC_IRQ_BASE + 7)
#define PNX833X_PIC_AUDIO_DEC_INT (PNX833X_PIC_IRQ_BASE + 8)
#define PNX833X_PIC_VIDEO_DEC_INT (PNX833X_PIC_IRQ_BASE + 9)
#define PNX833X_PIC_CONFIG_INT (PNX833X_PIC_IRQ_BASE + 10)
#define PNX833X_PIC_AOI_INT (PNX833X_PIC_IRQ_BASE + 11)
#define PNX833X_PIC_SYNC_INT (PNX833X_PIC_IRQ_BASE + 12)
#define PNX8330_PIC_SPU_INT (PNX833X_PIC_IRQ_BASE + 13)
#define PNX8335_PIC_SATA_INT (PNX833X_PIC_IRQ_BASE + 13)
#define PNX833X_PIC_OSD_INT (PNX833X_PIC_IRQ_BASE + 14)
#define PNX833X_PIC_DISP1_INT (PNX833X_PIC_IRQ_BASE + 15)
#define PNX833X_PIC_DEINTERLACER_INT (PNX833X_PIC_IRQ_BASE + 16)
#define PNX833X_PIC_DISPLAY2_INT (PNX833X_PIC_IRQ_BASE + 17)
#define PNX833X_PIC_VC_INT (PNX833X_PIC_IRQ_BASE + 18)
#define PNX833X_PIC_SC_INT (PNX833X_PIC_IRQ_BASE + 19)
#define PNX833X_PIC_IDE_INT (PNX833X_PIC_IRQ_BASE + 20)
#define PNX833X_PIC_IDE_DMA_INT (PNX833X_PIC_IRQ_BASE + 21)
#define PNX833X_PIC_TS_IN1_DV_INT (PNX833X_PIC_IRQ_BASE + 22)
#define PNX833X_PIC_TS_IN1_DMA_INT (PNX833X_PIC_IRQ_BASE + 23)
#define PNX833X_PIC_SGDX_DMA_INT (PNX833X_PIC_IRQ_BASE + 24)
#define PNX833X_PIC_TS_OUT_INT (PNX833X_PIC_IRQ_BASE + 25)
#define PNX833X_PIC_IR_INT (PNX833X_PIC_IRQ_BASE + 26)
#define PNX833X_PIC_VMSP1_INT (PNX833X_PIC_IRQ_BASE + 27)
#define PNX833X_PIC_VMSP2_INT (PNX833X_PIC_IRQ_BASE + 28)
#define PNX833X_PIC_PIBC_INT (PNX833X_PIC_IRQ_BASE + 29)
#define PNX833X_PIC_TS_IN0_TRD_INT (PNX833X_PIC_IRQ_BASE + 30)
#define PNX833X_PIC_SGDX_TPD_INT (PNX833X_PIC_IRQ_BASE + 31)
#define PNX833X_PIC_USB_INT (PNX833X_PIC_IRQ_BASE + 32)
#define PNX833X_PIC_TS_IN1_TRD_INT (PNX833X_PIC_IRQ_BASE + 33)
#define PNX833X_PIC_CLOCK_INT (PNX833X_PIC_IRQ_BASE + 34)
#define PNX833X_PIC_SGDX_PARSER_INT (PNX833X_PIC_IRQ_BASE + 35)
#define PNX833X_PIC_VMSP_DMA_INT (PNX833X_PIC_IRQ_BASE + 36)
#if defined(CONFIG_SOC_PNX8335)
#define PNX8335_PIC_MIU_INT (PNX833X_PIC_IRQ_BASE + 37)
#define PNX8335_PIC_AVCHIP_IRQ_INT (PNX833X_PIC_IRQ_BASE + 38)
#define PNX8335_PIC_SYNC_HD_INT (PNX833X_PIC_IRQ_BASE + 39)
#define PNX8335_PIC_DISP_HD_INT (PNX833X_PIC_IRQ_BASE + 40)
#define PNX8335_PIC_DISP_SCALER_INT (PNX833X_PIC_IRQ_BASE + 41)
#define PNX8335_PIC_OSD_HD1_INT (PNX833X_PIC_IRQ_BASE + 42)
#define PNX8335_PIC_DTL_WRITER_Y_INT (PNX833X_PIC_IRQ_BASE + 43)
#define PNX8335_PIC_DTL_WRITER_C_INT (PNX833X_PIC_IRQ_BASE + 44)
#define PNX8335_PIC_DTL_EMULATOR_Y_IR_INT (PNX833X_PIC_IRQ_BASE + 45)
#define PNX8335_PIC_DTL_EMULATOR_C_IR_INT (PNX833X_PIC_IRQ_BASE + 46)
#define PNX8335_PIC_DENC_TTX_INT (PNX833X_PIC_IRQ_BASE + 47)
#define PNX8335_PIC_MMI_SIF0_INT (PNX833X_PIC_IRQ_BASE + 48)
#define PNX8335_PIC_MMI_SIF1_INT (PNX833X_PIC_IRQ_BASE + 49)
#define PNX8335_PIC_MMI_CDMMU_INT (PNX833X_PIC_IRQ_BASE + 50)
#define PNX8335_PIC_PIBCS_INT (PNX833X_PIC_IRQ_BASE + 51)
#define PNX8335_PIC_ETHERNET_INT (PNX833X_PIC_IRQ_BASE + 52)
#define PNX8335_PIC_VMSP1_0_INT (PNX833X_PIC_IRQ_BASE + 53)
#define PNX8335_PIC_VMSP1_1_INT (PNX833X_PIC_IRQ_BASE + 54)
#define PNX8335_PIC_VMSP1_DMA_INT (PNX833X_PIC_IRQ_BASE + 55)
#define PNX8335_PIC_TDGR_DE_INT (PNX833X_PIC_IRQ_BASE + 56)
#define PNX8335_PIC_IR1_IRQ_INT (PNX833X_PIC_IRQ_BASE + 57)
#endif
/* GPIO interrupts */
#define PNX833X_GPIO_0_INT (PNX833X_GPIO_IRQ_BASE + 0)
#define PNX833X_GPIO_1_INT (PNX833X_GPIO_IRQ_BASE + 1)
#define PNX833X_GPIO_2_INT (PNX833X_GPIO_IRQ_BASE + 2)
#define PNX833X_GPIO_3_INT (PNX833X_GPIO_IRQ_BASE + 3)
#define PNX833X_GPIO_4_INT (PNX833X_GPIO_IRQ_BASE + 4)
#define PNX833X_GPIO_5_INT (PNX833X_GPIO_IRQ_BASE + 5)
#define PNX833X_GPIO_6_INT (PNX833X_GPIO_IRQ_BASE + 6)
#define PNX833X_GPIO_7_INT (PNX833X_GPIO_IRQ_BASE + 7)
#define PNX833X_GPIO_8_INT (PNX833X_GPIO_IRQ_BASE + 8)
#define PNX833X_GPIO_9_INT (PNX833X_GPIO_IRQ_BASE + 9)
#define PNX833X_GPIO_10_INT (PNX833X_GPIO_IRQ_BASE + 10)
#define PNX833X_GPIO_11_INT (PNX833X_GPIO_IRQ_BASE + 11)
#define PNX833X_GPIO_12_INT (PNX833X_GPIO_IRQ_BASE + 12)
#define PNX833X_GPIO_13_INT (PNX833X_GPIO_IRQ_BASE + 13)
#define PNX833X_GPIO_14_INT (PNX833X_GPIO_IRQ_BASE + 14)
#define PNX833X_GPIO_15_INT (PNX833X_GPIO_IRQ_BASE + 15)
#endif
arch/mips/include/asm/mach-pnx833x/irq.h deleted 100644 → 0
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* irq.h: IRQ mappings for PNX833X.
*
* Copyright 2008 NXP Semiconductors
* Chris Steel <chris.steel@nxp.com>
* Daniel Laird <daniel.j.laird@nxp.com>
*/
#ifndef __ASM_MIPS_MACH_PNX833X_IRQ_H
#define __ASM_MIPS_MACH_PNX833X_IRQ_H
/*
* The "IRQ numbers" are completely virtual.
*
* In PNX8330/1, we have 48 interrupt lines, numbered from 1 to 48.
* Let's use numbers 1..48 for PIC interrupts, number 0 for timer interrupt,
* numbers 49..64 for (virtual) GPIO interrupts.
*
* In PNX8335, we have 57 interrupt lines, numbered from 1 to 57,
* connected to PIC, which uses core hardware interrupt 2, and also
* a timer interrupt through hardware interrupt 5.
* Let's use numbers 1..64 for PIC interrupts, number 0 for timer interrupt,
* numbers 65..80 for (virtual) GPIO interrupts.
*
*/
#if defined(CONFIG_SOC_PNX8335)
#define PNX833X_PIC_NUM_IRQ 58
#else
#define PNX833X_PIC_NUM_IRQ 37
#endif
#define MIPS_CPU_NUM_IRQ 8
#define PNX833X_GPIO_NUM_IRQ 16
#define MIPS_CPU_IRQ_BASE 0
#define PNX833X_PIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + MIPS_CPU_NUM_IRQ)
#define PNX833X_GPIO_IRQ_BASE (PNX833X_PIC_IRQ_BASE + PNX833X_PIC_NUM_IRQ)
#define NR_IRQS (MIPS_CPU_NUM_IRQ + PNX833X_PIC_NUM_IRQ + PNX833X_GPIO_NUM_IRQ)
#endif
arch/mips/include/asm/mach-pnx833x/pnx833x.h deleted 100644 → 0
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* pnx833x.h: Register mappings for PNX833X.
*
* Copyright 2008 NXP Semiconductors
* Chris Steel <chris.steel@nxp.com>
* Daniel Laird <daniel.j.laird@nxp.com>
*/
#ifndef __ASM_MIPS_MACH_PNX833X_PNX833X_H
#define __ASM_MIPS_MACH_PNX833X_PNX833X_H
/* All regs are accessed in KSEG1 */
#define PNX833X_BASE (0xa0000000ul + 0x17E00000ul)
#define PNX833X_REG(offs) (*((volatile unsigned long *)(PNX833X_BASE + offs)))
/* Registers are named exactly as in PNX833X docs, just with PNX833X_ prefix */
/* Read access to multibit fields */
#define PNX833X_BIT(val, reg, field) ((val) & PNX833X_##reg##_##field)
#define PNX833X_REGBIT(reg, field) PNX833X_BIT(PNX833X_##reg, reg, field)
/* Use PNX833X_FIELD to extract a field from val */
#define PNX_FIELD(cpu, val, reg, field) \
(((val) & PNX##cpu##_##reg##_##field##_MASK) >> \
PNX##cpu##_##reg##_##field##_SHIFT)
#define PNX833X_FIELD(val, reg, field) PNX_FIELD(833X, val, reg, field)
#define PNX8330_FIELD(val, reg, field) PNX_FIELD(8330, val, reg, field)
#define PNX8335_FIELD(val, reg, field) PNX_FIELD(8335, val, reg, field)
/* Use PNX833X_REGFIELD to extract a field from a register */
#define PNX833X_REGFIELD(reg, field) PNX833X_FIELD(PNX833X_##reg, reg, field)
#define PNX8330_REGFIELD(reg, field) PNX8330_FIELD(PNX8330_##reg, reg, field)
#define PNX8335_REGFIELD(reg, field) PNX8335_FIELD(PNX8335_##reg, reg, field)
#define PNX_WRITEFIELD(cpu, val, reg, field) \
(PNX##cpu##_##reg = (PNX##cpu##_##reg & ~(PNX##cpu##_##reg##_##field##_MASK)) | \
((val) << PNX##cpu##_##reg##_##field##_SHIFT))
#define PNX833X_WRITEFIELD(val, reg, field) \
PNX_WRITEFIELD(833X, val, reg, field)
#define PNX8330_WRITEFIELD(val, reg, field) \
PNX_WRITEFIELD(8330, val, reg, field)
#define PNX8335_WRITEFIELD(val, reg, field) \
PNX_WRITEFIELD(8335, val, reg, field)
/* Macros to detect CPU type */
#define PNX833X_CONFIG_MODULE_ID PNX833X_REG(0x7FFC)
#define PNX833X_CONFIG_MODULE_ID_MAJREV_MASK 0x0000f000
#define PNX833X_CONFIG_MODULE_ID_MAJREV_SHIFT 12
#define PNX8330_CONFIG_MODULE_MAJREV 4
#define PNX8335_CONFIG_MODULE_MAJREV 5
#define CPU_IS_PNX8330 (PNX833X_REGFIELD(CONFIG_MODULE_ID, MAJREV) == \
PNX8330_CONFIG_MODULE_MAJREV)
#define CPU_IS_PNX8335 (PNX833X_REGFIELD(CONFIG_MODULE_ID, MAJREV) == \
PNX8335_CONFIG_MODULE_MAJREV)
#define PNX833X_RESET_CONTROL PNX833X_REG(0x8004)
#define PNX833X_RESET_CONTROL_2 PNX833X_REG(0x8014)
#define PNX833X_PIC_REG(offs) PNX833X_REG(0x01000 + (offs))
#define PNX833X_PIC_INT_PRIORITY PNX833X_PIC_REG(0x0)
#define PNX833X_PIC_INT_SRC PNX833X_PIC_REG(0x4)
#define PNX833X_PIC_INT_SRC_INT_SRC_MASK 0x00000FF8ul /* bits 11:3 */
#define PNX833X_PIC_INT_SRC_INT_SRC_SHIFT 3
#define PNX833X_PIC_INT_REG(irq) PNX833X_PIC_REG(0x10 + 4*(irq))
#define PNX833X_CLOCK_CPUCP_CTL PNX833X_REG(0x9228)
#define PNX833X_CLOCK_CPUCP_CTL_EXIT_RESET 0x00000002ul /* bit 1 */
#define PNX833X_CLOCK_CPUCP_CTL_DIV_CLOCK_MASK 0x00000018ul /* bits 4:3 */
#define PNX833X_CLOCK_CPUCP_CTL_DIV_CLOCK_SHIFT 3
#define PNX8335_CLOCK_PLL_CPU_CTL PNX833X_REG(0x9020)
#define PNX8335_CLOCK_PLL_CPU_CTL_FREQ_MASK 0x1f
#define PNX8335_CLOCK_PLL_CPU_CTL_FREQ_SHIFT 0
#define PNX833X_CONFIG_MUX PNX833X_REG(0x7004)
#define PNX833X_CONFIG_MUX_IDE_MUX 0x00000080 /* bit 7 */
#define PNX8330_CONFIG_POLYFUSE_7 PNX833X_REG(0x7040)
#define PNX8330_CONFIG_POLYFUSE_7_BOOT_MODE_MASK 0x00180000
#define PNX8330_CONFIG_POLYFUSE_7_BOOT_MODE_SHIFT 19
#define PNX833X_PIO_IN PNX833X_REG(0xF000)
#define PNX833X_PIO_OUT PNX833X_REG(0xF004)
#define PNX833X_PIO_DIR PNX833X_REG(0xF008)
#define PNX833X_PIO_SEL PNX833X_REG(0xF014)
#define PNX833X_PIO_INT_EDGE PNX833X_REG(0xF020)
#define PNX833X_PIO_INT_HI PNX833X_REG(0xF024)
#define PNX833X_PIO_INT_LO PNX833X_REG(0xF028)
#define PNX833X_PIO_INT_STATUS PNX833X_REG(0xFFE0)
#define PNX833X_PIO_INT_ENABLE PNX833X_REG(0xFFE4)
#define PNX833X_PIO_INT_CLEAR PNX833X_REG(0xFFE8)
#define PNX833X_PIO_IN2 PNX833X_REG(0xF05C)
#define PNX833X_PIO_OUT2 PNX833X_REG(0xF060)
#define PNX833X_PIO_DIR2 PNX833X_REG(0xF064)
#define PNX833X_PIO_SEL2 PNX833X_REG(0xF068)
#define PNX833X_UART0_PORTS_START (PNX833X_BASE + 0xB000)
#define PNX833X_UART0_PORTS_END (PNX833X_BASE + 0xBFFF)
#define PNX833X_UART1_PORTS_START (PNX833X_BASE + 0xC000)
#define PNX833X_UART1_PORTS_END (PNX833X_BASE + 0xCFFF)
#define PNX833X_USB_PORTS_START (PNX833X_BASE + 0x19000)
#define PNX833X_USB_PORTS_END (PNX833X_BASE + 0x19FFF)
#define PNX833X_CONFIG_USB PNX833X_REG(0x7008)
#define PNX833X_I2C0_PORTS_START (PNX833X_BASE + 0xD000)
#define PNX833X_I2C0_PORTS_END (PNX833X_BASE + 0xDFFF)
#define PNX833X_I2C1_PORTS_START (PNX833X_BASE + 0xE000)
#define PNX833X_I2C1_PORTS_END (PNX833X_BASE + 0xEFFF)
#define PNX833X_IDE_PORTS_START (PNX833X_BASE + 0x1A000)
#define PNX833X_IDE_PORTS_END (PNX833X_BASE + 0x1AFFF)
#define PNX833X_IDE_MODULE_ID PNX833X_REG(0x1AFFC)
#define PNX833X_IDE_MODULE_ID_MODULE_ID_MASK 0xFFFF0000
#define PNX833X_IDE_MODULE_ID_MODULE_ID_SHIFT 16
#define PNX833X_IDE_MODULE_ID_VALUE 0xA009
#define PNX833X_MIU_SEL0 PNX833X_REG(0x2004)
#define PNX833X_MIU_SEL0_TIMING PNX833X_REG(0x2008)
#define PNX833X_MIU_SEL1 PNX833X_REG(0x200C)
#define PNX833X_MIU_SEL1_TIMING PNX833X_REG(0x2010)
#define PNX833X_MIU_SEL2 PNX833X_REG(0x2014)
#define PNX833X_MIU_SEL2_TIMING PNX833X_REG(0x2018)
#define PNX833X_MIU_SEL3 PNX833X_REG(0x201C)
#define PNX833X_MIU_SEL3_TIMING PNX833X_REG(0x2020)
#define PNX833X_MIU_SEL0_SPI_MODE_ENABLE_MASK (1 << 14)
#define PNX833X_MIU_SEL0_SPI_MODE_ENABLE_SHIFT 14
#define PNX833X_MIU_SEL0_BURST_MODE_ENABLE_MASK (1 << 7)
#define PNX833X_MIU_SEL0_BURST_MODE_ENABLE_SHIFT 7
#define PNX833X_MIU_SEL0_BURST_PAGE_LEN_MASK (0xF << 9)
#define PNX833X_MIU_SEL0_BURST_PAGE_LEN_SHIFT 9
#define PNX833X_MIU_CONFIG_SPI PNX833X_REG(0x2000)
#define PNX833X_MIU_CONFIG_SPI_OPCODE_MASK (0xFF << 3)
#define PNX833X_MIU_CONFIG_SPI_OPCODE_SHIFT 3
#define PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_MASK (1 << 2)
#define PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_SHIFT 2
#define PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_MASK (1 << 1)
#define PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_SHIFT 1
#define PNX833X_MIU_CONFIG_SPI_SYNC_MASK (1 << 0)
#define PNX833X_MIU_CONFIG_SPI_SYNC_SHIFT 0
#define PNX833X_WRITE_CONFIG_SPI(opcode, data_enable, addr_enable, sync) \
(PNX833X_MIU_CONFIG_SPI = \
((opcode) << PNX833X_MIU_CONFIG_SPI_OPCODE_SHIFT) | \
((data_enable) << PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_SHIFT) | \
((addr_enable) << PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_SHIFT) | \
((sync) << PNX833X_MIU_CONFIG_SPI_SYNC_SHIFT))
#define PNX8335_IP3902_PORTS_START (PNX833X_BASE + 0x2F000)
#define PNX8335_IP3902_PORTS_END (PNX833X_BASE + 0x2FFFF)
#define PNX8335_IP3902_MODULE_ID PNX833X_REG(0x2FFFC)
#define PNX8335_IP3902_MODULE_ID_MODULE_ID_MASK 0xFFFF0000
#define PNX8335_IP3902_MODULE_ID_MODULE_ID_SHIFT 16
#define PNX8335_IP3902_MODULE_ID_VALUE 0x3902
/* I/O location(gets remapped)*/
#define PNX8335_NAND_BASE 0x18000000
/* I/O location with CLE high */
#define PNX8335_NAND_CLE_MASK 0x00100000
/* I/O location with ALE high */
#define PNX8335_NAND_ALE_MASK 0x00010000
#define PNX8335_SATA_PORTS_START (PNX833X_BASE + 0x2E000)
#define PNX8335_SATA_PORTS_END (PNX833X_BASE + 0x2EFFF)
#define PNX8335_SATA_MODULE_ID PNX833X_REG(0x2EFFC)
#define PNX8335_SATA_MODULE_ID_MODULE_ID_MASK 0xFFFF0000
#define PNX8335_SATA_MODULE_ID_MODULE_ID_SHIFT 16
#define PNX8335_SATA_MODULE_ID_VALUE 0xA099
#endif
arch/mips/include/asm/mach-rc32434/war.h deleted 100644 → 0
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
*/
#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
#define __ASM_MIPS_MACH_MIPS_WAR_H
#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 1
#define MIPS_CACHE_SYNC_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */
arch/mips/include/asm/mach-rm/war.h deleted 100644 → 0
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
*/
#ifndef __ASM_MIPS_MACH_RM_WAR_H
#define __ASM_MIPS_MACH_RM_WAR_H
/*
* The RM200C seems to have been shipped only with V2.0 R4600s
*/
#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 1
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0
#define MIPS_CACHE_SYNC_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MIPS_MACH_RM_WAR_H */
arch/mips/include/asm/mach-sibyte/war.h deleted 100644 → 0
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
*/
#ifndef __ASM_MIPS_MACH_SIBYTE_WAR_H
#define __ASM_MIPS_MACH_SIBYTE_WAR_H
#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#if defined(CONFIG_SB1_PASS_2_WORKAROUNDS)
#ifndef __ASSEMBLY__
extern int sb1250_m3_workaround_needed(void);
#endif
#define BCM1250_M3_WAR sb1250_m3_workaround_needed()
#define SIBYTE_1956_WAR 1
#else
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#endif
#define MIPS4K_ICACHE_REFILL_WAR 0
#define MIPS_CACHE_SYNC_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MIPS_MACH_SIBYTE_WAR_H */
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
*/
#ifndef __ASM_MIPS_MACH_TX49XX_WAR_H
#define __ASM_MIPS_MACH_TX49XX_WAR_H
#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0
#define MIPS_CACHE_SYNC_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 1
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MIPS_MACH_TX49XX_WAR_H */
arch/mips/include/asm/mips-boards/malta.h
View file @ 09a31a7e
......@@ -92,4 +92,6 @@ static inline unsigned long get_msc_port_base(unsigned long reg)
#define MALTA_JMPRS_REG 0x1f000210
extern void __init *malta_dt_shim(void *fdt);
#endif /* __ASM_MIPS_BOARDS_MALTA_H */
arch/mips/include/asm/mipsregs.h
View file @ 09a31a7e
......@@ -389,6 +389,13 @@
#define ST0_CU3 0x80000000
#define ST0_XX 0x80000000 /* MIPS IV naming */
/* in-kernel enabled CUs */
#ifdef CONFIG_CPU_LOONGSON64
#define ST0_KERNEL_CUMASK (ST0_CU0 | ST0_CU2)
#else
#define ST0_KERNEL_CUMASK ST0_CU0
#endif
/*
* Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
*/
......@@ -1706,12 +1713,6 @@ do { \
#define read_c0_count() __read_32bit_c0_register($9, 0)
#define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
#define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */
#define write_c0_count2(val) __write_32bit_c0_register($9, 6, val)
#define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */
#define write_c0_count3(val) __write_32bit_c0_register($9, 7, val)
#define read_c0_entryhi() __read_ulong_c0_register($10, 0)
#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
......@@ -1730,12 +1731,6 @@ do { \
#define read_c0_guestctl0ext() __read_32bit_c0_register($11, 4)
#define write_c0_guestctl0ext(val) __write_32bit_c0_register($11, 4, val)
#define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */
#define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val)
#define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */
#define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val)
#define read_c0_status() __read_32bit_c0_register($12, 0)
#define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
......@@ -2728,7 +2723,7 @@ static inline void tlb_probe(void)
static inline void tlb_read(void)
{
#if MIPS34K_MISSED_ITLB_WAR
#ifdef CONFIG_WAR_MIPS34K_MISSED_ITLB
int res = 0;
__asm__ __volatile__(
......@@ -2750,7 +2745,7 @@ static inline void tlb_read(void)
"tlbr\n\t"
".set reorder");
#if MIPS34K_MISSED_ITLB_WAR
#ifdef CONFIG_WAR_MIPS34K_MISSED_ITLB
if ((res & _ULCAST_(1)))
__asm__ __volatile__(
" .set push \n"
......
arch/mips/include/asm/netlogic/psb-bootinfo.h
View file @ 09a31a7e
......@@ -77,21 +77,6 @@ struct psb_info {
uint64_t avail_mem_map;
};
enum {
NETLOGIC_IO_SPACE = 0x10,
PCIX_IO_SPACE,
PCIX_CFG_SPACE,
PCIX_MEMORY_SPACE,
HT_IO_SPACE,
HT_CFG_SPACE,
HT_MEMORY_SPACE,
SRAM_SPACE,
FLASH_CONTROLLER_SPACE
};
#define NLM_MAX_ARGS 64
#define NLM_MAX_ENVS 32
/* This is what netlboot passes and linux boot_mem_map is subtly different */
#define NLM_BOOT_MEM_MAP_MAX 32
struct nlm_boot_mem_map {
......@@ -102,6 +87,7 @@ struct nlm_boot_mem_map {
uint32_t type; /* type of memory segment */
} map[NLM_BOOT_MEM_MAP_MAX];
};
#define NLM_BOOT_MEM_RAM 1
/* Pointer to saved boot loader info */
extern struct psb_info nlm_prom_info;
......
arch/mips/include/asm/octeon/cvmx-bootinfo.h
View file @ 09a31a7e
......@@ -295,6 +295,8 @@ enum cvmx_board_types_enum {
*/
CVMX_BOARD_TYPE_CUST_PRIVATE_MIN = 20001,
CVMX_BOARD_TYPE_UBNT_E100 = 20002,
CVMX_BOARD_TYPE_UBNT_E200 = 20003,
CVMX_BOARD_TYPE_UBNT_E220 = 20005,
CVMX_BOARD_TYPE_CUST_DSR1000N = 20006,
CVMX_BOARD_TYPE_KONTRON_S1901 = 21901,
CVMX_BOARD_TYPE_CUST_PRIVATE_MAX = 30000,
......@@ -396,6 +398,8 @@ static inline const char *cvmx_board_type_to_string(enum
/* Customer private range */
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MIN)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E100)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E200)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E220)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DSR1000N)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_KONTRON_S1901)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MAX)
......
arch/mips/include/asm/pgtable-bits.h
View file @ 09a31a7e
......@@ -249,11 +249,6 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val)
#define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT)
#elif defined(CONFIG_MACH_INGENIC)
/* Ingenic uses the WA bit to achieve write-combine memory writes */
#define _CACHE_UNCACHED_ACCELERATED (1<<_CACHE_SHIFT)
#endif
#ifndef _CACHE_CACHABLE_NO_WA
......
arch/mips/include/asm/pgtable.h
View file @ 09a31a7e
......@@ -37,8 +37,6 @@ struct vm_area_struct;
_PAGE_GLOBAL | _page_cachable_default)
#define PAGE_KERNEL_NC __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \
_PAGE_GLOBAL | _CACHE_CACHABLE_NONCOHERENT)
#define PAGE_USERIO __pgprot(_PAGE_PRESENT | _PAGE_WRITE | \
_page_cachable_default)
#define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | \
__WRITEABLE | _PAGE_GLOBAL | _CACHE_UNCACHED)
......
arch/mips/include/asm/processor.h
View file @ 09a31a7e
......@@ -29,6 +29,7 @@
*/
extern unsigned int vced_count, vcei_count;
extern int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src);
#ifdef CONFIG_32BIT
#ifdef CONFIG_KVM_GUEST
......
arch/mips/include/asm/r4k-timer.h
View file @ 09a31a7e
......@@ -5,8 +5,8 @@
*
* Copyright (C) 2008 by Ralf Baechle (ralf@linux-mips.org)
*/
#ifndef __ASM_R4K_TYPES_H
#define __ASM_R4K_TYPES_H
#ifndef __ASM_R4K_TIMER_H
#define __ASM_R4K_TIMER_H
#include <linux/compiler.h>
......@@ -27,4 +27,4 @@ static inline void synchronise_count_slave(int cpu)
#endif
#endif /* __ASM_R4K_TYPES_H */
#endif /* __ASM_R4K_TIMER_H */
arch/mips/include/asm/sgi/heart.h
View file @ 09a31a7e
......@@ -264,6 +264,57 @@ struct ip30_heart_regs { /* 0x0ff00000 */
#define HC_NCOR_MEM_ERR BIT(1)
#define HC_COR_MEM_ERR BIT(0)
/*
* HEART has 64 interrupt vectors available to it, subdivided into five
* priority levels. They are numbered 0 to 63.
*/
#define HEART_NUM_IRQS 64
/*
* These are the five interrupt priority levels and their corresponding
* CPU IPx interrupt pins.
*
* Level 4 - Error Interrupts.
* Level 3 - HEART timer interrupt.
* Level 2 - CPU IPI, CPU debug, power putton, general device interrupts.
* Level 1 - General device interrupts.
* Level 0 - General device GFX flow control interrupts.
*/
#define HEART_L4_INT_MASK 0xfff8000000000000ULL /* IP6 */
#define HEART_L3_INT_MASK 0x0004000000000000ULL /* IP5 */
#define HEART_L2_INT_MASK 0x0003ffff00000000ULL /* IP4 */
#define HEART_L1_INT_MASK 0x00000000ffff0000ULL /* IP3 */
#define HEART_L0_INT_MASK 0x000000000000ffffULL /* IP2 */
/* HEART L0 Interrupts (Low Priority) */
#define HEART_L0_INT_GENERIC 0
#define HEART_L0_INT_FLOW_CTRL_HWTR_0 1
#define HEART_L0_INT_FLOW_CTRL_HWTR_1 2
/* HEART L2 Interrupts (High Priority) */
#define HEART_L2_INT_RESCHED_CPU_0 46
#define HEART_L2_INT_RESCHED_CPU_1 47
#define HEART_L2_INT_CALL_CPU_0 48
#define HEART_L2_INT_CALL_CPU_1 49
/* HEART L3 Interrupts (Compare/Counter Timer) */
#define HEART_L3_INT_TIMER 50
/* HEART L4 Interrupts (Errors) */
#define HEART_L4_INT_XWID_ERR_9 51
#define HEART_L4_INT_XWID_ERR_A 52
#define HEART_L4_INT_XWID_ERR_B 53
#define HEART_L4_INT_XWID_ERR_C 54
#define HEART_L4_INT_XWID_ERR_D 55
#define HEART_L4_INT_XWID_ERR_E 56
#define HEART_L4_INT_XWID_ERR_F 57
#define HEART_L4_INT_XWID_ERR_XBOW 58
#define HEART_L4_INT_CPU_BUS_ERR_0 59
#define HEART_L4_INT_CPU_BUS_ERR_1 60
#define HEART_L4_INT_CPU_BUS_ERR_2 61
#define HEART_L4_INT_CPU_BUS_ERR_3 62
#define HEART_L4_INT_HEART_EXCP 63
extern struct ip30_heart_regs __iomem *heart_regs;
#define heart_read ____raw_readq
......
arch/mips/include/asm/stackframe.h
View file @ 09a31a7e
......@@ -450,7 +450,7 @@
*/
.macro CLI
mfc0 t0, CP0_STATUS
li t1, ST0_CU0 | STATMASK
li t1, ST0_KERNEL_CUMASK | STATMASK
or t0, t1
xori t0, STATMASK
mtc0 t0, CP0_STATUS
......@@ -463,7 +463,7 @@
*/
.macro STI
mfc0 t0, CP0_STATUS
li t1, ST0_CU0 | STATMASK
li t1, ST0_KERNEL_CUMASK | STATMASK
or t0, t1
xori t0, STATMASK & ~1
mtc0 t0, CP0_STATUS
......@@ -477,7 +477,7 @@
*/
.macro KMODE
mfc0 t0, CP0_STATUS
li t1, ST0_CU0 | (STATMASK & ~1)
li t1, ST0_KERNEL_CUMASK | (STATMASK & ~1)
#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
andi t2, t0, ST0_IEP
srl t2, 2
......
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