ppc64: some small optimisations

arch/ppc64/kernel/htab.c

@@ -333,7 +333,7 @@ int __hash_page(unsigned long ea, unsigned long access, unsigned long vsid,
 					  hpteflags, 0, large);
 
 		/* Primary is full, try the secondary */
-		if (slot == -1) {
+		if (unlikely(slot == -1)) {
 			pte_val(new_pte) |= 1 << 15;
 			hpte_group = ((~hash & htab_data.htab_hash_mask) *
 				      HPTES_PER_GROUP) & ~0x7UL; 
@@ -393,6 +393,7 @@ int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
 		mm = &init_mm;
 		vsid = get_kernel_vsid(ea);
 		break;
+#if 0
 	case EEH_REGION_ID:
 		/*
 		 * Should only be hit if there is an access to MMIO space
@@ -404,6 +405,7 @@ int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
 		 * Should never get here - entire 0xC0... region is bolted.
 		 * Send the problem up to do_page_fault 
 		 */
+#endif
 	default:
 		/* Not a valid range
 		 * Send the problem up to do_page_fault 

include/asm-ppc64/processor.h

@@ -725,17 +725,17 @@ static inline void prefetchw(const void *x)
 
 #define spin_lock_prefetch(x)	prefetchw(x)
 
-#define cpu_has_largepage()	(__is_processor(PV_POWER4) || \
-				 __is_processor(PV_POWER4p))
+#define cpu_has_largepage()	(processor_type() == PV_POWER4 || \
+				 processor_type() == PV_POWER4p)
 
-#define cpu_has_slb()		(__is_processor(PV_POWER4) || \
-				 __is_processor(PV_POWER4p))
+#define cpu_has_slb()		(processor_type() == PV_POWER4 || \
+				 processor_type() == PV_POWER4p)
 
-#define cpu_has_tlbiel()	(__is_processor(PV_POWER4) || \
-				 __is_processor(PV_POWER4p))
+#define cpu_has_tlbiel()	(processor_type() == PV_POWER4 || \
+				 processor_type() == PV_POWER4p)
 
-#define cpu_has_noexecute()	(__is_processor(PV_POWER4) || \
-				 __is_processor(PV_POWER4p))
+#define cpu_has_noexecute()	(processor_type() == PV_POWER4 || \
+				 processor_type() == PV_POWER4p)
 
 #endif /* ASSEMBLY */
 

include/asm-ppc64/system.h

@@ -105,13 +105,20 @@ extern void dump_regs(struct pt_regs *);
 	!(flags & MSR_EE);			\
 })
 
-static __inline__ int __is_processor(unsigned long pv)
+static inline int __is_processor(unsigned long pv)
 {
 	unsigned long pvr;
-      asm volatile("mfspr %0, 0x11F" : "=r" (pvr)); 
+	asm("mfspr %0, 0x11F" : "=r" (pvr)); 
 	return(PVR_VER(pvr) == pv);
 }
 
+static inline int processor_type(void)
+{
+	unsigned long pvr;
+	asm ("mfspr %0, 0x11F" : "=r" (pvr)); 
+	return(PVR_VER(pvr));
+}
+
 /*
  * Atomic exchange
  *

include/asm-ppc64/uaccess.h

@@ -131,7 +131,7 @@ do {								\
  */
 #define __put_user_asm(x, addr, err, op)			\
 	__asm__ __volatile__(					\
-		"1:	"op" %1,0(%2)\n"			\
+		"1:	"op" %1,0(%2)  	# put_user\n" 	 	\
 		"2:\n"						\
 		".section .fixup,\"ax\"\n"			\
 		"3:	li %0,%3\n"				\
@@ -179,7 +179,7 @@ do {								\
 
 #define __get_user_asm(x, addr, err, op)		\
 	__asm__ __volatile__(				\
-		"1:	"op" %1,0(%2)\n"		\
+		"1:	"op" %1,0(%2)	# get_user\n"  	\
 		"2:\n"					\
 		".section .fixup,\"ax\"\n"		\
 		"3:	li %0,%3\n"			\